HK1063121B - Method and apparatus for improved detection of rate errors in variable rate receivers - Google Patents

Description

Method and apparatus for improved rate error detection in a variable rate receiver

Technical Field

Technical Field

The disclosed embodiments relate to wireless communications, and more particularly, to a novel and improved method and apparatus for detecting errors in rate measurements used for encoding transmitted data at a receiver of a variable rate communication system.

Technical Field

Fig. 1 IS a diagram of exemplary steps of a variable rate CDMA transmission system 10 as described in the communications industry association spanning the air interface standard TLA/ELA transition standard 95 and variants thereof, such as IS-95B (hereinafter collectively referred to as IS-95). For example, the transmission system may be provided in a base station of a cellular transmission system for transmitting signals to mobile telephone users in a cell surrounding the base station. It may also be located in a mobile telephone subscriber unit for transmitting signals to a base station.

The speech signal is detected by microphone 11 and then sampled and digitized by an analog-to-digital converter (not shown). Variable rate data source 12 receives digitized samples of a speech signal, encodes the signal, and provides encoded speech packets of equal frame length. For example, the variable rate data source 12 may use Linear Predictive Coding (LPC) techniques to convert digitized samples of the input speech into digitized speech parameters that represent the input speech signal. In an exemplary embodiment, the variable rate data source is a variable rate vocoder as described in detail in U.S. Pat. No. 5,414,796, which is assigned to the assignee of the present invention and is incorporated herein by reference. The variable rate data source 12 operates at four possible frame rates: 9600 bits per second (bps), 4800 bits per second, 2400 bits per second, and 1200 bits per second (referred to herein as full rate, half rate, 1/4 rate, and 1/8 rate) provide variable rate data packets. Data packets encoded at full rate contain 172 information bits, data packets encoded at half rate contain 80 information bits, data packets encoded at 1/4 rate contain 40 information bits, and data packets encoded at 1/8 rate contain 16 information bits. The format of the data packets is shown in fig. 2A-2D. The data packets, regardless of their size, are all one frame length of 20 milliseconds in duration. "frame" and "data packet" may be used interchangeably herein.

Encoding and transmission of data packets at different rates compresses the data contained therein based in part on the complexity or amount of information the frame represents. For example, if the input voice signal includes little or no deviation, perhaps because the speaker is not speaking, the information bits of their corresponding data packets may be compressed and encoded at the 1/8 rate. This compression causes a loss of resolution of the corresponding portion of the speech signal, but, assuming that the corresponding portion of the speech signal contains little or no information, a reduction in signal resolution is generally not noticed. Alternatively, if the corresponding input voice signal of the data packet includes much information, perhaps because the speaker is actively speaking, the data packet is encoded at full rate and the compression of the input speech is reduced to achieve better voice quality.

Such compression and encoding techniques are typically used to limit the amount of information transmitted at any one time so that the overall bandwidth of the transmission system can be used more efficiently, e.g., more telephone calls can be handled at any one time.

Variable rate data packets generated by a data source 12 are provided to a packetizer 13 which selectively adds Cyclic Redundancy Check (CRC) bits and tail bits. As shown in fig. 2A, when the variable-rate data source 12 encodes frames at full rate, the packetizer 13 generates and adds 12 CRC bits and 8 tail bits. Also, as shown in fig. 2B, when the variable-rate data source 12 encodes a frame at a half-rate, the packetizer 13 generates and adds 8 CRC bits and 8 tail bits. As shown in fig. 2C, when the variable rate data source 12 encodes a frame at 1/4 rates, the packetizer 13 generates and adds 8 tail bits. As shown in fig. 2D, when the variable rate data source 12 encodes a frame at 1/8 rates, the packetizer 13 generates and adds 8 tail bits.

The variable rate packets from packetizer 13 are then provided to encoder 14, which encodes the bits of the variable rate data packets for error detection and correction purposes. In an exemplary embodiment, encoder 14 is a rate 1/3 convolutional encoder. The convolutionally encoded symbols are then provided to a CDMA spreader 16, the implementation of which is described in detail in U.S. Pat. nos. 5,103,459 and 4,901,307. The CDMA spreader 16 converts the 8 coded symbols into 64-bit walsh symbols and then spreads the walsh symbols according to a pseudo-random noise (PN) code.

The repetition generator 17 receives the extended data packet. For data packets less than full rate, the repetition generator 17 generates copies of the symbols in the data packet to provide a constant data rate data packet. When the variable rate data packet is at half rate, the repetition generator 17 introduces 2 redundant bit factors, i.e. each spreading symbol is repeated twice in the output data packet. When the variable rate data packet is at 1/4 rates, the repetition generator 17 introduces 4 redundant bit factors. When the variable rate data packet is at 1/8 rates, the repetition generator 17 introduces 8 redundant bit factors.

The repetition generator 17 provides the redundancy described above by dividing the spread data packet into smaller sub-packets called "power control groups". In the exemplary embodiment, each power control group includes 6 PN-spread walsh symbols. A constant rate frame may be generated by continuously repeating each power control group as many times as necessary to fill the frame as described above.

The spread data packet is then provided to a data burst randomizer 18 which removes redundancy from the spread data packet in accordance with the pseudo-random process described in U.S. patent 5,535,239, assigned to the assignee of the present invention. The data burst randomizer 18 selects one of the power control groups for transmission according to a pseudo-random selection process and gates the other redundant copy of the power control group.

The data packets are provided by a data burst randomizer 18 to a Finite Impulse Response (FIR) filter 20, an example of which is described in U.S. patent 5,659,569, which is assigned to the assignee of the present invention. The filtered signal is then provided to a digital-to-analog converter 22 and converted to an analog signal. The analog signal is then provided to a transmitter 24, which upconverts and amplifies the signal for transmission via an antenna 26.

Figure 3 shows relevant components of a base station. In another embodiment, the apparatus of FIG. 3 may reside in a mobile phone 28 or other mobile station that receives the transmitted signal. The signal is received by an antenna 30 and, if necessary, down-converted and amplified by a receiver 32. The signal is then supplied to a frame rate detection unit 33 which subdivides the signal into data packets and determines the respective frame rate for each data packet. Depending on the implementation, the frame rate may be determined by detecting the duration of each bit. The data packet and a signal identifying the determined frame rate of the data packet are then sent to the CRC unit 34 for a cyclic redundancy check or associated error detection check in an attempt to verify that no transmission errors or frame rate detection errors have occurred. Frame rate detection errors result in sampling the data packet at the wrong rate, causing the order of the bits to be virtually random. Transmission errors typically result in only one or two bit errors. In general, if a transmission error or a frame rate detection error is generated, the CRC unit detects the error. The "bad" frames that do not pass the CRC are deleted or discarded by the frame deletion unit 36. The "good" frames passing the CRC are routed to the variable rate decoder 40 and converted back to digitized voice signals. The digitized voice signal is converted to an analog signal by an analog-to-digital converter (not shown) and passed through the speaker of the mobile telephone as the final output.

Depending on the implementation, a separate frame deletion unit 36 is not necessary. Rather, CRC unit 34 is configured to simply not output the corrupted frame to variable rate decoder 40. However, the provision of a frame erasure unit facilitates the generation of a frame erasure signal that is sent back to the base station to inform the base station of frame erasure errors. The base station may utilize the frame erasure information to adjust the amount of power used to transmit the signal, perhaps as part of a feedback system intended to minimize transmit power while minimizing frame errors.

As described above, by varying the frame rate of the packets of information to compress the information contained therein, the overall bandwidth of the system can be more efficiently utilized, generally without any noticeable effect on the transmitted signal. However, occasionally, a problem arises in that noticeable effects occur. This problem occurs if frames subject to frame rate detection errors or transmission errors still pass the CRC. In this case, the bad frame is not erased but processed with other good frames. The error may be noticeable and may be unnoticeable. For example, if the error is a transmission error where only one or two bits in the encoded speech are erroneous, the error may be very small without any noticeable effect on the output voice signal. However, if the error is a frame rate detection error, the entire data packet will be processed using an incorrect frame rate, in effect causing random bits to be input to the decoder, likely resulting in noticeable artifacts in the output speech signal. Noticeable artifacts caused by frame rate determination errors are unacceptable distortions such as screeches and beeps. For some systems, it has been found that this incorrect frame rate detection occurs with a probability of about 0.005%, producing incorrectly received packets and corresponding artifacts in the output voice signal every 16 minutes of talk time. Although a CDMA system employing IS-95 protocol has been described, similar problems occur in almost any transmission system and related systems that use variable transmission rates.

The Rate Determination Algorithm (RDA) of the frame rate detection unit 33 does not guarantee that the received frame rate is correct due to the effects of channel conditions, such as noise, multipath fading, on the reception parameters. Given that this is a limitation of RDAs, it is desirable to ensure that such RDA errors do not cause audible artifacts such as screech or beeps. When a received frame is not suitable for accurate rate determination due to poor channel conditions, the RDA either determines that the frame must be erased or assigns an incorrect rate to the data packet. Typically, speech decoders have frame erasure processing mechanisms that use past frames to perceptually level lost frames to produce speech that is not annoying to the listener. But instead. If no frame erasure is employed, the RDA assigns an incorrect rate to the frame and feeds the random bits to the variable rate decoder 40. Unless detected, the random bits can produce very large and loud artifacts such as screeches and beeps. Frame erasure does not produce more degradation in speech quality than an incorrect rate frame, and is generally correct.

It is desirable to process these incorrect rate frames without audio artifacts. It may be desirable to detect incorrect rate frames, perform frame erasure processing, and/or clear the memory state in the variable rate decoder 40 so that the effects of incorrect rate determinations do not propagate over many frames.

It can therefore be appreciated that there is a significant need for a method of detecting rate determination errors and eliminating generated audible artifacts in a wireless communication system,

summary of The Invention

The disclosed embodiments are directed to a system and method for detecting rate determination algorithm errors in a variable rate communication system receiver (fig. 4). Accordingly, a method of detecting rate errors in a variable rate receiver is described, the method comprising receiving an encoded speech signal, performing a rate determination algorithm on the speech signal to provide a coding rate, and detecting errors in the provided rate.

In another embodiment, a rate error detection system is described that includes a receiver that receives an encoded speech signal, a rate determination element that performs a rate determination algorithm on the speech signal to provide an encoded rate, and a rate error detector that detects errors in the provided rate.

Brief description of the drawings

The features, objects, and advantages of the disclosed embodiments will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. The same numbers refer to the same parts and things throughout the drawings, wherein:

FIG. 1 is a schematic step diagram of a conventional transmit portion of a base station of a digital cellular telephone system;

FIGS. 2A-2D are diagrams of conventional frame formats employed by the system of FIG. 1;

FIG. 3 is a schematic illustration of the steps of a conventional receive portion of a cellular telephone configured to receive signals transmitted by the system of FIG. 1, but not in accordance with the disclosed embodiments;

FIG. 4 is a schematic diagram of the steps of a receive portion of a mobile subscriber unit configured in accordance with an embodiment of the disclosed rate error detector for receiving signals transmitted by the system of FIG. 1;

FIG. 5 is a flow chart of a method of detecting frame rate errors identified as full rate frames;

FIG. 6 is a flow chart of a method of detecting frame rate errors identified as half-rate frames;

FIG. 7 is a flow chart of a method of detecting frame rate errors for frames identified as rate 1/4;

FIG. 8 is a flow chart of a method of detecting frame rate errors for frames identified as rate 1/8; and

fig. 9 is a graph illustrating an exemplary fixed codebook gain versus LPC threshold curve.

Detailed description of the preferred embodiments

An improved exemplary embodiment of rate error detection in a variable rate receiver is implemented in a variable mode vocoder (SMV). The SMV IS a variable rate vocoder and IS selected for use in third generation CDMA systems, IS 2000. The SMV vocoder algorithm uses many parameters such as source-controlled rate, frame type, LP coefficients, adaptive and fixed codebook parameters. The amount of perceptual information contained in the speech to be encoded is analyzed. This analysis classifies speech into various types, such as background noise, stationary unvoiced, stationary voiced, and non-stationary speech (onset, transient, etc.). The inter-speech background noise is encoded at rate 1/8. The fixed unvoiced is encoded with a 1/4 rate noise-excited linear prediction (NELP) scheme. Fixed voiced sounds are encoded using either full-rate or half-rate CELP-1 type schemes. Non-stationary speech is encoded using either a full-rate or half-rate CELP-0 type scheme. The type information controls several aspects of the frame coding, such as the subframe size, the parameters used for the speech display and the coding scheme of these parameters. Type 0 frames, whose typical parameters such as pitch dependency and pitch lag can vary rapidly, are "non-periodic" frames. Thus, in CELP-0 type, the pitch lag is encoded and transmitted often (i.e., every subframe). Type 1 frames are "periodic" frames that have a high periodicity and are well perceptually displayed with a smooth pitch track. In the CELP-1 type, the pitch lag is encoded once per frame, and the interpolated pitch track is derived from this lag. Due to the high periodicity and the smooth pitch track, the pitch gain exhibits a very stable performance, being quantized together. One bit of each stationary voiced and non-stationary speech frame is used to indicate the CELP scheme type.

Those skilled in the art will recognize that: SMVs may be implemented using field programmable gate arrays (EPGAs), Programmable Logic Devices (PLDs), Digital Signal Processors (DSPs), one or more microprocessors, Application Specific Integrated Circuits (ASICs), or other devices capable of performing the SMV functions described above.

The disclosed embodiments are described in the context of a CDMA telephone. However, it should be understood that the disclosed embodiments may be applied to other types of communication systems and modulation techniques, such as Personal Communication Systems (PCS), Wireless Local Loops (WLL), private branch exchanges (PBX), or other known systems. Also, systems using other well-known transmission modulation schemes such as TDMA and FDMA, as well as other spread spectrum systems, can use the disclosed embodiments.

Figure 4 shows relevant components of a mobile subscriber unit 28 or other mobile station receiving signals provided by a base station transmission system, such as the system of figure 1, in which signals having variable rate data packets are transmitted, according to one embodiment. The frame rates include full rate, half rate, 1/4 rate, and 1/8 rate as in fig. 2A-2D. The data packet includes encoded speech parameters representative of a compressed speech signal. In addition, each data packet includes CRC bits and/or encoder tail bits. Additional details regarding the contents of the data packet have been provided above in conjunction with FIG. 1 and in U.S. Pat. No. 5,414,796, incorporated by reference above.

The components shown in fig. 4 are similar to those of fig. 3, only the relevant differences will be described in detail. The transmitted signal is received by an antenna 30 and down-converted and amplified by a receiver 32. The signal is then provided to a frame rate detection unit 33 which attempts to determine the respective frame rate of the data packets using a Rate Determination Algorithm (RDA). The data packet is then provided to a CRC unit 34 which performs a cyclic redundancy check on the frames of the received signal in an attempt to determine that no frame rate detection error or transmission error has occurred. Frames that do not pass the CRC, i.e., bad frames, are erased by the frame eraser 36. As described above, there is no need for a separate frame erasure unit, but rather, as long as a frame with a CRC error is not output from the CRC unit 34. In either case, frames passing the CRC, i.e., possibly good frames, are routed to the rate error detector 38. Depending on the implementation, there is no need for a separate rate error detector unit 38, but instead the rate error detector unit 38 may be implemented in the SMV or integrated with other receiver components.

The rate error detector unit 38 further checks the frames to verify that the frame rate detected by the RDA of the frame rate detection unit 33 is indeed correct. The full rate, half rate, 1/4 rate and 1/8 rate frames are further verified by the rate error detector 38 using the verification method for these frames as described in detail below in connection with fig. 5-8. Frames that fail verification may be erased by frame erase unit 36 and frames that fail verification may be processed to clear the memory state in variable rate decoder 40 so that distortion does not spread over many frames. The rate, control and frame information is output from the rate error detector 38 to the variable rate decoder 40 for the erasure process. The frames checked by the rate error detector are routed directly to the variable rate decoder 40.

The variable rate decoder 40 processes the frames by decoding the speech parameters contained in the frames and reconverts them back to digitized voice signals. When the receiver is a mobile subscriber unit, the digitized voice signal is ultimately converted to an analog signal by a digital-to-analog converter (not shown) for output to a listener via speaker 42. When the receiver is a base station, the digital signal will propagate further in the wireless system.

Fig. 5-8 detail the method of frame rate error checking with the rate error detector (fig. 4, element 38) according to the full rate, half rate, 1/4 rate and 1/8 rate embodiments. The checking method adopts new methods such as illegal classification conversion of rated speed and type frames, check of reserved bits, illegal filtering type check and analysis of Fixed Code Book (FCB) and LPC threshold gain curve and the like. In addition, the embodiments disclosed in FIGS. 5-8 employ new approaches to frame erasure processing and storage state control to mitigate the effects of detected frame rate errors.

The disclosed embodiments apply a novel state transition structure to rate conversion of successive frames based on speech classification and speech characteristics of conversational speech. Rate transitions that violate this structure are illegal and are used to detect rate errors. Defining these illegal rate conversions includes:

a full rate frame followed by an 1/8 rate frame;

a full rate, type 1 frame followed by an 1/8 rate frame;

a half-rate, type 1 frame followed by a rate 1/8 frame;

an 1/4 rate frame followed by a type 1 full rate frame;

an 1/4 rate frame followed by a type 1 half rate frame;

an 1/8 rate frame followed by a type 1 full rate frame;

an 1/8 rate frame followed by a type 1 half rate frame;

an 1/8 rate frame followed by a 1/4 rate frame followed by a 1/8 rate frame;

1/8 rate frames followed by half rate frames followed by 1/8 rate frames; and

an 1/8 rate frame followed by a full rate frame followed by a 1/8 rate frame.

Depending on the current and past frame rates and types, the presence of illegal transforms indicates an RDA error in the current frame or in the past frame.

The disclosed embodiments employ new approaches of full rate and 1/4 rate reserved transmit bits to detect RDA errors. A full rate data packet has 171 information bits per 20 millisecond frame, of which 1 bit is a reserved bit. The reserved bits are used by a rate error detector (fig. 4, element 38) to determine whether the received reserved bits have the desired fixed code value. Failure to receive the expected reserved bits indicates the RDA error in the current full-rate frame. The 1/4 rate packet has 40 information bits per 20 ms frame, with NELP using 39 bits and 1 bit unused. Also, the decoder may set the unused bits to a fixed value of 0 or 1. The rate error detector (fig. 4, element 38) checks the unused bits to determine if the received unused bits have the desired fixed encoded value. Failure to receive the expected unused bits indicates the RDA error in the current 1/4 rate frame.

The disclosed embodiments employ a new approach of illegal filtering type checking on 1/4 rate NELP frames to detect rate errors. NELP coding uses one of 3 different shaping filters for spectral shaping of the pseudo-random excitation. Two bits are used to transmit the index of the selected filter. 3 of the two-bit address forms are used to identify the selected shaping filter, leaving the fourth two-bit address form unused or illegal. The absence of use or the presence of an illegal address form indicates an RDA error in the current 1/4 rate NELP frame.

The disclosed embodiments employ a new approach to coding parameters to determine rate error. Investigation of the effect of RDA errors on vocoders revealed that artifacts such as audible tones like screams and beeps are primarily caused by excessively high FCB gain values accompanied by high LPC prediction gain values. When the coding parameter analysis is performed by the encoder, natural speech produces FCB gain and LPC prediction gain that are inversely proportional to each other. In other words, when the LPC gain is large, the FCB gain is generally small, and when the LPC gain is small, the FCB gain is generally large.

The inverse proportional relationship of the FCB gain and LPC gain in natural speech produces a curve in the graph of FCB gain and LPC gain over which no good natural speech appears. The FCB gain, and therefore the graph, should be a function of the input speech level. Frames received at a level above the curve on which good natural speech does not occur represent rate errors in the frame. When a rate error is detected on the graph, a new way to eliminate the difference due to the input level is to normalize the FCB gain using the average energy value calculated from the past frame. Figure 9 is a scattering curve showing the relationship between normalized FCB gain and LPC prediction gain. The circles below the solid curves are produced by the clear speech, and the asterisks above the solid correspond to unacceptable screaming sounds caused by the RDA. The solid line represents a threshold curve that separates good speech areas from unacceptable screaming sounds or other artifacts. This threshold can conveniently be represented parametrically and input to the rate error detector (fig. 4, element 38). After the FCB gain and LPC gain have been established for the received data packet, a check can be made to determine if the frame is below the threshold curve. If the frame is not below the threshold curve, it represents a screaming sound generated by the RDA error.

The disclosed embodiments employ an eighth rate excitation gain to detect the rate error approach. Because the eighth rate coding scheme is only used for the background noise portion of speech, there is an upper limit to the excitation energy that is quantized using the gain parameter. When the excitation gain is obtained from a received data packet, a check may be made to see if the excitation gain is below the upper limit of the gain parameter. If the gain parameter is not below the upper limit, then an RDA error is indicated.

When any of the disclosed detection mechanisms show a rate error in a current frame or in an immediately preceding frame, the disclosed embodiments may employ one or more novel schemes in canceling total distortion and/or preventing distortion from spreading over multiple frames when decoding. The scheme includes frame erasure processing, lowering FCB gain, and resetting of storage state.

Vocoders typically have an inherent procedure to handle frame erasures. The disclosed embodiments may use this frame erasure process for any frame in which the rate error detector (fig. 4, element 38) has detected an RDA error. The frame erasure processes the synthesized speech without using any information from the current frame and derives all decoder parameters from past memory to produce perceptually stationary speech relative to the previous frame.

When a rate error is detected due to the reception of a frame at the upper level of the FCB versus LPC gain curve where good natural speech does not occur, the decoder (fig. 4, element 40) can force the FCB gain down to a small value to prevent a high energy chirp or beep from being generated at the output of the decoder (fig. 4, element 40).

Vocoder algorithms typically reconstruct speech using past memory states. These memory states include the FCB-by-displacement-average vector quantizer (MAVQ) memory, the excitation memory, the LPC synthesis memory, and the post-filter synthesis memory. Undetected RDA errors may add bad values to these memories. The effect of bad values may persist many frames into the future, even if all future frames are normal frames. To prevent corruption of future frames, such as the detected RDA error described in the current or immediately preceding frame, the FCB gain MAVQ memory, the excitation memory, the LPC synthesis filter memory and the post-filter synthesis filter memory may be reset to predetermined values that do not produce high-energy screams. In one embodiment, the memory values are overwritten with zeros. In another embodiment, the memory values are overwritten with the corresponding initial values of the memory.

Fig. 5 illustrates a method of detecting rate errors in frames identified as full-rate frames by RDA, in accordance with an embodiment. Those skilled in the art will appreciate that the order of the steps shown in fig. 5 is not constrained. The method may be readily modified by omitting illustrated steps or by reordering the order of the steps without departing from the scope of the disclosed embodiments.

In step 502, the rate error detector inputs a frame of data determined by the RDA to be a full-rate frame. Control flows to step 504.

In step 504, the reserved or normal bits are tested to determine if the received value is equal to the fixed value set by the encoder. If the bit is not equal to the fixed value set by the encoder, indicating a frame rate error, the control flow goes to step 506. Otherwise, control flow proceeds to step 510.

In step 506, a frame erasure process and/or a memory state resetting process is performed. The flow of control proceeds to step 508 where decoding continues.

In step 510, the frame is checked to determine if it is a frame type. If the frame is a type 0 frame, control flow proceeds to step 512. If the frame is a type 1 frame, control flows to step 520.

In step 512, for a type 0 frame, the FCB and LPC gains are established for the frame and a check is made to determine if the frame is below the threshold curve. If the frame is below the threshold curve, then control flows to step 514 where decoding continues. If the frame is not below the threshold curve, control flows to step 516.

In step 516, a frame erasure process and/or FCB gain reduction and/or memory state reset process may be performed. The flow of control proceeds to step 518 where decoding continues.

In step 520, for type 1 frames, the previous frame is checked to determine whether the frame is an 1/8 rate frame or 1/4 rate frame. If the previous frame is not an 1/8 rate frame or a 1/4 rate frame, indicating a legal rate transformation, control flows to step 526 where full frame decoding continues. If the previous frame is an 1/8 rate frame or a 1/4 rate frame, indicating an illegal rate transformation, control flows to step 522.

In step 522, a frame erasure process and/or a memory state reset process may be performed. The flow of control proceeds to step 524 where decoding continues.

Fig. 6 illustrates a method of detecting a rate error in a frame identified by RDA as a field rate, according to an embodiment. Those skilled in the art will appreciate that the order of the steps shown in fig. 6 is not constrained. The method may be conveniently modified by omitting the steps or by reordering the steps without departing from the scope of the embodiments.

In step 602, the rate error detector inputs a frame of data determined by the RDA to be a half-rate frame. The flow of control proceeds to step 604.

In step 604, the frame is tested for frame type. If the frame is a type 0 frame, control flow proceeds to step 606. If the frame is a type 1 frame, control flow proceeds to step 614.

In step 606, for a type 0 frame, the FCB and LPC gains are established for the frame and a check is made to determine if the frame is below the threshold curve. If the frame is below the threshold curve, control flows to step 610 where decoding continues. If the frame is not below the threshold curve, control flows to step 608.

In step 608, a frame erasure process and/or an FCB gain reduction and/or a memory state reset process may be performed. The flow of control proceeds to step 612 where decoding continues.

In step 614, for type 1 frames, the previous frame is checked to determine whether the frame is an 1/8 rate frame or 1/4 rate frame. If the previous frame is not an 1/8 rate frame or a 1/4 rate frame, indicating a legal rate transformation, control flows to step 620 where half-frame decoding continues. If the previous frame is not an 1/8 rate frame or a 1/4 rate frame, indicating an illegal rate transformation, control flows to step 616.

In step 616, a frame erasure process and/or a memory state reset process may be performed. The flow of control proceeds to step 618 where decoding continues.

Fig. 7 illustrates a method of detecting a rate error in a frame identified by RDA as a rate 1/4 frame, in accordance with an embodiment. Those skilled in the art will appreciate that the order of the steps shown in fig. 7 is not constrained. The method may be conveniently modified by omitting the steps or by reordering the steps without departing from the scope of the embodiments.

In step 702, the rate error detector inputs a frame of data determined by the RDA to be an 1/4 rate frame. The flow of control proceeds to step 704.

In step 704, the reserved or normal bits are tested to determine if the received value is equal to the fixed value set by the encoder. If the bit is not equal to the fixed value set by the encoder, indicating a frame rate error, the control flow goes to step 706. Otherwise, control flow proceeds to step 710.

In step 710, a frame erasure process and/or a memory state reset process may be performed. The flow of control proceeds to step 708 where decoding continues.

In step 710, a two-bit pattern is used to identify whether the selected shaping filter is valid. If the two-bit mode is valid, control flows to step 716 where rate 1/4 decoding continues. If the two-bit pattern is not valid, control flows to step 712.

In step 712, a frame erasure process and/or a memory state reset process is performed. The flow of control proceeds to step 714 where decoding continues.

Fig. 8 illustrates a method of detecting a rate error in a frame identified by RDA as a rate 1/8 frame, in accordance with an embodiment. Those skilled in the art will appreciate that the order of the steps shown in fig. 8 is not limited. The method may be conveniently modified by omitting the steps or by reordering the steps without departing from the scope of the embodiments.

In step 802, the rate error detector inputs a data frame that is determined by the RDA to be an 1/8 rate frame. Control flows to step 804.

In step 804, the previous frame is checked to determine if the frame is a full rate frame. If the previous frame is not a full rate frame, indicating a legitimate rate transition, control flows to step 810. If the previous frame is not a full rate frame, indicating an illegal rate change, the flow of control proceeds to step 806.

In step 806, a frame erasure process and/or a memory state resetting process is performed. The flow of control proceeds to step 808 where decoding continues.

In step 810, the previous frame is checked to determine whether the frame is an 1/4 rate frame, a half rate frame, or a full rate frame. If the previous frame is an 1/4 rate frame, a half rate frame, or a full rate frame, indicating a possible illegal rate change, control flows to step 820. If the previous frame is not an 1/4 rate frame, a half rate frame, or a full rate frame, indicating a legal 1/8 rate transformation, control flows to step 812.

In step 812, the rate excitation gain is compared 1/8 to a maximum threshold. If the 1/8 rate excitation gain is less than the threshold, then control flow proceeds to step 818 where rate 1/8 decoding continues. If 1/8 the excitation gain is greater than the threshold, indicating a rate error, control flows to step 814.

In step 814, a frame erasure process and/or a memory state resetting process is performed. The flow of control proceeds to step 816 where decoding continues.

In step 820, the second frame before the first is checked to determine if the frame is an 1/8 rate frame. If the previous second frame is not an 1/8 rate frame, indicating a legal rate transformation, control flows to step 826. If the previous frame was an 1/8 rate frame, indicating an illegal rate change, control flows to step 822.

In step 822, a frame erasure process and/or a memory state reset process may be performed. The flow of control proceeds to step 824 where decoding continues.

In step 826, the previous frame is checked to determine whether the frame is a half rate 1 type frame or a full rate 1 type frame. If the previous frame is not a half rate 1 or full rate 1 frame, indicating a legal rate transition, control flows to step 832. If the previous frame is a half rate 1 or full rate 1 frame, indicating illegal rate conversion, the flow of control goes to step 828.

In step 828, a frame erasure process and/or a memory state reset process may be performed. The flow of control proceeds to step 830 where decoding continues.

In step 832, the 1/8 rate excitation gain is compared to a maximum threshold. If the 1/8 rate excitation gain is less than the threshold, then control flow proceeds to step 838 where rate decoding continues 1/8. If 1/8 the excitation gain is greater than the threshold, indicating a rate error change, control flows to step 834.

In step 834, a frame erasure process and/or a memory state resetting process may be performed. The flow of control proceeds to step 836 where decoding continues.

Fig. 9 shows a scattering curve for the relationship between normalized FCB gain and LP prediction gain. The circle below the solid curve is produced by clear speech and the asterisk above the solid corresponds to unacceptable screaming sounds caused by RDA. The solid curve represents a threshold curve that separates good speech areas from unacceptable screaming sounds or other artifacts. This threshold can conveniently be parametrically expressed and input to the rate error detector.

There has thus been described a novel and improved method and apparatus for rate error detection in a variable rate receiver. Those of skill in the art would appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans recognize the interchangeability of hardware and software under these circumstances, and how best to implement the described functionality for each particular application. By way of example, the logical block diagrams, modules, circuits, and algorithm steps illustrated in the various embodiments described herein may be implemented with a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components such as registers and FIFO, a processor executing a set of firmware instructions, any general programmable software module and processor, or any combination thereof. The processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A software module may reside in RAM memory, flash memory, ROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. Those skilled in the art will further appreciate that the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description are represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the disclosed embodiments. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the disclosed embodiments are not limited to the embodiments shown herein but are to be accorded the widest scope consistent with the principles and novel features described herein.

Claims (38)

1. A method for detecting rate errors in a variable rate receiver, the method comprising:

receiving an encoded speech signal;

performing a rate determination algorithm on the speech signal to provide a coding rate;

detecting an error in the provided rate, comprising: according to the information of the voice classification and the voice characteristics of the dialogue voice, establishing a set of voice continuous frame illegal rate conversion; and determining the presence of illegal rate conversion.

2. The method of claim 1 wherein said set of illegal rate conversions comprises a full rate frame followed by an 1/8 rate frame.

3. The method of claim 1 wherein said set of illegal rate conversions comprises a full rate 1 type frame followed by an 1/8 rate frame.

4. The method of claim 1 wherein said set of illegal rate conversions comprises a half rate 1 type frame followed by an 1/8 rate frame.

5. The detection method of claim 1, wherein said set of illegal rate conversions comprises an 1/4 rate frame followed by a full rate 1 type frame.

6. The method of claim 1 wherein said set of illegal rate conversions comprises an 1/4 rate frame followed by a half rate 1 type frame.

7. The method of claim 1 wherein said set of illegal rate conversions comprises an 1/8 rate frame followed by a full rate 1 type frame.

8. The method of claim 1 wherein said set of illegal rate conversions comprises an 1/8 rate frame followed by a half rate 1 type frame.

9. The method of claim 1 wherein the set of illegal rate transforms comprises 1/8 rate frames followed by 1/4 rate frames followed by 1/8 rate frames.

10. The method of claim 1 wherein the set of illegal rate transforms comprises 1/8 rate frames followed by half rate frames followed by 1/8 rate frames.

11. The method of claim 1 wherein the set of illegal rate transforms comprises 1/8 rate frames followed by full rate frames followed by 1/8 rate frames.

12. A method for detecting rate errors in a variable rate receiver, the method comprising:

receiving an encoded speech signal;

performing a rate determination algorithm on the speech signal to provide a coding rate;

detecting an error in the provided rate, comprising: the relationship between the fixed codebook gain and the linear predictive coding prediction gain is analyzed to establish a threshold curve and identify the received speech relative to the threshold curve.

13. The method of any of claims 1 and 12, further comprising perceptually mitigating effects of the detected rate error through a memory state reset process.

14. The method of claim 13, wherein the memory state reset process comprises overwriting memory values with zeros.

15. The method of claim 13, wherein the memory state reset process comprises overwriting memory values with initialization values.

16. The method of claim 13, wherein a memory state reset process is performed on a displacement average vector quantizer memory for fixed codebook gains.

17. The method of claim 13, wherein the memory state reset process is performed on a stimulus memory.

18. The method of claim 13, wherein the memory state reset process is performed on LPC synthesis memory.

19. The detection method of claim 13, wherein a memory state reset process is performed on the post-filter synthesis memory.

20. A system for detecting rate errors in a variable rate receiver, said error detection system comprising:

means for receiving an encoded speech signal;

means for performing a rate determination algorithm on the speech signal to provide a coding rate; and

apparatus for detecting errors in a provided rate, comprising: means for establishing a set of speech continuous frame illegal rate conversions based on the information of the speech classification and the speech characteristics of the conversational speech; and means for determining the presence of illegal rate conversion.

21. The error detection system of claim 20 wherein said means for establishing a set of illegal rate conversions of successive frames of speech includes means for establishing an illegal rate conversion for a full rate frame followed by a 1/8 rate frame.

22. The error detection system of claim 20 wherein said means for establishing a set of illegal rate conversions of successive frames of speech includes means for establishing an illegal rate conversion for a full rate 1 type frame followed by a 1/8 rate frame.

23. The error detection system of claim 20 wherein said means for establishing an illegal rate conversion set of successive frames of speech includes means for establishing an illegal rate conversion for a half rate 1 type frame followed by a 1/8 rate frame.

24. The error detection system of claim 20 wherein said means for establishing a set of illegal rate conversions of successive frames of speech includes means for establishing an illegal rate conversion for an 1/4 rate frame followed by a full rate type 1 frame.

25. The error detection system of claim 20 wherein said means for establishing an illegal rate conversion set of successive frames of speech includes means for establishing an illegal rate conversion for 1/4 rate frames followed by half rate type 1 frames.

26. The error detection system of claim 20 wherein said means for establishing a set of illegal rate conversions of successive frames of speech includes means for establishing an illegal rate conversion for an 1/8 rate frame followed by a full rate type 1 frame.

27. The error detection system of claim 20 wherein said means for establishing an illegal rate conversion set of successive frames of speech includes means for establishing an illegal rate conversion for 1/8 rate frames followed by half rate type 1 frames.

28. The error detection system of claim 20 wherein the means for establishing a set of illegal rate conversions for successive frames of speech comprises means for establishing illegal rate conversions for 1/8 rate frames followed by 1/4 rate frames followed by 1/8 rate frames.

29. The error detection system of claim 20 wherein said means for establishing a set of illegal rate conversions for successive frames of speech comprises means for establishing illegal rate conversions for 1/8 rate frames followed by half rate frames followed by 1/8 rate frames.

30. The error detection system of claim 20 wherein said means for establishing a set of illegal rate conversions of successive frames of speech includes means for establishing an illegal rate conversion for 1/8 rate frames followed by full rate frames followed by 1/8 rate frames.

31. A system for detecting rate errors in a variable rate receiver, said error detection system comprising:

means for receiving an encoded speech signal;

means for performing a rate determination algorithm on the speech signal to provide a coding rate; and

apparatus for detecting errors in a provided rate, comprising: means for analyzing a relationship between the fixed codebook gain and the linear predictive coding prediction gain to establish a threshold curve; and means for confirming the received speech relative to a threshold curve.

32. The error detection system of any of claims 20 and 31, further comprising memory state reset processing means for perceptually mitigating effects of detected rate errors through memory state reset processing.

33. The error detection system of claim 32, wherein the memory state reset processing means comprises means for overwriting memory values with zeros.

34. The error detection system of claim 32, wherein the memory state reset processing means comprises means for overwriting memory values with initial values.

35. The error detection system of claim 32, wherein the memory state reset processing means comprises means for performing memory state reset processing on a bit-averaged vector quantizer memory for fixed codebook gains.

36. The error detection system of claim 32, wherein the memory state reset processing means comprises means for performing a memory state reset process on a stimulus memory.

37. The error detection system of claim 32, wherein the memory state reset processing means comprises means for performing a memory state reset process on LPC synthesis memory.

38. The error detection system of claim 32, wherein the memory state reset processing means comprises means for performing a memory state reset process on a post-filter synthesis memory.