HK1062954A - Magnetic memory devices having multiple bits per memory cell - Google Patents

Description

Magnetic memory device having multiple bits per memory cell

Technical Field

The present invention relates to the field of magnetic memories.

Background

Magnetic random access memory ("MRAM") is a non-volatile memory that is considered for both short-term and long-term data storage. MRAM consumes less power than short term memories such as DRAM, SRAM, and flash memory. MRAM performs read and write operations much faster (several orders of magnitude) than typical long-term storage devices, such as hard disks. Furthermore, MRAM is more compact and consumes less power than hard disks. MRAM is also considered to be an embedded application such as extremely fast processors and network devices.

Disclosure of Invention

It is highly desirable to increase the bit density of MRAM devices. An increase in bit density can increase storage capacity and reduce storage cost.

Drawings

Fig. 1 shows a magnetic memory device according to a first embodiment of the present invention.

Fig. 1a and 1b show different magnetization directions of a magnetic memory device.

Fig. 2 shows hysteresis loops for data and reference layers of a magnetic memory device.

FIG. 3 illustrates a write operation of the magnetic memory device.

FIG. 4 illustrates a read operation of a magnetic memory device.

Fig. 5 illustrates an MRAM device in accordance with an embodiment of the present invention.

Fig. 6a and 6b illustrate a read-out method of an MRAM device according to an embodiment of the present invention.

Fig. 7 shows a magnetic memory device according to a second embodiment of the present invention.

Detailed Description

Referring to FIG. 1, a magnetic memory device 8 is shown that includes first and second magnetic tunnel junctions 10 and 20. The first magnetic tunnel junction 10 includes a first data layer 12, an upper portion 14a of a reference layer 14, and a first insulating tunnel barrier 16 between the data layer 12 and the upper portion 14 a. The first data layer 12 is constructed of ferromagnetic material and can be magnetized in two directions (represented by vector M1), generally along its easy axis (one direction represented by a solid line and the other direction represented by a dashed line). The upper portion 14a of the reference layer 14 is also comprised of ferromagnetic material and can be magnetized in two directions (represented by vector M3), generally along its easy axis. The easy axes of magnetization of the first data layer 12 and the upper portion 14a of the reference layer 14 extend in the same direction.

The directions of the first magnetic tunnel junction 10 are said to be "parallel" if the magnetization vectors (M1 and M3) of the first data layer 12 and the upper portion 14a of the reference layer 14 point in the same direction (FIG. 1 a). The direction of the first magnetic tunnel junction 10 is said to be "anti-parallel" if the magnetization vectors (M1 and M3) of the first data layer 12 and the upper portion 14a of the reference layer 14 point in opposite directions (FIG. 1 b). The two stable directions parallel and anti-parallel may correspond to logical values "0" and "1".

The first insulating tunnel barrier 16 allows quantum mechanical tunneling to occur between the second data layer 12 and the upper portion 14a of the reference layer 14. This tunneling phenomenon is electron spin dependent, making the resistance of the first magnetic tunnel junction 10 a function of the direction of the magnetization vectors (M1 and M3) with respect to the first data layer 12 and the upper portion 14a of the reference layer 14. For example, if the magnetization directions of the first magnetic tunnel junction 10 are parallel, the resistance of the first magnetic tunnel junction 10 is a first value (R), and if the magnetization directions are anti-parallel, the resistance of the first magnetic tunnel junction 10 is a second value (R1+ Δ R). The first insulating tunnel barrier layer 16 is made of alumina (Al)₂O₃) Silicon dioxide (Si 0)₂) Tantalum oxide (Ta)₂O₅) Silicon nitride (Si)₃N₄) Aluminum nitride (AlN) or magnesium oxide (MgO). Other dielectrics and certain semiconductor materials may also be used as the first insulating tunnel barrier layer 16. The thickness of the first insulating tunnel barrier layer 16 is from about 0.5 nanometers to about 3 nanometers.

The second magnetic tunnel junction 20 includes a second data layer 22, a lower portion 14b of the reference layer 14, and a second insulating tunnel barrier layer 24 between the data layer 22 and the lower portion 14 b. The second data layer 22 is constructed of a ferromagnetic material and can be magnetized in two directions (represented by vector M2), typically along its easy axis. The lower portion 14b of the reference layer 14 is also comprised of ferromagnetic material and can be magnetized in two directions (represented by the same vector M3), generally along its easy axis. The second insulating tunnel barrier layer 24 allows quantum mechanical tunneling to occur between the second data layer 22 and the reference layer 14. The resistance of the second magnetic tunnel junction 20 is a function of the direction of the magnetization vectors (M2 and M3) with respect to the lower portions of the second data layer 22 and the reference layer 14.

The first magnetic tunnel junction 10 has two resistance states (R1, R1+ Δ R1), and the second magnetic tunnel junction 20 has two resistance states (R2, R2+ Δ R2). The resistance of the magnetic tunnel junctions 10 and 20 is made different by using insulating tunnel barrier layers 16 and 24 of different thickness and/or material. Four different logic levels may be stored in the magnetic memory device 8 as long as a difference in the four impedance states can be detected.

First electrical conductor 30 is in contact with first data layer 12 and second electrical conductor 32 is in contact with second data layer 22. The reference layer 14 includes a third conductor 34. Conductors 30, 32 and 34 may be made of a material such as copper or aluminum. The first and second conductors 30 and 32 extend in the same direction. The third conductor 34 is at substantially right angles to the first and second conductors 30 and 32.

The reference layer 14 also includes a ferromagnetic cladding 36 on the third conductor 34. The upper portion 14a of the reference layer 14 includes a portion of the cladding layer 36 between the third conductor 34 and the first insulating tunnel barrier 16. The lower portion 14b of the reference layer includes a portion of the cladding layer 36 between the third conductor 34 and the second insulating tunnel barrier layer 24. The plot of the cladding thickness is exaggerated relative to the third conductor 34. The thickness of the cladding 36 is about 1nm to 50nm (typically 4 nm). Providing current to the third conductor 34 causes a magnetic field to be generated around the third conductor 34. If current flows in the third conductor 34, the magnetic field causes the reference layer magnetization vector (M3) to wrap around the third conductor 34 in a clockwise direction (as viewed in FIG. 1). If the current direction is reversed, the magnetic field causes the reference layer magnetization vector (M3) to wrap around the third conductor 34 in a counter-clockwise direction. The magnetization points in one direction in the upper part 14a and in the opposite direction in the lower part 14 b. The cladding 36 provides a path for the magnetic field.

Referring now to fig. 2, fig. 2 shows hysteresis loops L1 and L2 of the first and second data layers 12 and 22. Fig. 2 also shows a hysteresis loop L3 for the upper portion 14a and the lower portion 14b of the reference layer 14. The first and second data layers 12 and 22 have the same coercivity. I.e. H_C1＝H_C2. Coercivity (H) of data layers 12 and 22_C1，H_C2) Height ofCoercive force (H) at reference layer portions 14a and 14b_C3). Coercivity (H) of data layer_C1，H_C2) Is the coercivity (H) of the reference layer portions 14a and 14b_C3) 2-5 times of the total weight of the product. For example, the coercivity (H) of the data layer_C1，H_C2) Approximately 25Oe, the coercivity (H) of each of the reference layer segments 14a and 14b_C3) Approximately 5 Oe. Because the reference layer magnetization vector (M3) is more easily switched, the reference layer portions 14a and 14b are considered "softer" than the data layers 12 and 22. It is preferable to make the coercive force (H) of the reference layer portions 14a and 14b_C3) As low as possible.

The coercivity is made different by using different bit shapes, geometries, compositions, thicknesses, etc. Ferromagnetic layer materials include nickel-iron (NiFe), nickel-iron-cobalt (NiFeCo), cobalt-iron (CoFe), other magnetically soft alloys of NiFe and Co, doped amorphous ferromagnetic alloys, and PERMALLOY^TM. For example, the data layers 12 and 22 are made of NiFeCo or CoFe and the overcoat layer 36 is made of NiFe.

Reference is now made to fig. 3. By applying a first, a second and a third write current (I)_W1、I_W2、I_W3) Are applied to the first, second and third conductors 30, 32 and 34 for a write operation. First, second and third write currents (I)_W1、I_W2、I_W3) Magnetic fields (H1, H2, H3) are generated around the first, second and third conductors 30, 32 and 34, respectively. When the combination of the first and third magnetic fields (H1 and H3) exceeds the coercivity (H) of the first data layer 12_C1) At this time, the magnetization vector (M1) of the first data layer 12 is set to a desired direction. The direction of the first data layer magnetization vector (M1) determines the logical value stored in the first magnetic tunnel junction 10. When the combination of the second and third magnetic fields (H2 and H3) exceeds the coercivity (H) of the second data layer 22_C2) At this time, the magnetization vector (M2) of the second data layer 22 is set to a desired direction. The direction of the second data layer magnetization vector (M2) determines the logical value stored in the second magnetic tunnel junction 20.

The orientation of the first data layer magnetization vector (M1) is set independent of the orientation of the second data layer magnetization vector (M2). Therefore, it can be independent of the second and third write currents (I)_W2And I_W3) Applying the first and third write currents (I)_W1And I_W3) Combinations of (a) and (b).

The first and second magnetic tunnel junctions 10 and 20 can be written in sequence. For example, any one of the first and second write currents (I)_W1Or I_W2) A third write current (I) applied to the first or second conductor 30 or 32 and after a short delay (e.g., 20ns)_W3) To the third conductor 34. As a result, the hard axis field is applied first to obtain the advantage that the magnetization vector generated along the easy axis HAs a higher torque (the easy and hard axes are indicated by arrows labeled EA and HA).

If the three currents are equal in magnitude, the magnetic field surrounding the first and second conductors 30 and 32 has a greater effect on the data layers 12 and 22 than the magnetic field surrounding the third conductor 34 (because a portion of the magnetic field saturates the ferromagnetic cladding 36). Third write current (I)_W3) May be larger than the first and second write currents (I)_W1、I_W2) To compensate for saturation of ferromagnetic cladding 36 and to produce higher torque magnetization vectors (M1 and M2).

Referring now to FIG. 4, FIG. 4 illustrates a read operation. Sensing current (I)_R) To the third conductor 34. Sensing current (I)_R) The generated magnetic field is caused to surround the third conductor 34. The magnetic field causes the magnetization in the upper portion 14a of the reference layer 14 to point in the opposite direction to the magnetization in the lower portion 14b of the reference layer 14. Because of the coercivity (H) of the reference layer 14_C3) Low, so that the sense current (I)_R) May be small. The magnetic field thus generated does not influence the magnetization of the data layers 12 and 22.

A first potential (V) is applied to the first and second conductors 30 and 32 and the third conductor 34 is maintained at a potential lower than the first potential. As a result, the first detection current (I)_S10) Flowing through the first tunnel junction 10 and into node (N), a second sense current (I)_S20) Flows through the second tunnel junction 20 and enters node (N). Measuring the current (I) flowing through the node (N)_S10+I_S20+ IR) inference of the impedance state of device 8. The inferred impedance state would be R1+ R2, R1+ R2+ Δ R1, R1+ R2+ Δ R2, or R1+ R2+ Δ R1+ Δ R2. Four different logic levels can be read as long as the four impedance states are detected as different states.

Referring now to fig. 5, fig. 5 illustrates an MRAM device 110. MRAM device 110 includes an array 112 of memory cells 114. Each memory cell 114 includes first and second magnetic tunnel junctions 10 and 12. The memory cells 114 are arranged in rows extending in the x-direction and columns extending in the y-direction. Only a small number of memory cells 114 are shown to simplify the MRAM device 110 shown. In practice, any size array may be used.

Word lines 116 extend in the x-direction. Each word line 116 includes a second conductor and a third conductor coated with a ferromagnetic material 36. Each word line 116 is in contact with a row of first insulating tunnel barriers 16 (of the first magnetic tunnel junction 10) and a row of second insulating tunnel barriers 24 (of the second magnetic tunnel junction 20). The first and second bit lines 118 and 120 extend in the y-direction. Each first bit line 118 contacts a column of the first data layer 12 (of the first magnetic tunnel junction 10). Each first magnetic tunnel junction 10 is located at an intersection of a word line 116 and a first bit line 118. Each second bit line 120 contacts a column of the second data layer 22 (of the second magnetic tunnel junction 20). Each second magnetic tunnel junction 20 is located at an intersection of a word line 116 and a second bit line 120.

MRAM device 110 also includes first and second row decoders 122a and 122b, first and second column decoders 124a and 124b, and a read/write circuit 126. During read and write operations, decoders 122a, 122b, 124a, and 124b select word and bit lines 116, 118, and 120. The selected first magnetic tunnel junction 10 is located at the intersection of the selected word line 116 and the selected first bit line 118. The selected second magnetic tunnel junction 20 is located at the intersection of the selected word line 116 and the selected second bit line 120.

Read/write circuit 126 includes a current source 128 that provides a write current to the selected word and bit lines 116, 118, and 120 during a write operation. Current source 128 also provides a sense current during a sense operation. Read/write circuit 126 includes sense amplifier 130, ground connection 132, and voltage source 134 to apply a voltage during sensing.

During a write operation, the first and second magnetic tunnel junctions 10 and 20 of the memory cell 114 selected by the read/write circuit 126 write a logic value.

During a sensing operation, the read/write circuit 126 detects the resistance states of the first and second magnetic tunnel junctions 10 and 20 of the selected memory cell 114. However, in the array 112, the magnetic tunnel junctions 10 and 20 are connected together by many parallel paths. The impedance seen at one intersection is equal to the parallel of the impedance of the magnetic tunnel junction 10 at the intersection and the impedances of the magnetic tunnel junctions 10 and 20 in the other rows and columns. Thus, the array 112 of magnetic tunnel junctions 10 features a two-stage cross-point impedance network.

Because the magnetic tunnel junctions 10 and 20 are connected as a cross-point impedance network, parasitic or sneak path currents can interfere with the sensing operation on the selected magnetic tunnel junctions 10 and 20. Blocking devices such as diodes or transistors may be connected to the magnetic tunnel junctions 10 and 20. These blocking devices can block parasitic currents.

In an alternative embodiment, a variation of the "equipotential" approach is employed in assignee's U.S. patent No.6,259,644 to handle parasitic currents. The equipotential method disclosed in U.S. patent No.6,259,644 includes applying a potential to a selected line and providing the same potential to unselected bit lines and unselected word lines. Parasitic currents are avoided so as not to disturb the sense current.

An embodiment of the equipotential method is shown in fig. 6 a. The array voltage (Va) is applied to a first input of the sense amplifier 610, and the selected word line 116 is connected to a second input of the same amplifier 610. A second input of the sense amplifier 610 couples a voltage (Va ') to the selected word line 116, where Va' ═ Va. The selected bit lines 118 and 120 are connected to ground 132. Detecting the current (I)_S10、I_S20) Flows through the first and second magnetic tunnel junctions 10 and 20. Sense amplifier 610 operates by generating a sum current (I) with word line 116_S10+I_S20) Proportional output voltage to determine the impedance shape of the selected memory cell 114State.

To minimize parasitic currents, a voltage V1 is applied to all upper unselected bit lines 118 and a voltage V2 is applied to all lower unselected bit lines 120. All unselected word lines 116 are allowed to float. Parasitic current (I)_P10And I_P20) Flows through the nodes 10 and 20 to which the voltages V1 and V2 are applied. Voltages V1 and V2 may be set to array voltage (Va), such that V1 equals V2 equals Va.

Another embodiment of the equipotential method is shown in fig. 6 b. First and second inputs of sense amplifier 610 are connected to Ground (GND) and the selected word line 116, respectively. An array voltage (Va) is applied to the selected bit lines 118 and 120, and a voltage V1 is applied to all upper unselected bit lines 118, a voltage V₂To all lower unselected bit lines 120. V1-V2-GND. In an alternative embodiment, V1 ═ epsilon, V2 ═ epsilon, where epsilon is a small potential a few (e.g., tens) millivolts above ground potential (GND). Therefore, GND < ε < Va. By biasing the upper and lower portions of array 112 in this manner, parasitic current (I)_P10And I_P20) Does not interfere with the detection current (I)_S10And I_S20)。

MRAM devices are not limited to dual bit memory cells having a shared soft reference layer. MRAM devices may instead include one or more arrays of dual bit memory cells having a hard reference layer.

Referring now to fig. 7, fig. 7 illustrates a dual bit memory cell 710 of such an array. First bit 712 of memory cell 710 includes spacer layer 712a, data layer 712b on one side of spacer layer 712a, and hard reference layer 712c on the other side of spacer layer 712 a. The second bit 714 includes a spacer layer 714a, a data layer 714b on one side of the spacer layer 714a, and a hard reference layer 714c on the other side of the spacer layer 714 a. If the bits 712 and 714 are magnetic tunnel junctions, the spacer layers 712a and 714a are insulating tunnel barriers and the reference layers 712c and 714c are pin layers. The magnetization direction of the needle layer is fixed so as not to rotate in the presence of the applied magnetic field of interest. Thus, the data layer magnetization can be oriented in two directions: the magnetization direction of the needle layer is the same or opposite to the magnetization direction of the needle layer.

The magnetization direction of the needle layer may be fixed by an Antiferromagnetic (AF) needle layer (not shown). The AF pin layer provides a large exchange field to keep the magnetization of the pin layer in one direction.

A word line 716 is connected to the reference layers 712c and 714c of the bits 712 and 714, a first bit line 718 is connected to the data layer 712b of the first bit 712, and a second bit line 720 is connected to the data layer 714b of the second bit 714. The first bit 712 has two impedance states and the second bit 714 has two impedance states. The four impedance states are different detectable states. Such an array of memory cells can be read out in the way shown in fig. 6a and 6 b.

The memory cells are not limited to two bits. Additional bits may be added by adding a magnetoresistive device to each memory cell. For example, a memory cell comprising three magnetoresistive devices will have three bits and eight different resistance states.

The invention is not limited to this tunnel junction. The invention also encompasses other types of magnetoresistive devices, such as Giant Magnetoresistive (GMR) devices. GMR devices have the same basic structure as TMR devices except that the data and reference layers are separated by a conductive nonmagnetic metal layer instead of an insulating tunnel barrier. Exemplary spacer layer metals include gold, silver, and copper. The relative orientation of the data and reference magnetization vectors affects the in-plane (in-plane) resistance of the GMR device. Other types of devices include upper and lower rotating vacuum tubes (spin valve).

Although specific embodiments of the invention have been described and illustrated, the invention is not to be limited to the specific forms or arrangements of parts so described and illustrated. Rather, the invention is to be construed in accordance with the following claims.

Claims (9)

1. A data storage device (110), comprising:

an array (112) of memory cells (114), each memory cell (114) comprising first and second magnetoresistive devices (10, 20) connected in series, the first magnetoresistive device (10) of each memory cell (114) having first and second resistance states, the second magnetoresistive device (20) of each memory cell (114) having third and fourth resistance states, all four resistance states of each memory cell (114) having a detectable difference;

a column of first conductors (118), each first conductor (118) being connected to a data layer (12) of a column of first magneto-resistive devices (10);

a column of second conductors (120), each second conductor (120) being connected to a data layer (22) of a column of second magneto-resistive devices (20); and

a row of third conductors (116), each third conductor (116) being between the reference layers (14a, 14b) of the rows of first and second magneto-resistive devices (10, 20).

2. A data storage device as claimed in claim 1, wherein the first and second magneto-resistive devices (10, 20) of each memory cell (114) comprise insulating tunnel barrier layers (16, 24) of different thickness and/or material.

3. The data storage device of claim 1, wherein the first and second magnetoresistive devices (10, 20) of each memory cell (114) comprise:

a coating (36) of ferromagnetic material on the third conductor (116);

first and second spacers (16, 24) on opposite sides of the cladded conductor (116);

a first data layer (12) on the first spacer layer (16); and

a second data layer (22) over the second spacer layer (24).

4. A data storage device as claimed in claim 3, wherein the spacers (16, 24) are insulating tunnel barriers, whereby the first data and spacer layers (16, 24) form a first magnetic tunnel junction (10) with the cladding conductor (116) and the second data and spacer layers (22, 24) form a second magnetic tunnel junction (20) with the cladding conductor (116).

5. The data storage device of claim 1, wherein each magnetoresistive device (10, 20) comprises a spacer layer, a data ferromagnetic layer on one side of the spacer layer, and a hard reference ferromagnetic layer on the other side of the spacer layer.

6. The data storage device of claim 5, wherein the spacer layer is an insulating tunnel barrier layer and the hard reference layer is a pin layer.

7. A data storage device according to claim 1, further comprising a sense circuit (126) for applying a first voltage on the first and second conductors (118, 120) crossing at a selected memory cell (114) and maintaining the third conductor (116) crossing at the selected memory cell (114) at a second voltage different from the first voltage.

8. The data storage device of claim 7, wherein the sensing circuit (126) measures the total current on the third conductor (116) to determine the resistive state of the first and second magnetoresistive devices (10, 20).

9. The data storage device of claim 1, further comprising means (126) for shunting parasitic current during a read operation.