HK1062503B - Inverter controller - Google Patents

Description

Converter controller

Technical Field

The present invention relates to a converter controller, and more particularly, to a converter controller using a pin multiplexing and/or pin multiplexing technology, which can reduce the number of pins and the number of components while ensuring the function and/or performance. One particular application of the invention is a dual switch DC/AC inverter for driving CCFLs, but other inverter topologies and/or DC/DC inverter topologies, and/or other load conditions are contemplated herein.

Disclosure of Invention

The present invention provides an integrated circuit including an inverter controller that can generate a plurality of signals for driving the inverter circuit. The controller is configured with one or more pins to receive two or more input signals. Each signal supporting a respective function in the controller.

In one exemplary embodiment, the input pin is configured to receive a first signal representing a dark (dim) voltage, the first signal having a first voltage range. This pin may also receive a second signal representing the feedback voltage signal, the second signal having a second voltage range.

In another exemplary embodiment, the input pin is configured to receive a first signal indicative of the current feedback signal, the first signal occurring during a first time period. The pin may also receive a second signal representing a soft start signal, the second signal occurring in a second time period.

The present invention also provides an inverter controller integrated circuit comprising a multiplexing circuit operable to direct one input signal to a first circuit to support a first said function of the controller and another input signal to a second circuit to support a second said function of the controller.

The present invention further provides an inverter controller integrated circuit comprising an input pin capable of receiving two or more signals, each signal for supporting a respective function of the controller. Of these signals, one signal occurs in a first time period and the other signal occurs in a second time period.

In this way, the number of input pins can be greatly reduced by the present invention. At the same time, by selecting which pins to implement multi-function and/or multiplexing, the present invention may also reduce the requirements for processing and designing printed circuit layouts (PCBs).

In another exemplary embodiment, the inverter controller of the present invention can be applied to a liquid crystal flat panel display, which further includes a liquid crystal display panel; one or more cold cathode fluorescent lamps for providing illumination to the liquid crystal display panel; and an inverter circuit for generating an AC signal to be supplied to the one or more cold cathode fluorescent lamps. Preferably, the inverter circuit comprises a step-up transformer receiving the ac signal and generating a step-up ac signal.

The inverter controller of the present invention can also be applied to a computer system, wherein the computer system further comprises a system central processing unit; a liquid crystal display screen; one or more cold cathode fluorescent lamps for providing illumination to the liquid crystal display panel; and an inverter circuit for generating an AC signal to be supplied to the one or more cold cathode fluorescent lamps.

Other benefits and advantages of the invention will become apparent to those skilled in the art upon review of the following detailed description and claims and the accompanying drawings.

Drawings

Fig. 1 is an exemplary block diagram of a converter controller integrated circuit designed in accordance with the present invention.

Fig. 2 is another exemplary block diagram of a converter controller integrated circuit designed in accordance with this invention.

Fig. 3 is a block diagram of an exemplary application circuit layout of the converter controller integrated circuit shown in fig. 1 or 2.

Fig. 4 is a circuit layout block diagram of another example application of the converter controller integrated circuit shown in fig. 1 or fig. 2.

Fig. 5 shows a representative signal diagram of some of the signals generated by the controller of fig. 1.

Fig. 6 shows a representative signal diagram of some of the signals generated by the controller of fig. 2.

Detailed Description

Fig. 1 depicts a block diagram of an example converter controller integrated circuit 10 implemented with the present invention. In this example, the controller 10 is designed with 8 pins (numbered 1-8), where pin 2 can receive 2 signals and can be multiplexed to support two functions, and pin 4 can also receive 2 signals and support two functions, depending on the state of some portion of the controller. In this example, pin 2 supports both load voltage detection and dark signal detection. Pin 4 supports both current comparison under normal operating conditions and soft start operation under just start and/or lamp out (lamp out) conditions.

The controller 10 includes an overvoltage protection circuit 100, a dimming circuit 200, a current feedback control circuit 30, and an output circuit 400. The controller 10 also contains a MUX18 to control the functional switching of pin 2 between load voltage detection and dark signal input control depending on the state of the load. The controller 10 further includes an oscillator circuit 12, the oscillator circuit 12 being operable to generate a sawtooth signal 14 by charging and discharging a fixed capacitor 16, and a reference/offset generator 20 for generating one or more reference and/or offset signals for use by the controller 10. The controller operates to generate two switch drive signals NDR1 and NDR2 which can be used to drive two switches of a derivative Royer circuit known in the art, a push-pull circuit, a half-bridge circuit, and other known two-switch inverter circuits.

In other words, the present invention provides an inverter controller that includes one or more multiplexed and/or multi-function pins, which may generate one or more control signals based on the signal state of the multiplexed and/or multi-function pins. The following description is with respect to overvoltage protection circuit 100, dimming circuit 200, current control circuit 300, and output circuit 400. These descriptions will be well understood if familiar with converter technology. The various components of the controller 10 will be described in detail below.

The output circuit 400 includes a comparator 42, and the comparator 42 compares the signal 52 output from the error amplifier 30 with the sawtooth signal output from the oscillation circuit 12. Error signal 52 is generated by current control circuit 300 and/or the CMP capacitor (at pin 4) and may be modified by dimming circuit 200. Under normal operating conditions, the value of the error signal is between the maximum value and the minimum value of the sawtooth signal 14. For example, if it is a CCFL load, the sawtooth signal will range from 0v to 3.0 v. As is generally known to those skilled in the art, the crossing point of the sawtooth signal 14 and the error signal 52 will be used by the switch drive logic 44 to determine the pulse width of the switch drive signals NDR1 and NDR2. Generally, the higher the error signal value, the wider the pulse and thus more energy will be delivered to the load (although the circuit may also be modified so that the opposite occurs).

As set forth above, the value of error signal 52 is determined by current feedback information generated by current control circuit 300 and may be modified by dimming circuit 200. Typically, CMP capacitor 40 is charged when controller 10 is initially powered on. Error amplifier 30 operates as a current source (e.g., a transconductance amplifier) to adjust the charge on CMP capacitor 40. Amplifier 30 is used to compare the load current Isens to a user definable reference signal 32 which represents the maximum load current at maximum power or maximum brightness 32. If the load current value is less than the signal 32, the amplifier 30 will provide current to charge the capacitor 40 to increase the DC magnitude of the error signal 52, thereby increasing the pulse width of the output drive signals NDR1 and NDR2. If the load current value is greater than the signal 32, the amplifier 30 will receive the charge of the capacitor 40 to reduce the DC magnitude of the error signal 52, thereby reducing the pulse width of the output drive signals NDR1 and NDR2. In other words, amplifier 30 embodies a closed loop feedback current control by providing current and receiving current such that load current Isens and reference signal 32 are approximately equal.

Dimming circuit 200 is enabled by MUX circuit 18 (this process is described in detail below), and the corresponding dark value is set by VDIM (pin 2). In the example, VDIM is a DC signal that takes on values between VI and V2. The VDIM may be generated by a software programmable dim level or a user operated switch (e.g., rotary switch). In this example, the larger the VDIM, the more power the load will get, and of course the circuitry can be adjusted to allow the opposite to happen. The dimming circuit 200 is a burst mode dimming circuit that generates a burst mode signal (low frequency PMW signal 50) having a duty cycle proportional to Vdim. The frequency of this burst mode signal 50 is much lower than the frequency of the drive signals NDR1 and NDR2. For example, in CCFL applications, a typical drive signal frequency is 35-80kHz, while the frequency of the burst mode signal is approximately 200 Hz.

In the example, the dimming circuit 200 includes a digital dimming circuit that receives Vdim and converts Vdim to a digital signal. The digital signal is weighted at a predetermined bit depth (e.g., 8 bits) to provide a predetermined number of dark values (e.g., 256 dark values) that can be expressed. The digital dimming circuit 36 generates a duty cycle proportional to the Vdim burst mode signal 50. In this example, the duty cycle of the burst mode signal 50 is between 0% (Vdim ═ V1) and 100% (Vdim ═ V2).

If MUX18 enables dimming circuit 200, PWM enable module 38 will discharge CMP capacitor 40. The enable module 38 comprises a simple switch connected to ground, the on state of which is controlled by the burst mode signal 50. As described above, error amplifier 30 produces an output to maintain DC signal 52 at the maximum value exhibited by signal 32. The burst mode signal 50 operates as follows. When the burst mode signal is asserted (high or low), enable circuit 38 is discharged by capacitor 40. As a result, the dc signal 52 is at a minimum (e.g., 0 volts). Thus, the signal generated by comparator 42 represents the intersection between the lowest value of CT signal 14 and DC signal 52, and accordingly, switch drive logic 44 will turn off drive signals NDR1 and NDR2 when the burst mode signal is asserted. When the burst mode signal is deactivated, the PWM enable block is effectively an open circuit and error amplifier 30 recharges capacitor 40 to the initial value. As a result, the error signal restores the value corresponding to the maximum luminance output, and the switching logic driver generates the driving signals NDR1 and NDR2 having the duty ratios corresponding to the maximum luminance output. Thus in this example, burst mode operation swings the output between fully open and fully closed, the frequency of the swing being determined by burst mode signal 50.

Pin 2 is used to receive two signals representing load voltage sense (Vsens) and dark signal input. The dark signal (Vdim) is used to support power control of the load. The load voltage control functions, for example, to detect an overvoltage condition in the load. In this example, multiplexer MUX18 is used to direct the signal (Vsens or Vdim) on pin 2 to either overvoltage protection circuit 100 or dimming circuit 200 according to a predetermined condition. In this example, the predetermined condition is a light at signal 34 indicating the presence and proper operation of a load light, where signal 34 is an input to MUX 18. In this example embodiment, the dark signal is fixed in a predetermined range, i.e., V1 < Vdim < V2. Vsens is outside this range, i.e., Vsens > V2 or Vsens < V1.

When the controller is connected with a power supply to drive the load, the controller receives feedback of the load voltage and the load current to judge whether the load works normally. Current feedback is represented by Isens at pin 3 and voltage feedback is represented by Vsens at pin 2. Assuming a lamp as the load (e.g., CCFL), those skilled in the art will appreciate that a extinguished or extinguished lamp will produce a dangerously high voltage at the secondary winding of the transformer (not shown in fig. 1). Thus, the present invention determines the initial state of the load lamp by determining whether the load receives a minimum current.

To this end, the comparator 28 compares the load current Isens with a lamp threshold signal 46. The lamp threshold signal 46 indicates the minimum current at which the lamp can operate properly. If Isens is greater than or equal to signal 46, comparator 28 generates a light on signal 34 indicating normal operation of the load. The light-on signal 34 is a control signal generated by the comparator 28 to control the state of the MUX 18. Here, the light-on signal sets the output state of the MUX to couple dimming circuit 200 and pin 2 together. Once Isens exceeds the threshold signal, latch circuit 74 will latch the output of the light on signal. The light-on signal will maintain its state during normal operation so that burst mode dimming (described below) does not change the state of the light-on signal. The Vdim input on pin 2 is used to set the desired dark brightness value (as will be described below).

However, if the current value Isens is lower than the lamp threshold signal 46 just when the controller is energized to drive the load (and before the latch circuit 74 is set), the output of the amplifier 28 will change the state of the lamp-on signal 34. This in turn changes the state of the MUX, thereby coupling the overvoltage protection circuit 100 to pin 2. As will be apparent to those familiar with CCFLs, Vsens is derived from the secondary winding of a transformer to drive the lamp load. Under normal conditions, Vsens does not affect the range of Vlim, i.e. V1 < Vlim < V2. However, if an open circuit or lamp breakage occurs, Vsens may rise to a level greater than V2. If pin 2 and over-voltage circuit 100 are coupled together, Vsens is compared to a predetermined over-voltage threshold signal Vovp (Vovp > V2) at comparator 22. When Vsens exceeds Vovp48, the output of the comparator causes timing circuit 24 to initiate a predetermined pause period.

Since this is a broken or missing lamp condition, Isens will be less than the threshold signal 46 for the lamp. Further, error amplifier 30 will generate an output signal to charge the CMP capacitor, thereby increasing the amount of power delivered to the load. Accordingly, during the pause phase, the protection circuit operates in a similar manner as the PWM enable circuit 38. At this stage, the OVP signal 60 stops the charging and discharging operations of the error amplifier 30 on the CMP capacitor in order to prevent the error amplifier from generating an error signal to operate the switch at high power. At the end of the pause, the protection circuit disables the switch drive logic 44 so that the output overvoltage is controlled.

Therefore, in summary, the present invention provides a converter controller integrated circuit capable of providing power to a load, comprising: 1) an overvoltage protection circuit 100 for receiving a voltage feedback signal from a load and generating a protection signal to disable power delivery to the load, 2) a dimming circuit 200 for receiving a dimming signal and generating a dimming signal to control power delivery to the load, 3) a current control circuit 300 for receiving a current feedback signal from the load and generating an error signal; there is also an output circuit 400 for receiving a so-called error signal, a dimming signal and generating a drive signal for driving the load. One pin of the integrated circuit, such as pin 2, is used to receive the voltage feedback signal and the dimming signal. A multiplexer 18 is coupled to the pin and provides a voltage feedback signal to the over-voltage protection circuit or a dimming signal to the dimming circuit depending on the value of the current feedback signal.

Pin 4 and the CMP capacitor may also implement the function of controlling Soft Start (SST). As will be appreciated by those skilled in the art, soft-start is actually an operation at the beginning of power-on that causes the output circuit to produce a very small pulse width and then gradually widen the width. When the power is turned on, the voltage across the CMP capacitor is zero, so the error amplifier charges the CMP capacitor in response to signal 32. The time for this process is determined by the charge required on the CMP and the capacitance of the CMP, so this time is used as a soft start. This ensures that the power delivered to the load is slowly increased. This process continues until the load current reaches the threshold current 32. After this, the error amplifier 30 will take over the electrode pin 4 on the capacitor, as discussed herein. For CCFL loads, it is generally believed that a gradual increase in lamp load current helps to ensure lamp life.

Thus, pin 4 may generate a dc signal CMP52 based on an error signal generated by current control circuit 300 and/or a dimming signal generated by dimming circuit 200. Pin 4 may also generate the soft start signal 52 based on the value of an error signal generated by the current control circuit, so pin 4 is multifunctional.

Fig. 5 depicts some representative signal diagrams generated by the controller 10 of the present invention. FIG. 5A shows the drive signals NDR1 and NDR2. As shown in fig. 5D, the pulse width of the driving signal is determined by the intersection of the dc error signal CMP52 and the sawtooth signal CT. FIG. 5B illustrates the burst mode signal (LPWM)50, and FIG. 5C illustrates the load current I_L. When the burst mode signal is deactivated (high) 50A, the drive signal and the lamp current signal are present. When the burst mode signal is set (low) 50B, the drive signal stops and the lamp current signal is almost zero. It is noted that when the burst mode signal is set, the CMP signal drops to a minimum value (almost zero), as discussed herein.

Fig. 2 depicts another example inverter controller 10' according to this invention. This inverter controller 10' operates in a similar manner to the case of fig. 1 described above, but with the addition of some circuits that are more advantageous for certain given situations. For example, at the output of error amplifier 30, there is a switching circuit that is triggered by the OVP signal. If the overvoltage protection circuit is activated, the OVP signal will directly turn off the output of error amplifier 30 regardless of the value of Isens. Thus, when the OVP signal is set, the module 30 neither charges nor discharges the capacitor 40. Of course, the protection circuit may also be used to charge or discharge the capacitor 40 to a certain minimum value, so that the output signal can output a predetermined minimum pulse width to the load during the pause period.

The controller 10' also includes a min/max circuit 56 that generates a minimum dc signal value (rather than the zero dc value 52 for the corresponding time period as previously described) when the burst mode signal is used. Thus, the intersection between the sawtooth signal and the minimum DC signal generated by the min/max circuit 56 produces an output such that the output signal has some predetermined minimum pulse width. This can avoid situations such as large voltage swings and/or maintaining continuous function of the drive signal between the set burst mode signal and the cancel burst mode signal.

Enable comparator 58 may be used to generate an enable signal to switching logic 44. If the value on capacitor 40 is greater than the enable threshold, the comparator generates an enable signal (which enables the switching logic), and otherwise the switching logic is disabled.

The PMW enable circuit 38' may include a base low level value (i.e., offset) below which the PWM enable circuit does not draw charge from the CMP capacitor 40. This prevents, as with the min/max circuit, the burst mode enable signal from leaving all of the charge on the capacitor, so that the output signal is set at a non-zero predetermined minimum value. The magnitude of the offset may be determined based on the operating range of the controller, the minimum power required to be delivered to the load in burst mode, and other well-known factors.

Fig. 6 depicts some representative signal diagrams generated by the controller 10' of the present invention. FIG. 6A shows the drive signals NDR1 and NDR2. As shown in fig. 6D, the pulse width of the driving signal is determined by the intersection of the dc error signal CMP52 and the sawtooth signal CT. FIG. 6B illustrates the burst mode signal (LPWM) 50', and FIG. 6C illustrates the load current I_L. When the burst mode signal is deactivated (high) 50A', the driving signal and the lamp current signal are present. When the burst mode signal is set to 50B', the driving signal is reduced to a predetermined minimum pulse width, and the lamp current signal is also substantially reducedAnd (5) reducing. The set value for burst mode 50B' is obtained using the offset described above. It is noted that when the burst mode signal is set, the CMP signal drops to a minimum value (almost zero), as discussed herein.

Thus, the example inverter controller integrated circuits 10 and 10' of fig. 1 and 2 include a pin (e.g., pin 2) that may be multiplexed to receive a first signal (e.g., Vdim or Vsens) having a first predetermined range and a second signal having a second predetermined range. The inverter controllers 10 and 10' also include a multi-function pin (e.g., pin 4) that is operable for a first time period (e.g., normal operating condition) and a second time period (e.g., power-on with soft-start loading).

Fig. 3 illustrates an exemplary layout of an application of the inverter controller integrated circuit 10 or 10'. The controller integrated circuit 10 or 10' of fig. 3 is used to drive a derivative Royer circuit comprising transistors Q1 and Q2 for powering the CCFL load 66. Q1 and Q2 drive the primary side of transformer 60 through a resonant tank circuit formed by capacitor 68 and the primary side electrical conductance of transformer 60. The operating principle of such a circuit should be well known to the respective skilled person. Vsens is drawn from the voltage divider (node 62) between capacitors C1 and C2 so that the value of Vsens is always a fraction of the voltage across the secondary winding of the transformer. Typical values for Vsens are between 1 and 5 volts. Isens is drawn from the voltage divider (node 64) of R1 and R2 in the CCFL load. Typical values for Isens are between 0 volts (no lamp) and 1.25 volts (brightest lamp). Of course, these values are exemplary only and may be modified to accommodate design requirements in accordance with the present invention. Fig. 4 is another example layout configuration for an application of the inverter controller 10 or 10'. The controller in this example is used to drive two (or more) CCFL loads 66 and 70. In this case, since lamps 66 and 70 are in series, current feedback Isens is drawn from voltage dividers R1, R2.

Those skilled in the art will readily recognize that many modifications may be made to the present invention in light thereof. For example, controller integrated circuits 10 and 10' of fig. 1 and 2 can multiplex Vsens and DIM on pin 2, can combine the function of charge capacitor CMP40 with a soft start function. However, this is only one example of the ability of the present invention to implement pin multiplexing/multiplexing. Other pins of the integrated circuit in the example may also be multiplexed and multitasked. In addition, other integrated circuit designs having more or less than the 8 pins of FIGS. 1 and 2 may be implemented herein.

Further modifications may also be made. In the example controller integrated circuits of fig. 1 and 2, pin 2 is multiplexed to support load voltage detection and dark signal detection. As indicated previously, the range of dark signals (V1 < Vdim < V2) and the selection of the overvoltage protection threshold Vovp are required to satisfy Vovp > V2. However, this is not necessary for the invention to function properly. Since the value of Vdim is used by the overvoltage protection circuit 100 independently of the dark value, it is practical to have the value of Vovp at or below the range of Vdim. Alternatively, the multiplexing and/or multi-function pins referred to herein may support 3 or more signals using the multiplexing and/or multi-function techniques mentioned above.

Further modifications may also be made. The example application layout configurations of fig. 3 and 4 depict controller integrated circuit 10 or 10' used to drive a derivative Royer circuit, here composed of Q1 and Q2. However, the controller 10 or 10' may also be applied to a push-pull inverter, a half-bridge inverter, and/or other well-known dual-switch inverter topologies. Of course, further, the controller integrated circuit 10 or 10 'may be modified to include a second pair of drive signals (e.g., PDR1 and PDR2) to enable the controller integrated circuit 10 or 10' to drive a four-switch inverter topology (e.g., a full-bridge inverter).

The present invention is not limited to CCFL loads only. In fact, the controllers 10 and 10' of the present invention may be used to drive other lamp loads, such as metal halides or sodium vapor. Other loads may also be used. For example, the controllers 10 and 10' of the present invention may operate in a frequency range that is capable of supporting driving an X-ray tube or other high frequency load. The invention is also not limited by the type of load and should be considered load independent. In addition, to the multiple lamp arrangement depicted in FIG. 4, many other arrangements may be used, such as those described in U.S. Pat. No. 6,104,146, U.S. patent application Ser. Nos. 09/873,669,09/850,692, and 10/035,973, which are incorporated herein by reference.

The description of the operation of some components in fig. 1 and 2 is omitted here. For example, the operation of oscillator circuit 12 and switching logic 44 is omitted, as their operation and application will be readily apparent to those skilled in the art. Also, the timing of the drive signals NDR1 and NDR2 is not overly described herein, as such operations will be readily apparent to those skilled in the art. The foregoing details of the block diagrams of fig. 1 and 2 are primarily provided to explain the functionality of the components. The components referred to in fig. 1 and 2 may be normalized components or user-specific components capable of performing the described functions, and those skilled in the art will readily recognize that many circuits may be used to perform the functions described herein, and all such variations are considered to be within the scope of the present invention.

Further, an inverter controller including voltage and current feedback and dark signal control (as described herein) is well known to those skilled in the art. However, conventional integrated circuit inverter controllers have not been able to meet the long-felt need to reduce the number of package pins while maintaining functionality. The present invention provides an example of a solution to this problem by multiplexing and/or multi-function integrated circuit pins, as described. Those skilled in the art will readily recognize various modifications which may be made to the subject matter of the present invention, all of which should be considered within the scope of the present invention, as set forth in the following claims.

Claims (26)

1. An integrated circuit, comprising:

an inverter controller capable of generating a plurality of signals to drive an inverter circuit; at least one input pin of said controller for receiving at least two independent input signals, each of said input signals supporting a respective function of said controller during operation of said controller, said one input pin for receiving a first signal representative of a current feedback signal, wherein the first signal occurs during a first time period; and a second signal representative of the soft start signal, wherein the second signal occurs during a second time period.

2. The integrated circuit of claim 1, said another input pin for receiving a first signal representative of a dark voltage, said first signal having a first voltage range; and a second signal representing the voltage feedback signal, said second signal having a second voltage range.

3. The integrated circuit of claim 1, further comprising a multiplexing circuit that directs one of said input signals to a first circuit to support a first function of said controller and directs another of said input signals to a second circuit to support a second function of said controller.

4. An integrated circuit comprising an inverter controller, the controller in turn comprising a multiplexer and at least one input pin for receiving at least two independent input signals, each of said input signals being used to support a respective function of said controller during operation of said controller, said one input pin being used to receive a first signal representative of a current feedback signal, wherein the first signal occurs during a first time period; and a second signal representative of the soft start signal, wherein the second signal occurs during a second time period.

5. The integrated circuit of claim 4, the other input pin to receive a first signal representative of a dark voltage, the first signal having a first voltage range; and a second signal representative of the voltage feedback signal, the second signal having a second voltage range.

6. The integrated circuit of claim 4, said multiplexer directing one of said input signals to a first circuit to support a first said function of said controller, said multiplexer further directing another of said input signals to a second circuit to support a second said function of said controller.

7. An inverter converter integrated circuit for generating power to a load, comprising:

an overvoltage protection circuit for receiving a voltage feedback signal from the load and generating a protection signal to stop power supply to the load;

a dimming circuit for receiving a dimming signal and generating a dimming signal for controlling power to a load;

a current control circuit for receiving a current feedback signal from the load and generating an error signal; and

an output circuit for receiving said error signal and said dimming signal and generating a drive signal for driving said load;

wherein said integrated circuit further comprises at least one input pin for receiving said voltage feedback signal and said dimming signal, and wherein said integrated circuit further comprises a multiplexer coupled to said input pin for directing said voltage feedback signal to said overvoltage protection circuit or said dimming signal to said dimming circuit, the directing being dependent on the value of said current feedback signal during operation of said integrated circuit.

8. The inverter converter integrated circuit of claim 7, wherein the current control circuit comprises a first comparator that compares the current feedback signal to a load threshold signal indicative of a minimum current level that should be present at the load, the comparator being operable to generate a control signal to control the state of the multiplexer.

9. An inverter controller integrated circuit comprising:

an overvoltage protection circuit for receiving a voltage feedback signal from the load and generating a protection signal to stop power supply to the load;

a dimming circuit for receiving a dimming signal and generating a dimming signal for controlling power to a load;

a current control circuit for receiving a current feedback signal from the load and generating an error signal; and

an output circuit for receiving said error signal and said dimming signal and for generating a drive signal for driving said load;

wherein said integrated circuit further comprises at least one input pin for receiving said error signal, said dimming signal, and wherein a first signal is generated in dependence of the value of the error signal and/or the dimming signal, or a second signal is generated in dependence of the value of the error signal during operation of said integrated circuit.

10. An LCD flat panel display, comprising:

a liquid crystal display screen;

one or more cold cathode fluorescent lamps for illuminating the display screen;

an inverter circuit for generating an ac signal to be supplied to said one or more lamps; and

an inverter controller for generating a plurality of signals for driving said inverter circuit, said controller including at least one input pin for receiving at least two independent input signals, each said input signal supporting a respective function of said controller during operation of said controller, said one input pin for receiving a first signal representative of a current feedback signal, wherein the first signal occurs during a first time period; and a second signal representative of the soft start signal, wherein the second signal occurs during a second time period.

11. The LCD panel display of claim 10, wherein said inverter circuit is selected from the group consisting of push-pull, half-bridge and full-bridge inverter configurations for converting a dc signal to said ac signal.

12. The LCD panel display of claim 10, wherein the inverter circuit comprises a plurality of power switches for converting a dc signal to an ac signal.

13. The LCD panel display of claim 10, wherein the inverter circuit comprises a step-up transformer for receiving the ac signal and generating a step-up ac signal.

14. The LCD flat panel display of claim 10, the other input pin for receiving a first signal representing a dark voltage, the first signal having a first voltage range; and a second signal representing a voltage feedback signal, said second signal having a second voltage range, where the voltage feedback signal is indicative of the voltage supplied to said CCFL.

15. The LCD panel display of claim 10, further comprising a multiplexing circuit that directs one of said input signals to a first circuit to support a first function of said controller and directs another of said input signals to a second circuit to support a second function of said controller.

16. A computer system, comprising:

a system central processing unit;

a liquid crystal display screen;

one or more cold cathode fluorescent lamps for illuminating the display screen;

an inverter circuit for generating an ac signal to be supplied to said one or more lamps; and

an inverter controller for generating a plurality of signals for driving said inverter circuit, said controller including at least one input pin for receiving at least two independent input signals, each said input signal supporting a respective function of said controller during operation of said controller, said one input pin for receiving a first signal representative of a current feedback signal, wherein the first signal occurs during a first time period; and a second signal representative of the soft start signal, wherein the second signal occurs during a second time period.

17. The computer system of claim 16 wherein the inverter circuit is selected from the group consisting of a push-pull, half-bridge, and full-bridge inverter configuration.

18. The computer system of claim 16 wherein the inverter circuit comprises a plurality of power switches for converting a dc signal to an ac signal.

19. The computer system of claim 16 wherein said inverter circuit comprises a step-up transformer for receiving said ac signal and generating a step-up ac signal.

20. The computer system of claim 16, the other input pin to receive a first signal representing a dark voltage, the first signal having a first voltage range; and a second signal representing a voltage feedback signal, said second signal having a second voltage range, where the voltage feedback signal is indicative of the voltage supplied to said CCFL.

21. The computer system of claim 16 further comprising a multiplexing circuit that directs one of said input signals to a first circuit to support a first function of said controller and directs another of said input signals to a second circuit to support a second function of said controller.

22. A dc/ac converter comprising:

a plurality of power switches for converting the DC signal to an AC signal;

a step-up transformer for receiving said AC signal and generating a step-up AC signal;

an inverter controller for generating a plurality of signals for driving said plurality of power switches, said controller comprising at least one input pin for receiving at least two independent input signals, each of said input signals supporting a respective function of said controller during operation of said controller, said one input pin for receiving a first signal representative of a current feedback signal, wherein the first signal occurs during a first time period; and a second signal representative of the soft start signal, wherein the second signal occurs during a second time period.

23. The dc/ac inverter of claim 22, further comprising one or more cold cathode fluorescent lamps, said lamps receiving said boosted ac signal.

24. The dc/ac converter as claimed in claim 22, wherein said power switches are arranged to form a converter circuit selected from the group consisting of push-pull, half-bridge and full-bridge converter configurations.

25. The dc/ac converter as claimed in claim 22, said other input pin being adapted to receive a first signal indicative of a dark voltage, said first signal having a first voltage range; and a second signal representative of a voltage feedback signal, the second signal having a second voltage range, wherein the voltage feedback signal is indicative of a voltage provided to the load.

26. The dc/ac converter of claim 22, further comprising a multiplexing circuit that directs one of said input signals to a first circuit to support a first function of said controller and directs another of said input signals to a second circuit to support a second function of said controller.