HK1061939A - Automatic gain control for a time division duplex receiver - Google Patents

Description

Automatic gain control for time division duplex receivers

Background

The present invention relates generally to wireless communication systems. More particularly, the present invention relates to an improved Automatic Gain Control (AGC) circuit for a Time Division Duplex (TDD), Time Division Multiple Access (TDMA) or time division code division multiple access (TD-CDMA) receiver. For simplicity, this receiver is referred to as a TDD receiver throughout.

It is well known in the art that significant power variations between adjacent time slots of a TDD frame can result due to variations in data rate or variations in the number of active users in a time slot. To determine the correct AGC gain, the AGC circuit estimates its symbol power when the first N symbols are received. During this estimation process, symbols used for data estimation will be lost due to imperfect gain control at this time. This estimation process takes a long time to estimate the accuracy from the initial gain.

A typical TDD frame typically includes 15 time slots. Each slot contains two bursts of data separated by a training sequence followed by a guard period forming the end of the frame. The data required for the burst data transmission and the training sequence are used to perform channel estimation. Because the training sequence is used to perform channel estimation, the gain must be constant over the entire slot to obtain an accurate estimate of the channel.

The AGC approach of the prior art has drawbacks. Since neither the number of codes in a received TDD frame nor its associated power is known, the AGC circuit takes a long unnecessary time to adjust to the correct gain level. To determine the estimated symbols, the receiver receives data values for a slot and performs channel estimation based on the training sequence. Channel estimation assumes constant gain and the symbol power is known during the estimation process. Interference with the channel estimate may occur if the AGC is active during the training sequence or any of the data bursts. If the signal strength of the first few data symbols is significantly less than the remaining symbols in the TDD frame, these data symbols will not be received correctly due to the weak symbols. Channel estimation based on this prior art AGC method, therefore, eventually results in slow and not very accurate channel estimation,

disclosure of Invention

The present invention is an enhanced TDD frame structure including a preamble for gain estimation, and a method and apparatus for using the enhanced TDD frame. This preamble allows the AGC circuit to quickly estimate the power level of the received signal and adjust the gain level accordingly. This achieves correct reception of all data symbols in the burst and results in a more accurate training sequence channel estimate. It also allows the AGC circuit in the TDD receiver to be simpler. Further improvements are achieved by using a preamble with a Binary Phase Shift Keying (BPSK) format.

Brief description of the drawings

Fig. 1 is an enhanced TDD burst communication with a preamble.

Fig. 2 shows a block diagram of an AGC circuit for processing the burst communication shown in fig. 1.

Fig. 3 shows a flow chart of a method for channel estimation using the circuit of fig. 2.

Detailed description of the preferred embodiments

Fig. 1 shows an improved TDD burst communication 10 having a preamble 11, two bursts 12, 16, a training sequence 14, two Transport Format Combination Indicator (TFCI) periods 15, 17, and a guard period 18. As shown, burst communication 10 comprises one time slot of a TDD signal architecture. The two bursts 12, 16 are separated by a training sequence 14 and two TFCI periods 15, 17.

Each part of the TDD burst communication 10 supports different functions. The training sequence 14 assists in the estimation of the transmitter channel. The two bursts of data 12, 16 comprise the data-carrying part of the burst communication 10 and are used for transmitting the desired data. The administrative functions of the communication system are handled by the transmission settings. The TFCI periods 15, 17 store information bits about these transmission settings and instruct the receiver how to divide the data in the burst communication 10. The guard period 18 has no information, which serves as a demarcation interval between successive time slots.

According to the invention, the preamble 11 comprises one or more symbols. The preamble 11 is preferably in Binary Phase Shift Keying (BPSK) format, although this is not essential. The use of a BPSK symbol format is preferred because a squared BPSK signal can simply determine the power estimate. The remaining burst communication 10 is in Quadrature Phase Shift Keying (QPSK) format. The content of the preamble 11 allows a simpler estimation of the signal power level. The preamble 11 is preferably a pseudo-random sequence, randomly generated and maintained as a fixed sequence. Since the pseudorandom sequence is the same for each time slot, the synchronization process is simplified by providing the system with only a single correlator. The spreading of the pseudo-random signal will also be maximized to avoid adverse power concentration phenomena. In addition, the use of a pseudo-random signal can eliminate dc bias in the signal.

Fig. 2 shows a simplified Automatic Gain Control (AGC) circuit made in accordance with the present invention, which utilizes a preamble 11. The AGC circuit 30 includes a Variable Voltage Attenuator (VVA)39, an analog-to-digital converter (A/D)34, a converter 41, a power estimation unit 35, a reference power 47, an adder 36, a feedback filter 37, and a digital-to-analog converter (D/A) 38. Converter 41, power estimation unit 35, reference power 32, adder 36, feedback filter 37, and D/a converter 38 together form a feedback loop 43.

The VVA39 is a standard electronic device used in AGC circuits that is responsible for receiving an input signal and adjusting amplifier gain to maintain a constant output signal level for further processing by the receiver. The a/D converter 34 receives the analog signal output from the VVA39 and outputs a digital signal 33. A power estimation unit 35 receives the digital signal 33 and mathematically processes the digital signal using a predetermined algorithm to average the power levels of the sequence of symbols comprising the burst communication 10. The power is preferably estimated using the following equation:equation (1)

This average power level is provided to a first input of adder 36 as power estimation signal 43. Adder 36 simply adds the two signal inputs, which are: 1) a power estimation signal 43 output by the power estimation unit 35; and 2) the reference power signal 32 output by the reference power unit 47. Since the reference power signal 32 output by the reference power unit 47 is preferably a negative signal, the reference power signal 32 is essentially subtracted from the power estimation signal 43, thereby generating the error signal 40. This error signal 40 is then input to the feedback filter 37. The feedback filter 37 is an integrator or a low pass filter. The feedback filter 37 sets the time constant of the feedback loop to ensure stability and to eliminate variations in the error signal 40. This filtered output signal 48 is input to the converter 41.

The converter 41 determines whether the filtered output signal 48 is within a predetermined tolerance threshold. If so, the converter 41 will maintain the filtered output signal 48, and thus maintain the converter output signal 49 at the same level as the filtered output signal 48 when the converter 41 is turned on. If filtered output signal 48 is not within the predetermined tolerance threshold, converter 41 allows filtered output signal 48 to fluctuate through feedback filter 37. The D/a converter 38 then converts the converter output signal 49 to an analog signal 50, and this analog signal 50 serves as a control signal to adjust the gain of the VVA 39. The A/D and D/A converters 34, 38 are well known and widely used in the art and will not be described further herein.

Referring to fig. 3, a preferred method 100 according to the present invention is shown. The method begins at step 101 where a burst communication 31 begins through VVA39, and the burst communication is then digitally converted via a/D converter 34. The digital signal 33 enters the feedback loop 43 and is then processed by the power estimation unit 35 in step 102. The negative predetermined reference power signal 32 is added to the power estimate signal at adder 36 to form an error signal 40 (step 103). This error signal 40 is averaged by the feedback filter 37 (step 104). A decision step 105 is performed to determine whether the error signal 40 is sufficiently low (i.e., below a threshold) so that the channel estimation process can be completed. If the error signal 40 is below the error threshold, the channel estimation process is complete and the feedback loop 43 is set by the switch 41 to keep the VVA39 control signal constant for the remaining time slots (step 106).

However, if the error signal 40 is above the tolerance threshold, the control signal from the filter 37 is converted by the D/a converter 38, which serves as the control signal for the VVA39 (step 107), and the channel estimation is repeated. The estimation and attenuation adjustment process is repeated again, or a number of times, with respect to the second symbol power of the preamble until the error is reduced to an acceptable level and the converter 41 is activated. Next, the attenuation provided by VVA39 is fixed for the remaining time slots (step 106). This process is preferably repeated for each slot.

One advantage of using a preamble for the hardware aspect, according to the present invention, is that the required size of the a/D converter 34 is reduced. According to the present invention, the A/D converter 34 is typically six (6) to ten (10) bits in size, as desired.

Claims (4)

1. A TDD wireless communication system in which a communication signal is divided into successive time slots, each time slot being subdivided into portions comprising:

a preamble in Binary Phase Shift Keying (BPSK) format at the beginning of the time slot;

a training sequence located in the center of the time slot;

a pair of data packets;

two Transport Format Combination Indicator (TFCI) portions, each located between said training sequence and one of said data packets; and

a guard period at the end of the slot.

2. The system of claim 1, wherein the preamble is a pseudo-random code, and its sequence is the same for each time slot.

3. A method for Automatic Gain Control (AGC) in a TDD communication system, wherein each time slot of the communication signal contains a BPSK preamble, the method comprising:

estimating said signal;

comparing the signal to a predetermined reference power;

calculating an error signal based on the comparison; and

adjusting attenuation of the communication signal.

4. The method of claim 3, wherein the preamble is a pseudo random code, and its sequence is the same for each time slot.