HK1061112B - Polysilicon etching method - Google Patents

Description

Method for etching polycrystalline silicon

CROSS-REFERENCE TO RELATED APPLICATIONS

The basis for and claiming priority application for the present invention is the japanese patent application, filed on 9/27/2002 and having application number 2002-284566, which is incorporated by reference in its entirety.

Technical Field

The present invention relates to a method for etching polycrystalline silicon, which is suitable for manufacturing a semiconductor device such as a semiconductor memory having a multi-layered gate electrode structure or a stacked capacitor electrode structure.

Background

Electrically Erasable and Programmable Read Only Memory (EEPROM) and flash memory are known as semiconductor memories having a multi-layer gate electrode structure. It is also known that a Dynamic Random Access Memory (DRAM) is a semiconductor memory having a stacked capacitor electrode structure. In the process of manufacturing these memories, it is required to precisely etch and pattern a deposited polysilicon layer covering a bump having a vertical sidewall of about 0.3 μm.

In a conventional polysilicon etching method satisfying these requirements, a high-density plasma etching process is divided into first and second steps. In the first step, HBr, Cl are used at a low pressure of 2-8m Torr₂And O₂The polycrystalline silicon layer is selectively etched by the mixed gas. In a second step, HBr and O are used at a high pressure of 20-40m Torr₂The mixed gas of (2) etching the polysilicon residue (this method is referred to as a first conventional method, for example, refer to japanese patent publication No. 2,822,952).

In another conventional polysilicon etch process, HBr, Ar and O are utilized₂The mixed gas of (2) selectively etches the polysilicon layer by reactive ion etching (this method is referred to as a second conventional method, for example, refer to japanese patent publication No. 3,088,178).

In yet another conventional polysilicon etching method, CCl is used in a first anisotropic etching step₄And He, and in a second isotropic etching step, using CCl₄He and SF₆The etching residue is removed by using the plasma scattering phenomenon (this method is referred to as a third conventional method, for example, refer to japanese patent publication No. 2,574,045).

According to the third conventional method, since isotropic etching is performed by the plasma scattering phenomenon, an abnormal shape called a notch is formed on the interface between the polysilicon layer and the underlying film. According to the second conventional method, since Ar ions suppress formation of a deposited film on the side wall of the polysilicon layer, the polysilicon layer is likely to undergo side etching (undercut), resulting in a reduction in dimensional accuracy.

The first conventional method can solve the problems in the second and third conventional methods. However, if the space between two adjacent resist layers is as narrow as only about 0.4 μm, then HBr and O are used₂The mixed gas of (2) cannot completely remove the polysilicon residue remaining on the sidewall of the protrusion having a height of 0.3 μm by over-etching.

Disclosure of Invention

An object of the present invention is to provide a novel polysilicon etching method capable of completely removing polysilicon residues remaining on the sidewalls of the protrusions covered with the polysilicon layer after the polysilicon layer is patterned by plasma etching while retaining the formation anisotropy of the polysilicon layer and protecting the underlying insulating film from etching.

According to one aspect of the present invention, there is provided a polysilicon etching method including the steps of: preparing a semiconductor substrate having an insulating film with a projection formed on one main surface of the substrate and a polysilicon layer deposited on the insulating film and covering the projection; forming a resist layer on the polysilicon layer, the resist layer having a predetermined pattern not covering at least a portion of the sidewalls of the protrusions; using HBr and Cl₂Performing a first plasma etching process of etching the polysilicon layer using the resist layer as a mask so as to leave the polysilicon layer having a pattern corresponding to the resist layer and polysilicon residues formed from a part of the polysilicon layer remaining on the side walls of the protrusions; and performing a second plasma etching process for removing the polysilicon residue using HBr, which is a gas, using the resist layer as a mask.

In such a pluralityHBr and Cl are utilized in the etching method of crystalline silicon₂The mixed gas of (a) can etch most of the layer by the first plasma etching process and leave polysilicon residues on the sidewalls of the protrusions. In the first plasma etching process, HBr and Cl are added₂Wherein HBr provides a high etch selectivity relative to the underlying insulating layer (e.g., silicon dioxide) and Cl is used as the etching gas₂Providing a higher etch rate. High-throughput etching can be performed while suppressing damage to the underlying insulating film.

A second plasma etch process using HBr, a gas, can remove polysilicon residues from the bump sidewalls. In the second plasma etching process, HBr, a gas, is used as an etching gas without adding other gases (e.g., O)₂). Micropatterning can be performed in the horizontal direction and polysilicon residues removed completely.

In this polysilicon etching method, it is preferable that the second plasma etching process is performed at a pressure of 5.0 to 10.0m Torr. The incidence direction of Br ions radiated toward one main surface of the substrate is irregular, and thus the polysilicon residue can be easily removed.

Preferably, the second plasma etching process is performed under the condition that the etching selection ratio of the polysilicon layer to the insulating film is 20-40. This can avoid damage to the underlying insulating film and preserve the formation anisotropy of the polysilicon layer. Side etching and notching can be suppressed. In order to set the etching selection ratio in the range of 20-40, it is preferable to set the Radio Frequency (RF) bias power (bias power) in the range of 10-20W.

In this polysilicon etching method, a third plasma etching process using a resist layer as a mask and using HBr and O may be performed after removing polysilicon residues₂Mixed gas of (5) or Cl₂And O₂The mixed gas is used as an over-etching process of the etching gas. Polysilicon residue on the lower sidewalls of the protrusions on one major surface of the substrate can thus be removed.

As described above, in the process of forming the pattern of the polysilicon layer covering the protrusions using the plasma etching process, the process is divided into the first and second steps. In the first step, HBr and Cl are used₂The mixed gas etches most of the polysilicon layer and leaves polysilicon residues on the bump sidewalls. In a second step, the polysilicon residue is removed from the bump sidewalls using HBr, a gas. The polysilicon residue can be completely removed from the bump sidewalls while preserving the formation anisotropy of the polysilicon layer and protecting the underlying insulating film from etching. Polysilicon residues remaining on the sidewalls of the protrusions having a height of about 0.3 μm can be completely removed even when the space between two adjacent resist layers is as narrow as about 0.3 μm.

Drawings

Fig. 1 is a sectional view showing a polysilicon layer forming process of an EEPROM manufacturing method according to an embodiment of the present invention.

Fig. 2 is a sectional view showing a resist formation process after the process of fig. 1.

Fig. 3 is a cross-sectional view illustrating a first etching process after the process of fig. 2.

Fig. 4 is a cross-sectional view illustrating a second etching process after the process of fig. 3.

Fig. 5 is a sectional view showing a resist layer formation process in one peripheral annular region.

Fig. 6 is a cross-sectional view illustrating a first etching process after the process of fig. 5.

Fig. 7 is a cross-sectional view illustrating a second etching process after the process of fig. 6.

Detailed Description

FIGS. 1-7 are cross-sectional views of a semiconductor substrate illustrating a method of manufacturing an EEPROM in accordance with one embodiment of the present invention. Where fig. 1-4 are cross-sectional views showing the memory matrix region and fig. 5-7 are cross-sectional views showing the peripheral annular region.

In the process shown in fig. 1, one main surface of a semiconductor substrate 10 such as made of silicon is subjected to a thermal oxidation process, thereby forming gate insulating films (gate insulating films) 12a, 12b made of silicon dioxide having a thickness of about 15 nm. This silicon oxide film formed by the thermal oxidation process is hereinafter referred to as a "thermal oxide film".

A polysilicon layer having a thickness of about 300nm is deposited by Chemical Vapor Deposition (CVD) to cover the gate insulating films 12a, 12 b. During or after the process of polysilicon layer deposition, impurity ions are added to the polysilicon layer to determine its conductivity type and reduce its resistance to a level that can be used as a gate electrode. Thereafter, the polysilicon layer is selectively thermally etched to form the gate insulating films 12A, 12B.

By using the resist layer (resist layer) as a mask, the polysilicon layer can be dry-etched and patterned, thereby forming the gate electrode layers 14A and 14B made of the remaining part of the polysilicon layer. Then, a thermal oxidation process is performed to form a thermal oxide film on the sidewalls of the gate electrode layers 14A and 14B and the substrate surface. The thermal oxide film formed on the substrate surface is thicker than the gate insulating films 12a, 12b, for example, about 44nm in thickness. The integrated insulating film including the thermally oxidized gate insulating films 12A, 12B, and the thermally oxidized film on the sidewalls of the electrode layers 14A, 14B will be hereinafter collectively referred to as an insulating film 12. The insulating film 12 has a projection formed of a laminated structure of an insulating film 12A, an electrode layer 14A, and an insulating film 12A, and a laminated structure of an insulating film 12B, an electrode layer 14B, and an insulating film 12B. There are also other protrusions (not shown) having a height less than the protrusions formed by these stacked structures.

A polysilicon layer 16 of approximately 300nm thickness is deposited by CVD, covering the insulating film 12. The resistance of the polysilicon layer 16 can also be reduced by implanting impurity ions.

In the peripheral ring region (as shown in fig. 5), on one surface of the substrate 10, a thermally oxidized gate insulating film 128 is formed, and then a polysilicon layer 14S is formed. The insulating film 12s is formed by a thermal oxidation process used in forming the gate insulating films 12a, 12 b. The polysilicon layer 14S is formed by CVD, resistance reduction, and patterning processes used in forming the gate electrode layers 14A, 14B. Thereafter, the polysilicon layer 16 is also formed in the peripheral region by the CVD process used in forming the polysilicon layer 16 (shown in fig. 1).

In the process shown in fig. 2, photolithography is used to form resist layers 18A and 18B having a desired gate electrode pattern on the polysilicon layer 16. Each of the resist layers 18A and 18B covers the upper surface of the protrusions but does not cover at least a portion of the sidewalls of the protrusions. One of the resist layers 18A and 18B may cover the bump sidewalls in other regions not shown in fig. 2. The space between two adjacent resist layers 18A and 18B is set to 0.3 to 0.6 μm.

In the peripheral annular region, as shown in fig. 5, a resist layer 18S having a desired gate electrode pattern is formed by a photolithography process used in forming the resist layers 18A and 18B. The thickness of each of the resist layers 18A, 18B, and 18S is about 2 μm.

In the processes shown in fig. 3 and 4, the plasma etching process is performed by using an Electron Cyclotron Resonance (ECR) plasma etching system using high-density plasma. In the process shown in fig. 3, the substrate 10 is placed in a process chamber of an ECR plasma etching system, and the polysilicon layer 16 is etched by using the resists 18A and 18S as masks, thereby forming gate electrodes 16A and 16B having a pattern corresponding to the resists 18A and 18B. The process is a first plasma etch process. The first plasma etch process is terminated in a state where polysilicon spacer residues 16a-16d are left on the sidewalls of the protrusions. For example, the etching conditions are:

gas flow rate: HBr/Cl₂＝50/50sccm

Pressure in the process chamber: 4.0m Torr

Microwave power: 1800W

RF bias power: 60W

The polysilicon etch rate becomes 320 nm/min.

This first plasma etching process used as the main etching process has strong shape anisotropy, so that a protrusion having a vertical wall shape or a forward tapered shape can be formed. However, the polysilicon spacer residues 16a-16d cannot be removed using only the first plasma etch process. To preserve the shape anisotropy, HBr/Cl can be utilized₂/O₂Or the like, and the pressure in the process chamber is preferably set in the range of 1.0 to 5.0m Torr. To obtain a suitable etch rate, it is preferable to set the microwave power in the range of 1500-2000W and the RF bias power in the range of 40-80W.

In the peripheral ring region, as shown in fig. 6, the polysilicon layer 16 is selectively etched by using the resist layer 18S as a mask, thereby forming a gate electrode layer 16S by a first plasma etching process. On the sidewalls of the polysilicon layer 14S, polysilicon spacer residues 16e and 16f remain.

After the polysilicon residues 16a-16d are present in the first plasma etch process, a second plasma etch process is performed as shown in fig. 4. In a second plasma etch process, the polysilicon spacer residues 16a-16d are removed from the bump sidewalls using the resist layers 18A and 18B as a mask and using HBr, a gas, as an etch gas. For example, the etching conditions are:

gas flow rate: HBr 100sccm

Pressure in the process chamber: 6.0m Torr

Microwave power: 1200W

RF bias power: 15W

The polysilicon etching rate becomes 80-120 nm/min.

The second plasma etch process is the polysilicon residue removal process that forms a feature of the present invention. Using HBr as an etching gas without using a gas such as Cl₂And SF₆These gases and gases such as O₂And CF₄These sidewall protection films form gas. HBr, Cl₂And SF₆Horizontal etch rates of these three gases are in Cl₂＜HBr＜＜SF₆The order of (a) becomes large. Cl due to the small horizontal etch rate₂The polysilicon spacer residues 16a-16d cannot be removed. Due to SF₆The etching rate of (a) is too fast, so that the size can be reduced, and because of the side etching, the notch can be formed. Since HBr has a small horizontal etch rate in addition to the vertical etch rate, polysilicon residues 16a-16d can be effectively removed. Using e.g. O₂These gases to form SiO_xThe sidewall protection film maintains the formation anisotropy. O is not used in the second plasma etching process₂Because the horizontal etch rate is reduced.

In order to completely remove the polysilicon spacer residues 16a-16d from the bump sidewalls, it is necessary to irregularly radiate Br ions on the substrate surface. Finally, it is preferable to set the pressure in the process chamber to 5.0 to 10.0m Torr, which is slightly higher than the pressure used for the high-density plasma.

In the second plasma etching process using HBr, which is a gas, if the RF bias power is set high in order to increase the etching rate, the etching selectivity ratio of the polysilicon layer to the thermal oxide film becomes 10 or less, so that the thermal oxide film as the underlying film (underlying film) may be damaged, for example, holes may be formed in the underlying film. It is preferable that the etching selection ratio of the polycrystalline silicon layer to the thermal oxide film is set to about 20-40. For this reason, it is preferable to set the RF bias power relatively low in the range of 10-20W.

The polysilicon spacer residues 16a-16d can be completely removed from the bump sidewalls, which are not removed in the normal case, using the second plasma etch process under the above conditions. Since the above-described conditions are suitable for the shape anisotropy in the micropattern, the sidewalls of the polysilicon layers 16A and 16B subjected to the first plasma etching process are not subjected to a size reduction process such as side etching. No notch is formed on the interface between the etched polysilicon layers 16A and 16B and the underlying insulating film 12.

In the peripheral ring-shaped region, as shown in fig. 7, the polysilicon layer 14S and the polysilicon residues 16e and 16f are etched and removed by using the resist layer 18S as a mask and using a second plasma etching process, thereby forming a polysilicon gate electrode layer 14S having a pattern corresponding to the resist layer 18S. The gate electrode layer 14S and the gate electrode layer 16S stacked thereon constitute one gate electrode.

After the second plasma etching process, a third plasma etching process is performed by using the resist layers 18A, 18B, and 18S as masks. The process is an over-etch process. For example, the etching conditions are:

gas flow rate: HBr/O₂＝100/6sccm

Pressure in the process chamber: 2.0m Torr

Microwave power: 1200W

RF bias power: 15W

The etching selectivity ratio of the polysilicon layer to the thermal oxide film was about 180 and the etching amount was about 220 nm. By using such over-etching, the polysilicon residue in the under-bump region can be removed. If the second plasma etch is not performed and only the third plasma etch is performed, the polysilicon spacer residues 16a-16d cannot be removed although their heights are small.

In the third plasma etching process, Cl may be utilized₂And O₂Substitute for HBr and O₂If HBr/O is used as the etching gas₂Mixed gas of (5) or Cl₂/O₂By controlling O in the mixed gas of₂Is set higher than the flow rate ratio ofThe etching selectivity can reduce the damage to the thermal oxide film below. For example, if O is to be added₂The flow ratio of (1.0 to 5.0m Torr) is set to about 6 to 40%, the pressure is set to 1.0 to 5.0m Torr, and the RF bias power is set to about 10 to 30V, then the etching selectivity ratio of the polysilicon film to the underlying thermal oxide film can be set to about 150 to 200, so that the over-etching is performed in the range of 00 to 240 nm.

After the third plasma etching process, as shown in fig. 4 and 7, the resists 18A, 18B, and 18S are removed by a known ashing process or the like.

In the above-described embodiment, an ECR plasma etching system is used as the high-density plasma etching system. The present invention is not limited thereto, and other systems such as an Inductively Coupled Plasma (ICP) etching system and a plasma etching system using a helicon wave may also be utilized. These etching systems are all known as high density plasma etching systems.

The invention has been described above in connection with preferred embodiments. The invention is not limited to the embodiments described above. It is obvious that those skilled in the art can make various modifications, improvements, combinations, and the like.

Claims (5)

1. A method of etching polysilicon, the method comprising the steps of:

preparing a semiconductor substrate (10), forming an insulating film (12S) on one surface of the substrate, forming a polysilicon layer (14S), and then forming a polysilicon layer (16) covering the polysilicon layer (14S) on the insulating film;

forming a resist layer (18S) on the polysilicon layer (16), the resist layer having a predetermined pattern that does not cover at least a portion of the sidewalls of the polysilicon layer (14S);

using HBr and Cl₂Mixed gas ofPerforming a first plasma etching process for etching the polysilicon layer (16) using the resist layer (18S) as a mask, forming a layer (16S) having a pattern corresponding to the resist layer (18S), and polysilicon residues on sidewalls of the polysilicon layer (14S), leaving polysilicon residues (16e and 16 f);

performing a second plasma etching process for removing polysilicon residues using HBr gas and the resist layer (18S); and

a step of performing a third plasma etching process using the resist layer as a mask and Cl after removing the polysilicon residue₂And O₂Or HBr and O₂The mixed gas is used as an over-etching process of the etching gas.

2. The polysilicon etching method of claim 1, wherein the second plasma etching process is performed at a pressure of 5.0-10.0 mTorr.

3. The polysilicon etching method according to claim 1, wherein the second plasma etching process is performed under a condition that an etching selection ratio of the polysilicon layer to the insulating film is 20-40.

4. The method of claim 3, wherein the second plasma etching process is performed at a RF bias power of 10-20W.

5. A method of etching polysilicon, the method comprising the steps of:

preparing a semiconductor substrate (10), forming an insulating film (12S) on one surface of the substrate, forming a polysilicon layer (14S), and then forming a polysilicon layer (16) covering the polysilicon layer (14S) on the insulating film;

forming a resist layer (18S) on the polysilicon layer (16), the resist layer having a predetermined pattern that does not cover at least a portion of the sidewalls of the polysilicon layer (14S);

using HBr and Cl₂And using said resist layer (18S) as a mask, to carry out a first plasma etching process for etching said polysilicon layer (16), forming a layer (16S) having a pattern corresponding to said resist layer (18S), and polysilicon residues on the sidewalls of the polysilicon layer (14S), leaving polysilicon residues (16e and 16 f); and

performing a second plasma etching process for removing polysilicon residues using HBr gas and the resist layer (18S);

wherein on a major surface portion of the substrate, wherein:

the main surface of the substrate has an insulating film with projections and a polysilicon layer deposited on the insulating film and the projections;

forming a resist layer on the polysilicon layer, the resist layer having a predetermined pattern not covering at least a portion of the side walls of the protrusions;

using HBr and Cl₂And performing the first plasma etching process of etching the polysilicon layer using the resist layer as a mask, so as to leave the polysilicon layer having a pattern corresponding to the resist layer and polysilicon residues formed from a portion of the polysilicon layer remaining on the bump sidewalls.