HK1060440A - Layout and process for a device with segmented ball limited metallurgy for the inputs and outputs - Google Patents

Description

Layout and method for device having segmented ball-limiting metallurgy for input/output

Background

1. Field of the invention

The present invention relates to the field of semiconductor Integrated Circuits (ICs), and in particular to a layout and process with segmented gold Ball Limited Metallurgy (BLM) for input/output (I/O).

2. Background of the invention

Input/outputs in the device are used to define and distribute electrical power, ground and input/output signals. The input/output is soldered to the case or the circuit board with a lead composed of gold (Au) or copper (Cu) wire. However, bump bonding (bumping) tends to be more advantageous than wire bonding when the number of inputs/outputs reaches 400 to 1000.

Fig. 1(a) and 1(b) show solder bumps 15 with a diameter of 1 and a pitch of 2. Solder bumps 15 are formed on the Ball Limiting Metallurgy (BLM) 14. Ball Limiting Metallurgy (BLM) is also known as Pad Limiting Metallurgy (PLM) or Under Bump Metallurgy (UBM). The ball limiting metallurgy 14 is connected to the lower layer bond pad 11b via a via 12 in the passivation layer 13. The passivation layer 13 comprises one or more layers of material, such as a layer of silicon oxide, silicon nitride or polyimide, which act as a barrier against moisture, ions or contaminants. The pad 11b is a soldered portion of the metal line 11a in the metal top layer of the device. The metal line 11a is connected to the lower layer, i.e., the lower layer line 9, through the via 10. Devices typically have 2 to 8 metal layers, so vias and metal lines alternate vertically until electrical contacts are formed as desired portions of the IC or substrate.

Bump bonding significantly improves the access to the core region and maximizes the utilization of the silicon region. Fig. 1(a) and 1(b) show the area array 3 of bumps 15 over the entire active area of the chip. The array 3 is substantially periodic and may be face-centered cubic or hexahedral to provide a higher density of the protrusions 15. The bump-bonded device is flip-chip packaged (FC). Solder bumping technology based on controlled flat chip attach (C4) may be used for Direct Chip Attach (DCA) to conductive traces on a housing or circuit board. The circuit board may be a ceramic substrate, a Printed Wiring Board (PWB), a flex circuit, or a silicon substrate. Bump bonding of the device also reduces the resistance and inductance in the input/output, and therefore, significantly improves performance.

High performance devices, such as microprocessors, Application Specific Integrated Circuits (ASICs), programmable field gate arrays (FPGAs) or system on a chip (SOCs), may have 600 to 7000I/os, and therefore need to be scaled down to limit the die size. Wire bonding is performed with a wire diameter of less than 25 microns, a ball diameter of less than 40 microns, and a pitch of less than 60 microns. Bump bonding involves bumps of 45 to 90 microns in diameter and 125 to 300 microns in pitch.

Power control and thermal control are critical as the size of the leads or bumps decreases. If the junction temperature of each I/O exceeds 100 to 125 deg.C, or the current density exceeds 150 to 425mA, the I/O may be damaged. Electromigration and thermomigration cause an increase in resistance value by more than 2 orders of magnitude before causing the final open circuit. The temperature increase may also cause intermetallic diffusion. The resulting intermetallic alloy is brittle and can also cause stress failure. Temperature Coefficient of Thermal Expansion (CTE) mismatches can cause large shear stresses on the leads or bumps. For example, the temperature Coefficient of Thermal Expansion (CTE) of solder is 30 ppm/deg.C, which is comparable to 7 ppm/deg.C for ceramic substrates and 5 ppm/deg.C for silicon substrates. If the temperature rising speed exceeds 15 to 20 c/min, the lead or the bump may be damaged due to thermal shock. Thermal cycling at low temperature rise rates can also cause the leads or bumps to crack due to fatigue from elastic and peristaltic deformation.

There is therefore a need for a new layout and process for a device having a segmented ball-defining metallurgical structure for input/output

Drawings

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1(a) is a plan view of a prior art projection;

FIG. 1(b) is a cross-sectional view of a prior art projection;

FIG. 2(a) is a plan view of a boss connected to a BLM having two segments;

FIG. 2(b) is a cross-sectional view of a projection attached to a BLM having two segments;

FIG. 3 is a plan view of a boss connected to a BLM having four segments;

FIG. 4 is a plan view of a bump connected to a BLM having two segments, each segment connected to two vias;

FIG. 5 is a plan view of a bump connected to a BLM having two segments, each segment connected to two pads;

fig. 6(a) - (f) are schematic diagrams of an embodiment of a process of forming a segmented BLM.

Detailed Description

The present invention discloses a new layout and new process for a device having a segmented ball limited metallurgy structure (BLM) for input/output (O/I). The present invention also discloses a segment of a BLM that may be electrically connected to more than one via or pad. The present invention can reduce inductance and minimize I/O failure due to operation at high current and high temperature.

In the following description, numerous specific details are set forth, such as specific materials, dimensions, and processes, in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without these specific details. In other instances, well-known semiconductor devices and processes have not been described in detail in order to avoid unnecessarily obscuring the present invention.

The layout of the device of the present invention is first described.

In a first embodiment of the invention, as shown in fig. 2(a) and 2(b), the BLM is divided into two segments 24 n. One or more of the segments 24n may have a layout that is substantially polygonal, such as hexagonal or octagonal. These segments 24n are close to each other. The gap 23 between the two segments 24n will prevent the defect occurring in any single segment 24n from propagating. The segment 24n also provides redundancy against defects that occur at any time in the segment 24 n.

Two segments 24n are connected to the same upper level bump 25, as shown in fig. 2(a) and 2(b), and each segment 24n is also connected to one lower level via 22 n. One or more of the vias 22n have a polygonal layout such as a square or rectangle. The vias 22n are close to each other. The spacing 26 between the vias 22n prevents the propagation of defects that occur in any single via 22 n. The vias 22n also provide redundancy that prevents defects from ever occurring in the vias 22 n. One or more vias 22n may be laterally displaced from the upper level bump 25 to be electrically connected thereto. The via 22n is connected to the same lower layer pad 21 b. The pad 21b is a part of the lower layer lead 21a which has been bonded, and whether aligned or not, the via 22n can be ensured to be in full contact with the lead 21 a.

According to a second embodiment of the present invention, the BLM may be divided into more than two sections, for example, four sections 34n, as shown in fig. 3. The four segments 34n are all connected to the same lower level bump 35. Each segment 34n is connected to a lower level via 32 n. The four vias 32n are all connected to the same lower-layer lead 31a at the pad 31 b.

In accordance with a third embodiment of the present invention, each segment 44n of the BLM may be connected to more than one via 42n, such as two vias 42n, as shown in fig. 4.

According to the fourth embodiment of the present invention, each segment 54n of the BLM may be connected to more than one pad 51b, for example, two pads 51b, as shown in fig. 5.

The process of forming the segmented BLM of the present invention is described below.

First, the passivation layer 23 is patterned to form a via 22n to expose the pad 21b, as shown in fig. 6 (a). Patterning may be performed with photoresist or photodefinable polyimide.

After that, the BLM is formed generally by a sputtering method. The BLM generally has a lower layer 24a and an upper layer 24b, as shown in fig. 6 (b). The lower layer 24a provides good solder adhesion to the attach pad 21b and the passivation layer 23. The lower adhesive layer 24a may be formed of a titanium (Ti) film having a thickness of 200-1500  (angstroms). Other metals that may be used as the underlayer 24a include titanium Tungsten (TiW), tantalum (Ta), chromium-copper (Cr-Cu) or chromium (Cr).

The upper layer 24b has good adhesion to the lower layer 24a and is wettable by the solder. The upper layer 24b is a layer formed from nickel-vanadium with a thickness of 1000 a and 8000 a 8000  a. Other metals that may be used as the upper layer 24b include nickel (Ni), chromium-copper (Cr-Cu), copper (Cu). Gold (Au), nickel-gold (Ni-Au), or copper-gold (Cu-Au).

The upper layer 24a and the lower layer 24b of the BLM function as diffusion barriers for barrier metals. However, additional layers are interposed between the upper and lower layers 24a, 24b depending on the type of metallurgy selected for the solder bumps and BLM. To prevent diffusion between the metals. Any intermediate layer used must have good adhesion to the upper and lower layers 24a, 24 b. Depending on the material used for the upper layer 24a, a top layer of, for example, copper (Cu) or gold (Au) may be added to the upper layer 24a to prevent oxidation and corrosion of the upper layer 24 a.

Photoresist and patterning are added to etch away the BLM in the gaps 23 between the vias 22n, as shown in fig. 6 (c). After stripping the photoresist, another layer of photoresist is added and patterned to allow solder to plate onto the BLM, as shown in fig. 6 (d). The solder may be a lead-tin (Pb-Sn) solder, or a lead-indium (Pb-In) solder. Tin prevents oxidation and enhances the solderability of the BLM.

The solder in the openings of the photoresist will fill the gaps 23 between the vias 22n, melt and eventually rise up on the photoresist to form a mushroom shape, as shown in fig. 6 (d). The height of the photoresist and the pitch of the openings for the bumps must be well controlled to form a uniform solder height. The solder height and uniformity of alloy composition are related to the current density on the wafer and certain parameters of the plating solution. Solder bubbling (voiding) due to the generation and trapping of hydrogen gas and plating solution left in the plated solder must be prevented.

The excess portions of the upper layer 24a and the lower layer 24b which are not covered with the solder 25 are etched away as shown in fig. 6 (f). The solder on the segment 24n of the BLM is heated in an oven or furnace to reflow the solder into the individual bumps 25, as shown in fig. 6 (f). The melting temperature of the solder in the bumps 25 on the chip is related to the type of metals chosen and their relative concentration. For example, the reflow temperature for high lead solder at a weight ratio of 95Pb/5Sn is 300-360 ℃. While the reflow temperature of a low melting solder, for example, in a 37Pb/63Sn weight ratio, is 180-240 c.

The bumps 25 on the chip may be connected to corresponding bumps on the housing or circuit board. The bumps on the housing or circuit board are formed with tin (Sn) or low melting point (e.g., 160 c) solder so that the bumps on the chip do not reflow during the chip attach process.

The segmented BLM may be compatible with other reflow processes for forming the bumps of the I/O. Only a few embodiments are described herein. Non-electrical methods of nickel (Ni) plating do not require a mask, but require an intermediate layer, e.g., zinc (Zn) can be first plated on aluminum (Al) wires. Conductive posts surrounded by a non-conductive dielectric may be used to plate solder. Solder dams or dams may be used to limit bump spread during reflow. The solder balls may be reflowed before the excess BLM is etched to minimize the portion of the BLM under the bump 25 that is cut away. It is not necessary to sequentially etch the upper layer 24a and the lower layer 24b of the BLM. The BLM may be protected by photoresist during photolithography.

The segmented BLM may also be compatible with other materials for the protrusions. Low alpha particle solder may be used to prevent softening defects. Alpha particle emission below 0.02 counts/hour/cm in sensitive semiconductor devices such as memory chips². With respect to environmental requirements, metallic lead (Pb) is required to be excluded from solder about 2004. Lead-free bumps may be constructed using Alternative Ball Metallurgy Structures (ABMs). ABM can be exemplified by tin (Sn), silver (Ag), copper (Cu), antimony (Sb), indium (in)(In), and cadmium (Cd). One example is a ternary tin-silver-copper (Sn-Ag-Cu) alloy with a melting point of about 215 c. Other examples include a tin-copper (Sn-Cu) binary alloy or a tin-silver (Sn-Ag) binary alloy.

The solder itself may be removed from the conductive adhesive (ECA) or paste by stenciling the bumps. The ECA includes an epoxy resin with a filler of conductive particles, for example, a silver-loaded epoxy resin. The conductivity may be anisotropic or isotropic. ECA is commonly used for heat-sensitive devices because the temperature required to cure the adhesive by polymerizing the resin adhesive is less than 160 ℃. ECAs have certain advantages over solder bumps. The contact resistance of ECA is 25 μ Ω, which is higher than 10 μ Ω of the contact set for solder. ECA also has a low thermal conductivity of 1-3W/mK. Therefore, the device must operate at low power. But a conductive polymer having a thermal conductivity of 60W/mK comparable to that of solder has been developed.

Various embodiments of a device with a segmented BLM and its fabrication process have been described above. The projections described in the above embodiments are overlaid on the segment BLM. However, the present invention contemplates overlaying the segmented pad with a wire. In that case, the wire bonder is modified to connect the lead wires to more than two segments of the bond pad to achieve the same effect of reducing inductance and preventing I/O failures.

The foregoing embodiments and many of the details are presented for purposes of understanding the invention. Those skilled in the art will appreciate that many features of one embodiment may be used in other embodiments as well. Those skilled in the art will recognize that various equivalent substitutions may be made with respect to these specific materials, processes, dimensions, and concentrations described herein. It is to be understood that the detailed description of the invention is intended to be illustrative of the invention and not limiting, the scope of the invention being defined by the appended claims.

The present invention thus illustrates a new layout and new process for a device with segmented BLM for input/output.

Claims (28)

1. A device having an input/output connected to a package or circuit board, comprising:

a pad;

a ball defining metallurgical structure (BLM) on the pad, the ball defining metallurgical structure having more than two segments; and

a protrusion disposed on the segment.

2. The device of claim 1, wherein the bump comprises a solder such as lead-tin or lead-indium.

3. The device of claim 1, wherein the bumps are lead-free.

4. The device of claim 1, wherein the bump comprises a ternary alloy such as tin-silver-copper.

5. The device of claim 1, wherein the bumps comprise a conductive adhesive or polymer.

6. The device of claim 1, wherein the ball-defining metallurgical structure provides a metal diffusion barrier.

7. The device of claim 1, wherein the ball-defining metallurgical structure comprises a lower layer and an upper layer.

8. The device of claim 7 wherein the lower layer comprises titanium having a thickness of about 200 a and 1500 a 1500  a.

9. The device of claim 7 wherein the upper layer comprises nickel-vanadium having a thickness of about 1000 a and 8000 a 8000  a.

10. The device of claim 1, wherein the segments comprise a substantially polygonal layout.

11. The device of claim 1, further comprising a plurality of vias, a segment being electrically connected to two or more of said vias.

12. The device of claim 11, wherein the via is laterally offset from a center of the bump to which it is electrically connected.

13. The device of claim 11, wherein the via comprises a substantially polygonal layout.

14. The device of claim 4, further comprising a plurality of bond pads, wherein a segment is electrically connected to two or more of said bond pads.

15. The device of claim 14, wherein the pad is laterally offset from a center of the bump to which it is electrically connected.

16. A method of forming a ball-defined metallurgical structure on a device, comprising:

forming a top metal layer of the device, the top metal layer including leads with pads;

forming a passivation layer on the top metal layer;

etching a via through the passivation layer to expose the pad;

forming a ball-defining metallurgical structure on the via;

dividing the ball-defining metallurgical structure into a plurality of segments such that each segment covers at least one of the vias;

forming a bump on a segment of the ball-defining metallurgical structure;

the bumps are connected to a package or a circuit board.

17. The method of claim 16, wherein the ball-defining metallurgical structure comprises a lower layer and an upper layer.

18. The method of claim 17 wherein the underlayer comprises titanium 200 a and 1500 a 1500  a thick.

19. The method of claim 17 wherein the upper layer comprises nickel-vanadium having a thickness of 1000 a-8000 .

20. The method of claim 16, wherein the bumps comprise solder that is electroplated with a photoresist mask and reflowed after the photoresist is removed.

21. The method of claim 16, wherein the bumps comprise a solder such as lead-tin or lead-indium.

22. The method of claim 16, wherein the bumps are lead free.

23. The method of claim 16, wherein the bump comprises a ternary alloy such as tin-silver-copper.

24. The method of claim 16, wherein the bumps comprise a conductive adhesive or polymer.

25. The method of claim 16, wherein the bumps comprise a silver-loaded epoxy.

26. A device having an input/output connected to a package or circuit board, comprising:

a pad having two or more segments;

a wire connected to the segment.

27. The device of claim 26, further comprising vias, wherein a segment is electrically connected to two or more of the vias.

28. The device of claim 26, further comprising leads, wherein a segment is electrically connected to two or more of the leads.