HK1060229B - A modulation technique for transmitting multiple high data rate signals through a band limited channel - Google Patents

Description

Modulation technique for transmitting multiple high data rate signals over a band limited channel

Technical Field

The present invention relates to modulation techniques for transmitting multiple high data rate signals over a band limited channel.

Background

It is often desirable to provide higher data rates of data over channels having limited bandwidth. A number of modulation techniques have been developed to increase the data rate through a channel. For example, M-ary Phase Shift Keying (PSK) and Quadrature Amplitude Modulation (QAM) techniques allow compression by encoding multiple data bits in each transmitted symbol. Such systems have their own limitations. First, the hardware associated with such systems is expensive. This is because a high level of channel linearity is required in order for these techniques to operate properly. Then further signal processing of carrier tracking, symbol recovery, interpolation and signal shaping has to be performed. Second, such techniques are sensitive to multipath effects. These effects need to be compensated for in the receiver. Third, these systems often require bandwidth for the desired data rate that exceeds the bandwidth available in certain applications (e.g., broadcasting FM subcarrier service on an in-band channel).

It is also desirable to provide several data signals over one channel. Some modulation techniques make full use of the channel, while others leave a portion of the channel unused. Frequency domain multiplexing and time domain multiplexing are two techniques for sharing a channel between multiple signals. By sharing the channel in this manner, the overall throughput through the channel is increased.

Disclosure of Invention

In accordance with the principles of the present invention, a digital data modulator comprises: a plurality of digital data signal sources having a common data bit period; a plurality of encoders, each encoder encoding a respective one of the plurality of digital data signal sources using a variable pulse width code having edges that occur in respective non-overlapping intervals within a data bit period; a plurality of pulse signal generators, each pulse signal generator generating a respective pulse representing an edge of a corresponding one of the encoded plurality of digital data signals; and a carrier signal generator generating a carrier signal having carrier pulses corresponding to the respective pulses.

According to another aspect of the present invention, a digital data demodulator includes: a source of modulated signals comprising successive bit periods, each bit period having a plurality of non-overlapping intervals respectively associated with respective ones of the successive bit periods, each interval comprising a carrier pulse, wherein the carrier pulses are spaced relative to the carrier pulses in other associated intervals, the carrier pulses representing a respective variable pulse width encoded digital data signal; a detector that demodulates the modulated signal to generate pulses corresponding to the received carrier pulses; a plurality of decoders, each decoder decoding pulses received in each of a plurality of associated intervals in the bit period in a manner to decode variable pulse width encoded digital data information in the pulses to produce a corresponding digital data signal.

According to another aspect of the present invention, a digital data modulation method includes the steps of: providing a plurality of digital data signals having a common data bit period; encoding each of the plurality of digital data signals using a variable pulse width code having edges that occur in respective non-overlapping intervals within the data bit period; generating respective pulses representing edges of a corresponding one of the encoded plurality of digital data signals; and generating a carrier signal having carrier pulses corresponding to the respective pulses.

According to another aspect of the present invention, a digital data modulator includes: a first digital data signal source having a data bit period; a first encoder for encoding the first digital data signal using a variable pulse width code having edges that occur in a first interval within the data bit period; a first pulse signal generator generating respective pulses representing edges of the encoded first digital data signal; a second digital data signal source having the data bit period; a second encoder for encoding the second digital data signal using a variable pulse width code having edges occurring in a second interval within the data bit period that does not overlap the first interval; a second pulse signal generator generating respective pulses representing edges of the encoded second digital data signal; a carrier signal generator for generating a carrier signal having carrier pulses corresponding to respective first pulses in the first intervals and having carrier pulses corresponding to respective second pulses in the second intervals.

Techniques in accordance with the principles of the present invention are used to simultaneously transmit multiple independent high data rate signals over a single channel. The system according to the invention can be implemented using relatively inexpensive circuitry, is insensitive to multipath interference and provides substantial bandwidth compression.

Drawings

In the drawings:

FIG. 1 is a block diagram of a modulator for generating a relatively high data rate signal within a relatively narrow bandwidth;

FIG. 2 is a waveform diagram useful in understanding the operation of the modulator shown in FIG. 1;

FIG. 3 is a block diagram of a receiver that can receive a signal modulated as in FIG. 1;

FIG. 4 is a spectral diagram useful in understanding the application of the modulation technique shown in FIGS. 1 and 2;

FIG. 5 is a block diagram of an FM broadcast transmitter having an in-band on-channel digital transmit channel implemented using the modulation techniques shown in FIGS. 1 and 2;

fig. 6 is a block diagram of an FM broadcast receiver that may receive signals modulated by the FM broadcast transmitter shown in fig. 5;

FIG. 7 is a waveform diagram useful in understanding the operation of a modulator according to the principles of the present invention;

fig. 8 is a block diagram of another embodiment of the modulator of fig. 1 and 2, also for transmitting an auxiliary data signal along with a high data rate data signal;

FIG. 9 is a block diagram of a receiver that may receive signals generated by the modulator shown in FIG. 8;

FIG. 10 is a waveform diagram useful in understanding the operation of a modulator according to the principles of the present invention;

fig. 11 is a block diagram of a modulator according to the principles of the present invention;

fig. 12 is a block diagram of a receiver that can receive signals generated by the modulator shown in fig. 11 in accordance with the present invention.

Detailed Description

Fig. 1 is a block diagram of a modulator for generating a high data rate, narrowband signal. IN fig. 1, an input terminal IN receives a high data rate digital signal. The input IN is connected to an input of the encoder 10. An output of the encoder 10 is connected to an input of a differentiator 20. The output of the differentiator 20 is connected to the input of a level detector 25. An output of the level detector 25 is connected to a first input of a mixer 30. A local oscillator 40 is connected to a second input of the mixer 30. The output of the mixer 30 is connected to the input of a Band Pass Filter (BPF) 50. The output of the BPF50 is connected to the output OUT, producing a modulated signal representing the digital signal at the input IN.

Fig. 2 is a waveform diagram useful in understanding the operation of the modulator shown in fig. 1. To more clearly illustrate the waveforms, fig. 2 is not shown to scale. IN the exemplary embodiment, the high data rate digital signal at input IN is a bi-level signal IN the form of a non-return-to-zero (NRZ). This signal is shown in the upper waveform of fig. 2. The NRZ signal carries successive bits, each of which lasts for a predetermined period, called bit period, indicated by a dashed line in the NRZ signal, and has a corresponding frequency, called bit rate. The level of the NRZ signal represents the value of the bit in all known ways. The encoder 10 operates to encode the NRZ signal using a variable pulse width code. In the illustrated embodiment, the variable pulse width code is a variable alert code. Variable mask coding is described in detail in international patent application PCT/US99/05301 filed by Chandra Mohan on 11.3.1999. In this patent application, the NRZ signal is bit-encoded in the following manner.

Each bit period in the NRZ signal is encoded as a transient in the encoded signal. An encoding clock M times the bit rate is used to phase encode the NRZ signal. In the above-mentioned patent application, the encoding clock is running at a rate 9 times the bit rate. When the NRZ signal transitions from a logic "1" level to a logic "0" level, a transition is generated in the encoded signal 8 encoding clock cycles (M-1) from the previous transition. When the NRZ signal transits from a logic "0" level to a logic "1" level, a transition is generated 10 coding clock cycles (M +1) from the previous transition in the coded signal. When the NRZ signal is not transient, i.e. if consecutive bits have the same value, then in the encoded signal, 9 encoding clock cycles (M) from the previous transient generate a transient. The variable mask encoded signal (VAC) is shown as the second waveform in fig. 2.

The variable mask encoded signal (VAC) is differentiated by a differentiator 20 to produce a pulse sequence that is time aligned with the transients in the VAC signal. The differentiator also imparts a 90 degree phase shift to the VAC modulated signal. Leading edge transients produce positive going pulses and trailing edge transients produce negative going pulses, all in a well known manner. Differentiated VAC signalA third signal as in fig. 2 is shown. TheThe signal is level-detected by a level detector 25 to generate a three-level pulse train having a constant amplitude. When differentiated VAC signalHaving a value greater than a positive threshold, generating a level signal having a high value; when differentiated VAC signalHaving a value less than a negative threshold, a level signal having a low value is generated, otherwise it has an intermediate value, all in a known manner. This LEVEL signal is shown as the fourth signal (LEVEL) in fig. 2.

The LEVEL signal modulates a carrier signal from a local oscillator 40 in a mixer 30. The positive pulses generate carrier signal pulses having a first phase and the negative pulses generate carrier signal pulses having a second phase. The first and second phases are preferably completely 180 degrees out of phase. The carrier signal pulse is preferably exactly one code clock period long and, in the illustrated embodiment, has a duration of 1/9 of exactly NRZ bit periods. The frequency signal of the local oscillator 40 is selected such that at least 10 cycles of the local oscillator signal preferably occur within the carrier signal pulse time period. In fig. 2, the carrier signal CARR is shown as a waveform at the bottom end, wherein the carrier signal is represented by vertical hatching within the respective rectangular envelopes. In the CARR signal shown in fig. 2, the phase of a carrier pulse generated in response to a positive-going LEVEL pulse is denoted by "+" and the phase of a carrier pulse generated in response to a negative-going LEVEL pulse is denoted by "-". The "+" and "-" merely indicate a complete 180 degree phase difference and do not indicate any absolute phase.

The BPF50 filters all out-of-band fourier components in the CARR signal, as well as its own carrier component and one of the sidebands, leaving only one single sideband. The output signal OUT from the BPF50 is thus a Single Sideband (SSB) phase or frequency modulated signal representing the NRZ data signal at the input IN. The signal may be transmitted to the receiver by one of many well-known transmission techniques.

Fig. 3 is a block diagram of a receiver that can receive a signal modulated by the modulator shown in fig. 1 and 2. IN fig. 3, the input IN is connected to a source of modulated signals as described above with reference to fig. 1 and 2. The input terminal IN is connected to the input terminal of the BPF 110. The output of the BPF 110 is connected to the input of the integrator 120. The output of the integrator 120 is connected to the input of the limiting amplifier 130. The output of the limiting amplifier 130 is connected to the input of the detector 140. An output of the detector 140 is connected to an input of a decoder 150. An output of the decoder 150 reproduces the NRZ signal represented by the signal modulated at the input IN and is connected to an output OUT.

In operation, as described above, the BPF 110 filters out-of-band signals, passing only the modulated SSB signals. Integrator 120 compensates for the 90 degree phase shift introduced by differentiator 20 (of fig. 1). The limiting amplifier 130 limits the amplitude of the signal from the integrator 120 to a constant amplitude. The signal from the limiting amplifier 130 corresponds to the carrier pulse signal CARR shown in fig. 2. The detector 140 is also an FM discriminator or Phase Locked Loop (PLL) for demodulating FM or PM modulated carrier pulse signals, respectively. The detector 140 detects the carrier pulses and generates a bi-level signal having transients represented by the phase and timing of those pulses. The output of detector 140 is a variable bit width signal corresponding to the VAC signal of fig. 2. The decoder 150 performs the inverse operation of the encoder 10 (of fig. 1) and generates an NRZ signal corresponding to the NRZ signal in fig. 2 at an output terminal OUT. The above-mentioned us patent application (RCA88,945) describes a decoder 150 that can be used in fig. 3. The NRZ signal at the output OUT is then processed by an application circuit (not shown).

Because the carrier pulses (signal CARR of fig. 2) occur at precisely defined times with respect to each other and because those pulses are clipped in duration, detector 140 may be enabled only at the time of the intended pulse. For example, in the illustrated embodiment, each pulse has a duration of 1/9 times the time between the NRZ signal transient times, as described in detail above. At 8/9 from the time between NRZ signal transients from the previous carrier pulse (representing the trailing edge), after receiving a carrier pulse, the following pulse is expected to occur only at the time 9/9 (no transient) or 10/9 (leading edge) from NRZ from that pulse, between signal transients. Similarly, at 10/9 from the time between NRZ signal transients from the previous carrier pulse (representing the leading edge), after a carrier pulse is received, the following pulse is expected to occur only at 8/9 (trailing edge) or 9/9 (no transient) from that pulse at the time between NRZ signal transients. The detector 140 needs to be enabled only when a carrier pulse is expected, and only around the time of the duration of the expected pulse.

The window timer, shown as 160 in fig. 3, has an input connected to the status output of detector 140, and an output connected to the enable input of detector 140. The window timer 160 monitors the signal from the detector 140 and enables the detector only when a carrier pulse is expected, and only around the duration of the pulse.

In the illustrated embodiment, the energy in the modulated signal is primarily between 0.44(8/18) and 0.56(10/18) times the bit rate and thus has a bandwidth of 0.11 times the bit rate. This results in a 9-fold increase in the data rate across the bandwidth. Other compression ratios are readily achieved by varying the ratio of the encoding clock to the bit rate, with tradeoffs and limitations that will be readily apparent to those skilled in the art.

The above system can be implemented in a transmitter and a receiver with simpler circuitry than M-ary PSK or QAM modulation techniques. More specifically, in the receiver, after extraction of the modulated signal, a limiting amplifier (e.g., 130) that is both inexpensive and power efficient may be used. Also, encoding and decoding of NRZ signals may be performed with a nominal fast Programmable Logic Device (PLD). Such devices are relatively inexpensive (currently $ 1 to $ 2). In addition, in this system, there is no intersymbol interference, and thus no waveform shaping is required. In addition, no tracking loop is required other than a clock recovery loop.

Because, as described above, carrier transmission occurs only at bit boundaries and does not last for the entire bit period, a time window may be used in the receiver to detect received carrier pulses only when pulses are expected. Thus, the present system does not have multipath problems.

One application of the above modulation technique is the simultaneous transmission of CD quality digital music and FM mono and stereo broadcast audio signals. Fig. 4 is a spectral diagram useful in understanding the application of the modulation technique shown in fig. 1 and 2. Fig. 4a illustrates the power envelope of FM broadcast signals in the united states. In fig. 4a, the horizontal line represents frequency and represents a portion of the VHF band between approximately 88MHz and 107 MHz. The vertical direction represents the signal strength. The allowable envelopes of two adjacent broadcast signal spectra are shown. Each carrier is shown as a vertical arrow. Around each carrier is a sideband carrying a broadcast signal FM modulated on that carrier.

In the united states, FM broadcasters may broadcast mono and stereo audio at full power in sidebands within a 100kHz carrier. In fig. 4a, these sidebands are shown without hatching. The broadcaster can broadcast other information in the sidebands from 100kHz to 200kHz, but the power sent in this band must be 30dB below full power. The hatched portions show these sidebands. Neighboring stations (within the same geographical area) must be separated by at least 400 kHz.

In the spectral diagram of fig. 4b, the upper sideband of the low frequency broadcast signal of fig. 4a is illustrated above the carrier. In fig. 4b, the vertical direction represents the modulation percentage. In fig. 4b, the mono audio signal L + R is transmitted in the 0 to 15kHz sidebands with a modulation level of 90%. The L-R audio signal is transmitted as a double sideband suppressed carrier signal at a modulation level of 45% around a suppressed subcarrier frequency of 38 kHz. The lower sideband (lsb) is from 23kHz to 38kHz and the upper sideband (usb) is from 38kHz to 53 kHz. A pilot tone at 19kHz (half the frequency of the suppressed carrier) is also included in the sidebands around the primary carrier. In this way, 47kHz (i.e., from 53kHz to 100kHz) in the upper (fig. 4b) and lower (not shown) sidebands around the primary carrier are still available for the broadcaster to broadcast additional information at full power. As mentioned above, the power transmitted from 100kHz to 200kHz must be 30dB less than full power.

Using the modulation techniques described above and shown in fig. 1 and 2, a 128 kilobits per second (kbps) signal containing an MP3CD quality audio signal may be encoded and transmitted within a bandwidth of less than 20 kHz. The digital audio signal may be placed, for example, in the 53kHz to 100kHz band in the upper sideband and transmitted as a subcarrier signal along with a periodic broadcast stereo audio signal as shown in fig. 4 b. In fig. 4b, the digital audio signal is the SSB signal centered at 70kHz described above, and covers approximately from 60kHz to 80 kHz. The signal is within the main carrier at 100kHz and is therefore transmitted at full power.

Fig. 5 is a block diagram of an FM broadcast transmitter having an in-band on-channel digital transmit channel implemented in accordance with the modulation techniques described above with reference to fig. 1-3. In fig. 5, the same elements as those shown in fig. 1 are included in the dashed rectangles labeled fig. 1, are labeled with the same reference numerals, and are not described in detail below. As described with reference to fig. 1 and 2, the combination of the encoder 10, differentiator 20, level detector 25, mixer 30, oscillator 40, and BPF50 produces an SSB phase or frequency modulated signal (CARR of fig. 2) representative of the digital input signal (NRZ of fig. 2). The output of the BPF50 is connected to the input of an amplifier 60. The output of the amplifier 60 is connected to a first input of a second mixer 70. A second oscillator 80 is connected to a second input of the second mixer 70. The output of the second mixer 70 is connected to the input of the first filter/amplifier 260. The output of the first filter/amplifier 260 is connected to a first input of the signal combiner 250.

An output of the broadcast baseband signal processor 210 is connected to a first input of a third mixer 220. The third oscillator 230 is connected to a second input of the third mixer 220. The output of the third mixer 220 is connected to the input of a second filter/amplifier 240. The output of the second filter/amplifier 240 is connected to a second input of the signal combiner 250. The output of the signal combiner 250 is connected to the input of a power amplifier 270, the power amplifier 270 being connected to a transmit antenna 280.

In operation, the encoder 10 receives a digital signal representing a digital audio signal. In the preferred embodiment, the signal is a digital audio signal adapted to MP 3. More specifically, the digital audio data stream is Forward Error Correction (FEC) encoded using a Reed-Solomon (RS) code. The FEC encoded data stream is then packetized. The packetized data stream is then compressed into an SSB signal by the circuitry shown in fig. 1, as described in detail above.

The frequency of the signal generated by oscillator 40 is selected to be 10.7MHz, so the digital information from encoder 10 is modulated around the center frequency of 10.7 MHz. The modulation frequency may be any frequency, but is more realistically selected to correspond to the frequency of existing low cost BPF filters. For example, a typical BPF filter has a center frequency of 6MHz, 10.7MHz, 21.4MHz, 70MHz, 140MHz, etc. In the illustrated embodiment, 10.7MHz is selected as the modulation frequency, and the BPF50 is implemented as one of the existing 10.7MHz filters. The filtered SSB signal from the BPF50 is amplified by an amplifier 60 and upconverted by a combination of a second mixer 70 and a second oscillator 80. In the illustrated embodiment, the second oscillator 80 generates a 77.57MHz signal and the SSB is upconverted to 88.27 MHz. The signal is filtered and amplified by a first filter/amplifier 260.

The broadcast baseband signal processor 210 receives a stereo audio signal (not shown) and performs the signal processing necessary to form a baseband composite stereo signal comprising an L + R signal at baseband, a double sideband suppressed carrier L-R signal at a (suppressed) 38kHz carrier frequency and a pilot tone at 19kHz, all in a well-known manner. The signal is then modulated onto a carrier signal at the assigned frequency of the FM station. The third oscillator 230 generates a carrier signal at an assigned broadcast frequency, which in the illustrated embodiment is 88.2 MHz. The third mixer 220 generates a modulated signal that is modulated with the baseband composite mono and stereo audio signals as shown in fig. 4 b. The modulated signal, at a carrier frequency of 88.2MHz, and with standard broadcast audio sidebands as shown in figure 4b, is then filtered and amplified by a second filter/amplifier 240. This signal is combined with the SSB modulated digital signal from the first filter/amplifier 260 at the 88.27MHz center frequency to form a composite signal. The composite signal thus comprises a standard broadcast stereo audio sideband modulated on an 88.2MHz carrier and an SSB modulated signal on the carrier (88.27MHz) carrying a digital audio signal centred at 70kHz as shown in figure 4 b. The composite signal is then power amplified by a power amplifier 270 and provided to a transmit antenna 280 for transmission to an FM radio receiver.

Fig. 6 is a block diagram of an FM broadcast receiver capable of receiving signals modulated by the FM broadcast transmitter shown in fig. 5. In fig. 6, those elements that are the same as those shown in fig. 3 are enclosed by the dashed box labeled in fig. 3, are labeled with the same reference numerals, and are not described in detail. In fig. 6, a receive antenna 302 is connected to an RF amplifier 304. The output of the RF amplifier 304 is connected to a first input of a first mixer 306. The output of the first oscillator 308 is connected to a second input of the first mixer 306. The output of the first mixer 306 is connected to respective inputs of the BPF310 and the tunable BPF 110. The output of the BPF310 is connected to the input of an Intermediate Frequency (IF) amplifier 312, which IF amplifier 312 may be a limiting amplifier. The output of the IF amplifier 312 is connected to the input of the FM detector 314. An output of the FM detector 314 is connected to an input of an FM stereo decoder 316.

In operation, RF amplifier 304 receives and amplifies RF signals from receive antenna 304. The first oscillator 308 generates a signal at 98.9 MHz. The combination of the first oscillator 308 and the first mixer 306 down-converts the 88.2MHz host carrier signal to 10.7MHz and the SSB digital audio signal from 88.27MHz to 10.63 MHz. The BPF310 passes only the 53kHz FM stereo signal sidebands (L + R and L-R) around 10.7MHz in a known manner. The IF amplifier 312 amplifies the signal and provides it to an FM detector 314, which FM detector 314 produces a baseband composite stereo signal. The FM stereo decoder 316 decodes the baseband composite stereo signal in a known manner to produce a mono and/or stereo audio signal (not shown) representative of the transmitted audio signal.

In the illustrated embodiment, the tunable BPF 110 is tuned to a center frequency of 10.63MHz and passes only 20kHz digital audio signals around that frequency. In the illustrated embodiment, the passband of the BPF 110 covers from 10.53MHz to 10.73 MHz. The combination of the BPF 110, the integrator 120, the limiting amplifier 130, the detector 140, the decoder 150, and the window timer 160 operates to extract the modulated digital audio signal and demodulate and decode the signal in the manner described with reference to fig. 3 to reproduce the digital audio signal. The digital audio signal from the decoder 150 is processed by further circuitry (not shown) in a suitable manner to produce an audio signal corresponding to the transmitted digital audio signal. More specifically, the signal is split (depacketize) and any errors introduced during transmission are detected and corrected. The corrected bit stream is then converted to a stereo audio signal in a known manner.

The above-described embodiments provide equivalent compression performance for 1024QAM systems. In practice, however, QAM systems are limited to around 256QAM due to the difficulty of correcting for noise and multipath inter-symbol interference caused by tight constellation spacing. The above system has no ISI problem due to the narrow and wide spacing. In short, higher data rates can be transmitted within a narrower bandwidth channel without the problems associated with other techniques, such as QAM.

Referring back to fig. 2, in the CARR signal, it can be seen that there is a relatively wide spacing between carrier pulses during which no carrier signal is transmitted. These intervals can be further exploited. Fig. 7 is a more detailed waveform diagram of the CARR signal that is helpful in understanding the operation of a modulator that may utilize these spacings. As described above, in the encoder 10 shown in fig. 1, the encoding clock signal has a period of 1/9 times the bit period of the NRZ signal. The dashed vertical lines in fig. 7 represent the encoding clock signal periods. In fig. 7, the bit periods are illustrated from time t1 to time t10 to illustrate that there are nine clock periods in one bit period. However, the bit period is not necessarily time aligned with the NRZ input signal and will most likely be delayed relative to the NRZ signal.

The allowed time positions of the carrier pulses are indicated by the dashed rectangles. The carrier pulse may occur 8,9 or 10 clock pulses after the previous one. Thus, the carrier pulse may occur in any one of three adjacent clock cycles. Carrier pulse a is assumed to be 8 clock pulses from the previous pulse, carrier pulse B is assumed to be 9 clock pulses from the previous pulse, and carrier pulse C is assumed to be 10 clock pulses from the previous pulse.

As described above, when the carrier pulse is 8 clock pulses from the previous pulse (a), this represents a trailing edge in the NRZ signal, and may immediately follow only one 9 clock pulse interval (D) representing no change in the NRZ signal, or follow 10 clock pulse intervals (E) representing a leading edge in the NRZ signal. Likewise, when the carrier pulse is 10 clock pulses from the previous pulse (C), this represents a trailing edge in the NRZ signal and may only immediately follow an 8 clock pulse interval (E) representing a leading edge in the NRZ signal, or a 9 clock pulse interval (F) representing no change in the NRZ signal. When the carrier pulse is 9 clock pulses from the previous pulse (B), it represents no change in the NRZ signal and may immediately follow 8 clock pulses (D) representing the trailing edge in the NRZ signal, or 9 clock pulses (E) representing no change in the NRZ signal, or 10 clock pulses (F) representing the leading edge in the NRZ signal. All of which are illustrated in figure 7. It is evident that for 9 encoding clock cycles in one NRZ bit period, a first interval of a bit period consisting of one of three adjacent clock cycles (t1-t4) can potentially contain one carrier pulse, while a second interval consisting of the other 6 clock cycles (t4-t10) cannot contain a carrier pulse.

In the intervals in which no carrier pulse is generated in the CARR signal (t4-t10), other auxiliary data may be modulated on the carrier signal. As shown by the vertically shaded rounded rectangles (AUX data) in fig. 7. Two guard periods at are maintained around this interval, the first after the last potential carrier pulse (C) in the bit period and the second before the next subsequent potential carrier pulse (D) in the next bit period, to minimize potential interference between the carrier pulses (a) to (F) carrying the digital audio signal and the carrier modulation (AUX data) carrying the auxiliary data.

Fig. 8 is a block diagram of an embodiment of a modulation system that may be implemented to include auxiliary data in a modulated encoded data stream. In fig. 8, the same elements as those shown in fig. 1 are labeled with the same reference numerals and will not be described in detail below. In fig. 8, an auxiliary data (AUX) source (not shown) is connected to an input of a first-in-first-out (FIFO) buffer 402. An output of the FIFO buffer 402 is connected to a first data input of a multiplexer 404. The output of multiplexer 404 is connected to the input of mixer 30. An output of level detector 25 is connected to a second data input of multiplexer 404. The timing output of the encoder 10 is connected to a control input of the multiplexer 404.

In the illustrated embodiment, it is assumed that the auxiliary data signal directly modulates the carrier signal. Those skilled in the art will understand how to encode and/or prepare a signal to modulate a carrier wave in a manner that best suits the characteristics of the signal. Additionally, in the illustrated embodiment, the auxiliary data signal is assumed to be in digital form. This is not necessary, however. The auxiliary data signal may also be an analog signal.

In operation, encoder 10 includes internal timing circuitry (not shown) that controls the relative timing of the pulses. The timing circuit may be modified in a manner understood by those skilled in the art to generate a signal having a first state for three adjacent code clock cycles t1 through t4 and a second state for the remaining code clock cycles t4 through t10 when a potential pulse may occur in the CARR signal. This signal may be used to control the multiplexer 404 to connect the output of the level detector 25 to the input of the mixer 30 during periods t1 to t4 when a pulse may occur, otherwise to connect the output of the FIFO buffer 402 to the mixer 30 during periods t4 to t 10. During periods t1 through t4, when the output of level detector 25 is connected to mixer 30, the circuit of FIG. 8 is configured as shown in FIG. 1 and operates as described in detail above.

During the period (t4+ Δ t to t10- Δ t), when the FIFO buffer 402 is connected to the mixer 30 (taking into account the guard band Δ t), the data from the FIFO buffer 402 modulates the carrier signal from the oscillator 40. The FIFO buffer 402 operates to receive a digital auxiliary data signal at a constant bit rate and buffer the signal during time periods t1 through t4 when carrier pulses (a) - (C) may be generated. When auxiliary data is to be transmitted, the FIFO buffer 402 provides the stored auxiliary data to the mixer 30 as bursts of higher bit rate during a time period (t4+ Δ t to t10- Δ t). The network throughput of the burst of assistance data through the CARR signal must match the constant network throughput of assistance data from an assistance data signal source (not shown). The skilled person will understand how to match the throughput in a known manner and also how to prepare for overloads and underruns.

Fig. 9 is a block diagram of a receiver that may receive signals generated by the system shown in fig. 8. In fig. 9, the same elements as those shown in fig. 3 are denoted by the same reference numerals and will not be described in detail below. In fig. 9, the output of the detector 140 is connected to a first input of a controllable switch 406. A first output of the controllable switch 406 is connected to an input of the decoder 150 and a second output of the controllable switch 406 is connected to an input of the FIFO 408. The output of the FIFO 408 generates auxiliary data (AUX). The output of the window timer 160 is connected to a control input of the controllable switch 406 instead of to the enable input of the detector 140 as shown in fig. 3.

In operation, detector 140 in FIG. 9 is enabled at all times. The window signal from the window timer 160 corresponds to the timing signal generated by the encoder 10 of fig. 8. The window signal has a first state during a period (t1-t4) in which carrier pulses (A) - (C) may potentially occur, and a second state during the remaining period (t4-t 10). During periods (t1-t4) where carrier pulses (A) - (C) may potentially occur, the window timer 160 controls the controllable switch 406 to connect the detector 140 to the decoder 150. This configuration is the same as that shown in fig. 3 and operates as described in detail above.

During the remaining period (t4-t10), the detector 140 is connected to the FIFO 408. During this period, the modulated auxiliary data is demodulated and provided to the FIFO 408. The FIFO 408 receives bursts of auxiliary data from the detector 140 in a manner corresponding to the FIFO 402 (of fig. 8) and produces an auxiliary data output signal AUX of constant bit rate. The auxiliary data signal represents auxiliary data encoded as a modulation for a carrier wave. Further processing (not shown) may be required to decode the received auxiliary data signal into the required format.

In accordance with the principles of the present invention, the auxiliary data inserted into the carrier signal is another set of carrier pulses representing a second, independent, high data rate signal. In some implementations, more than one set of carrier pulses representing more than one corresponding high data rate signal may be included as the assistance data. In the illustrated embodiment, two additional high data rate signals are included in the channel for the entire three data signals.

In fig. 10, each horizontal line shows the timing of a carrier pulse representing a high data rate signal. The line labeled DATA1 (DATA1) above shows the timing of the carrier pulses representing the first high DATA rate signal DATA 1. Similar to fig. 7. The second line in fig. 10 shows the timing of the carrier pulses representing the second high DATA rate signal DATA2 (DATA2), and the third line in fig. 10 shows the timing of the carrier pulses representing the third high DATA rate signal DATA3 (DATA 3). As can be seen, the carrier pulse representing the first DATA signal DATA1 is located within one of the clock cycles in the interval from time t1 to t4, the carrier pulse representing the second DATA signal DATA2 is located within one of the clock cycles in the interval from time t4 to t7, and the carrier pulse representing the third DATA signal DATA3 is located within one of the clock cycles in the interval from time t7 to t 10. As shown in the lower part of fig. 10, the carrier pulses from all the DATA signals DATA1, DATA2, and DATA3 are combined into a single carrier signal CARR. The single carrier signal may thus transmit three separate high data rate signals over a single channel.

Those skilled in the art will appreciate that each data signal, represented as a carrier pulse, requires a time interval within a bit period comprising three adjacent encoding clock periods, as described in detail above. In the illustrated embodiment, there are nine encoding clock cycles in each bit period, so up to three data signals can be carried simultaneously. More generally, S encoding clock cycles of 3 rounds within one bit period are required to encode S data signals simultaneously. Those skilled in the art will further appreciate that not every encoding clock cycle within a bit period need be utilized to encode a data signal. For example, in the illustrated embodiment, two data signals may be encoded simultaneously. First intervals of three adjacent encoding clock cycles are assigned to the first signal, and second intervals of three adjacent encoding clock cycles, which do not overlap with those assigned to the first signal, are assigned to the second signal. The remaining three encoding clock cycles remain unused or allocated to the auxiliary data as shown in fig. 7. Those skilled in the art will appreciate that the encoding clocks used to encode the respective data signals need not be the same, have the same period, or time alignment, so long as the time intervals at which the carrier pulses representing the respective signals occur do not overlap.

Fig. 11 is a block diagram of a transmitter that can simultaneously transmit three high data rate signals over a single channel in accordance with the present invention. Fig. 11 corresponds to fig. 8. Elements common to fig. 8 are labeled for corresponding inclusion and are not described in detail below. In FIG. 11, the respective input terminals DATA1, DATA2, and DATA3 are connected to respective high DATA rate signal sources (not shown). The first input terminal DATA1 is connected to the first input terminal of the multiplexer 404' via the encoder 10(1), the differentiator 20(1) and the level detector 25(1) connected in series. The second input terminal DATA2 is connected to the second input terminal of the multiplexer 404 'via the sequentially connected encoder 10(2), differentiator 20(2) and level detector 25(2), and the third input terminal DATA3 is connected to the third input terminal of the multiplexer 404' via the sequentially connected encoder 10(3), differentiator 20(3) and level detector 25 (3). The output of multiplexer 404' is connected to the input of mixer 30.

In operation, encoder 10(1), differentiator 20(1), and LEVEL detector 25(1) generate a three-LEVEL signal, corresponding to signal LEVEL in fig. 2, and as described in detail above, representing first high DATA rate signal DATA 1. Similarly, the encoder 10(2), the differentiator 20(2) and the level detector 25(2) generate three-level signals representing the second high DATA rate signal DATA2, and the encoder 10(3), the differentiator 20(3) and the level detector 25(3) generate three-level signals representing the third high DATA rate signal DATA 3. The timing of the pulses of each three-level signal is controlled by a system timing circuit (not shown) to occur as shown in fig. 10. Those skilled in the art will understand how to design and implement such timing circuits. Multiplexer 404' combines the three-level pulses into a single three-level signal having the timing shown in the bottom signal CARR of FIG. 10. In mixer 30, the combined signal is then used to modulate a carrier signal from oscillator 40. As described above, the resulting carrier signal is filtered in the BPF50 to form the SSB signal.

The timing of the high DATA rate signals DATA1, DATA2, and DATA3 may not be synchronized and/or include timing jitter with respect to each other. To compensate for these conditions, respective FIFO buffers 27(1), (27), (2) and (27), (3), shown in dashed lines in FIG. 11, are connected between respective level detectors (25(1), (25), (2), (25), (3)) and respective inputs of multiplexer 404'. The FIFO buffers 27(1), (27), (2), and 27(3) all operate in a known manner to compensate for differences in DATA rates between the input signals DATA1, DATA2, and DATA3 and the timing of the carrier signal CARR generated by the mixer 30.

Fig. 12 is a block diagram of a receiver capable of receiving the modulated signal generated by the transmitter shown in fig. 11 and reproducing three high DATA rate signals DATA1, DATA2, and DATA3 in accordance with the present invention. Fig. 12 corresponds to fig. 9. In fig. 12, the same elements as those of fig. 9 are denoted by the same reference numerals and will not be described in detail below. In fig. 12, the output of the detector 140 is connected to the input of a controllable switch 406'. A first output of the controllable switch 406' is connected to an input of the first decoder 150 (1). The output of the first decoder 150(1) is connected to the output DATA 1. A second output of the controllable switch 406' is connected to an input of the second decoder 150 (2). An output of the second decoder 150(2) is connected to the output DATA2, and a third output of the controllable switch 406' is connected to an input of the third decoder 150 (3). The output of the third decoder 150(3) is connected to the output DATA 3.

In operation, detector 140 generates a signal corresponding to the composite three-level signal (CARR of FIG. 10) generated by multiplexer 404' of FIG. 11. In the interval from time t1 to t4, the controllable switch 406 ' connects the detector 140 to the first decoder 150(1), in the interval from time t4 to t7, the controllable switch 406 ' connects the detector 140 to the second decoder 150(2), and in the interval from time t7 to t10, the controllable switch 406 ' connects the detector 140 to the third decoder 150 (3). A control circuit (not shown) generates a control signal for controlling the controllable switch 406' to operate as described above. Those skilled in the art will understand how to design and implement such control circuits.

The first decoder 150(1) receives a three-level signal, corresponding to DATA1 in fig. 10, in the interval from time t1 to t 4. The first decoder 150(1) processes the signal in a known manner to reproduce the first NRZ signal DATA 1. Similarly, the second decoder 150(2) reproduces the second NRZ signal DATA2 from the three-level signal DATA2 of fig. 10, and the third decoder 150(3) reproduces the third NRZ signal DATA3 from the three-level signal DATA3 of fig. 10.

Claims (19)

1. A digital data modulation method, comprising the steps of:

providing a plurality of digital data signals having a common data bit period;

encoding each of the plurality of digital data signals using a variable pulse width code having edges that occur in respective non-overlapping intervals within the data bit period;

generating respective pulses representing edges of a corresponding one of the encoded plurality of digital data signals; and

a carrier signal is generated having carrier pulses corresponding to the respective pulses.

2. A digital data modulator, comprising:

a plurality of digital DATA signal sources (DATA1, DATA2, DATA3) having a common DATA bit period;

a plurality of encoders (10(1), 10(2), 10(3)), each encoder encoding a respective one of a plurality of digital data signals using a variable pulse width code having edges that occur in respective non-overlapping intervals within the data bit period;

a plurality of pulse signal generators (20(1), (25) (1), (20) (2), (25) (2), (20) (3), (25) (3)), each pulse signal generator generating a respective pulse indicative of an edge of a respective one of the encoded plurality of digital data signals;

a carrier signal generator (30, 40) for generating a carrier signal having carrier pulses corresponding to said respective pulses.

3. The modulator of claim 2, wherein the variable pulse width code is a variable mask.

4. A modulator according to claim 3 wherein the edge of each digital data signal occurs in one of three adjacent periods within the respective interval.

5. A modulator according to claim 3, wherein:

s digital DATA signals are generated by S DATA signal sources (DATA1, DATA2, DATA3), respectively, S > 1; and

the data bit period is divided into at least 3 · S encoding clock periods, S non-overlapping intervals of three adjacent encoding clock periods being formed from the at least 3 · S encoding clock periods; wherein

An edge of each of the S digital data signals occurs in each of the S non-overlapping intervals.

6. A modulator according to claim 2, further characterized in that a multiplexer (404 ') is connected between the plurality of pulse signal generators (20(1), 20(3), 25(1), 25(3)) and the carrier signal generator (30, 40), and the multiplexer (404') selects one pulse signal generator from the plurality of pulse signal generators, in an interval when pulses are generated from the selected pulse signal generator, and connects the selected pulse signal generator to the carrier signal generator.

7. The modulator of claim 6, further comprising: a plurality of first-in-first-out (FIFO) buffers (27(1), 27(3)) respectively connected between the plurality of pulse signal generators and the multiplexer (404').

8. The modulator of claim 2,

each of the plurality of encoders (10(1), 10(2), 10(3)) produces an encoded digital data signal having a leading edge and a trailing edge;

each of the plurality of pulse signal generators (20(1), 20(3), 25(1), 25(3)) generates a positive-going pulse in response to a leading edge in the corresponding digital data signal and generates a negative-going pulse in response to a trailing edge in the corresponding digital data signal;

a carrier signal generator (30, 40) generates carrier pulses having a first phase responsive to positive-going pulses and having a second phase responsive to negative-going pulses.

9. The modulator of claim 8, wherein the first phase is completely 180 degrees out of phase with the second phase.

10. The modulator of claim 2, wherein each of the plurality of pulse signal generators comprises:

a differentiator (20(1), 20(3)) coupled to a respective one of the plurality of encoders; and

a level detector (25(1), 25(2), 25(3)) connected to the differentiator.

11. The modulator of claim 2, wherein the carrier signal generator comprises:

a carrier wave oscillator (40); and

a mixer (30) having a first input connected to the pulse signal generator and a second input connected to the carrier oscillator.

12. A modulator according to claim 11, characterized in that it further comprises a band-pass filter (50) connected to the output of the mixer (30).

13. A digital data demodulator, comprising:

a source (IN) of a modulated signal comprising successive bit periods, each bit period having a plurality of non-overlapping intervals respectively associated with respective ones of the successive bit periods, each interval comprising a carrier pulse, wherein the carrier pulses are spaced apart relative to carrier pulses IN other associated intervals, the carrier pulses representing a respective variable pulse width encoded digital data signal;

a detector (140) for demodulating the modulated signal to produce pulses corresponding to the received carrier pulses;

a plurality of decoders (150(1), 150(2), 150(3)), each decoder decoding pulses received in each of a plurality of associated intervals within the bit period in a manner to decode variable pulse width encoded digital data information in the pulses to produce a corresponding digital data signal.

14. A demodulator, as in claim 13, further comprising a controllable switch (406 ') having an input coupled to the detector (140) and a plurality of outputs coupled to respective ones of the plurality of decoders (150(1), 150(3)), the controllable switch (406') coupling the detector (140) to the respective outputs during respective ones of a plurality of associated intervals within the bit period.

15. The demodulator of claim 13 wherein the variable pulse width code is a variable mask.

16. The demodulator of claim 13 wherein the carrier pulse has one of a first phase and a second phase.

17. The demodulator of claim 13 wherein said first phase is substantially 180 degrees out of phase with said second phase.

18. The demodulator of claim 13, wherein between the modulated signal source and the detector there is connected:

a band-pass filter (110);

an integrator (120); and

a limiting amplifier (130).

19. A digital data modulator, comprising:

a first digital DATA signal source (DATA1) having a DATA bit period;

a first encoder (10(1) for encoding the first digital data signal using a variable pulse width code having edges occurring in a first interval within the data bit period;

a first pulse signal generator (20(1), 25(1)) for generating respective pulses representing edges of the encoded first digital data signal;

a second digital DATA signal source (DATA2) having said DATA bit period;

a second encoder (10(2)) for encoding the second digital data signal using a variable pulse width code having edges occurring in a second interval within the data bit period which does not overlap the first interval;

a second pulse signal generator (20(2), 25(2)) for generating respective pulses representing edges of the encoded second digital data signal;

a carrier signal generator (30, 40) for generating a carrier signal having carrier pulses corresponding to respective first pulses in the first intervals and having carrier pulses corresponding to respective second pulses in the second intervals.