HK1059522B - Conditional access information arrangement - Google Patents

Description

Apparatus for conditional access to information

The application is a divisional application of an invention patent application with the application number of 95193702.2-3 and the application date of 3, 15 in 1995.

Technical Field

The present invention relates to an apparatus for processing program group metadata packets from a video signal packet, and in particular to circuitry for detecting user conditional access to packet payloads for entitlement information.

Background

It is known from documents such as us 5,168,356 and us 5,289,276 that it is advantageous to transmit compressed video signals in the form of data packets and to provide error protection/correction measures for the individual data packets. The system of the aforementioned patent transmits and processes a single television program from each transmission channel, albeit with multiple program components. These systems utilize a reverse transport processor to extract the video signal components of the respective programs for further processing to set the video components for rendering.

From a Book on satellites, The Theory and practice of Satellite Television, The Satellite Book, a Complete Guide to Satellite TV and practice, 17 Pittsfield, Cricklade, Wilts England, issued for example by The fast Television in The united kingdom, it is known that The reception of transmitted Television signals can be restricted to specific users using signal scrambling techniques. This limitation may be changed at the broadcaster's will by periodically transmitting different entitlement data. This entitlement data may be processed by a smart card which is placed on the respective receiver to generate a decrypted or descrambled key. The decryption or descrambling keys are only used in those decryption or descrambling devices of the receivers that have the right to reproduce the corresponding program content. In a packet-transmitted video system of the type mentioned above, the entitlement data may be contained in a specific packet that may be identified as containing data that is readily accessible by the smart card circuitry.

A wide range of broadcast systems, such as a north american direct broadcast satellite system, has a large number of users. This number is so large as to prevent the change of the entitlement data of a particular receiver in a short time. Consider, for example, that a broadcaster is required to block an area near a sports arena, assuming that tickets to a sports event cannot be sold, this information is not provided until the event occurs. Of course, the broadcaster may wish to wait until the last possible minute before making a decision to block the local area. The present invention provides a method and apparatus for providing a denial of rights to receive program content in a short time by layering entitlement data.

Disclosure of Invention

The invention relates to a system and a method for transmitting or receiving layered entitled data. One receiver embodiment includes a packet transport processor for selecting packets having a payload including a conditional access payload header and a payload reserved portion for entitlement data. Each payload header includes a group of bytes encoded in a manner that allows or disallows individual receivers from processing the entitled data. A conditional access filter preprogrammed with a user specific conditional access code word checks whether the respective tuples of the conditional access header match the user specific conditional access code word. The processor allows processing of the entitled data only if a match occurs.

A method of transmitting conditional access information including entitlement management and control data according to the present invention comprises the steps of: forming a plurality of N-byte conditional access codes; forming an N-byte code of a particular predetermined logic state; concatenating M different N-byte conditional access codes, where M and N are integers greater than 1; selecting one of said N-byte conditional access codes or one of said particular N-byte codes; forming a payload containing a) said selected one of said N-byte conditional access codes or said particular N-byte code, b) concatenating the selected code with said M different N-byte conditional access codes, and c) concatenating the concatenated code with said entitlement management and control data; and forming a transport packet containing a) a header marking that the transport packet contains the entitlement data, and b) said payload.

Apparatus in accordance with the present invention for processing a data packet signal in a data packet signal receiver, the data packet signal including entitlement data included in signal packets having a header marking such packets as to contain entitlement data and having a payload containing said entitlement data and further including M concatenated N byte conditional access codes, M and N being integers greater than 1, said apparatus comprising: means for applying said data packet signal; a transport processor for identifying signal packets containing the entitled data based on said packet signals and extracting entitled data payloads from the identified packets; an empowerment data processor; and a conditional access filter for checking the entitled data payloads of the conditional access codes within the unique N byte data group, and disabling the entitled data processor from receiving the extracted entitled data payloads when a check for a conditional access code fails.

Drawings

The invention is described in connection with the accompanying drawings, in which:

fig. 1 is a graphical representation of the time allocation of composite television signal data packets.

Fig. 2 is a graphical representation of individual signal packets.

Fig. 3 is a block diagram of a receiver implementing the present invention for selecting and processing composite component signal packets.

Fig. 4 is a block diagram of a conditional access filter or start code detector.

Fig. 5 is a flow chart of the operation of a conditional access filter.

Fig. 6 is a block diagram of another conditional access filter.

FIG. 7 is a block diagram of an exemplary memory management circuit that may be used for cell 17 of FIG. 3.

Figure 8 is a graphical representation showing memory addresses forming service channel data.

Fig. 9 is a flowchart of a memory address control operation.

Detailed Description

Fig. 1 shows a stream of signal packets represented by a series of small blocks representing signal packets comprising groups of a plurality of different television or interactive television programs. It is assumed that these program components take the form of compressed data and that the amount of video data for each image as such is variable. The length of these packets is fixed. Packets having characters such as labels represent elements of a single program. For example, V_i，A_i，D_iRepresents video, audio and data packets and is designated as V₁、A₁、D₁The data packet of (1) represents the video, audio and data components of program No. 1, V₃、A₃₁、A₃₂，D₃Video, first audio, second audio and data elements representing program No. 3, data packet D_iMay compriseFor example, control data to initiate specific operations of the receiver, or they may contain executable code that forms an application for execution by a microprocessor located within or associated with the receiver.

In the upper row of the packet string, the components of a particular program are displayed in groups. However, it is not necessary to group packets from the same program into packets as represented by the entire packet string, nor is there any particular ordering requirement for the order of appearance of the individual components.

Each packet may be arranged to include a prefix and a payload as shown in fig. 2. The prefix of this example includes two 8-bit bytes, which consist of five fields, four of which (P, BB, CF, CS) are 1-bit fields and the other field (SCID) is a 12-bit field. The SCID area is a signal component identification area. The region CF contains a flag to indicate whether the payload of the packet is scrambled and the region CS contains a flag to indicate which of two alternative descrambling keys is used to descramble the scrambled packet. The prefix of each packet is arranged per packet so that the location of each region can be easily identified.

Each payload contains a header containing a consecutive number, CC, modulus 16, and a TOGGLE flag for a program element. The consecutive number is simply the consecutive label of a series of data packets of the same program element. The TOGGLE flag bit is a 1-bit signal that changes its logic level to indicate the presence of a picture layer start code in an MPEG compressed video component.

Fig. 3 illustrates, in block diagram form, a portion of a digital television signal receiver including an inverse transmit receive processor unit. The signal is detected by an antenna 10 and applied to a tuned detector 11 which extracts a particular frequency band from the received signal and provides a baseband compressed signal in binary format. The frequency bands are selected by the user by means of a microprocessor 19 using conventional methods. Conventional broadcast digital signals have been error coded, such as with Reed-Solomon Forward Error Correction (FEC) coding. The baseband signal is then applied to an FEC decoder 12. The FEC decoder 12 is synchronized with the received video signal and provides an error corrected stream of signal packets of the type shown in figure 1. FEC12 may be provided in packets at regular intervals or as required by, for example, memory controller 17. In each case, a packet framing signal or synchronization signal is provided by the FEC circuit that indicates the time at which the respective packet information is communicated by the FEC 12.

The detected frequency band may contain a plurality of time division multiplexed programs in a packet structure. In practice, only packets from a single program may be passed to the next circuit unit, assuming in this example that the user does not know which packet to select. This information is contained in a program guide, which is itself a program consisting of data associated with program signal elements by means of SCIDs, and may comprise, for example, information relating to the identity of the user. For each program, the program guide is a list of SCIDs for the audio, video, and data components of the respective program. The program guide (packet D4 in fig. 1) is designated as a fixed SCID. When power is applied to the receiver, microprocessor 19 executes a program to load the SCIDs associated with the program guide into one of an array of identical programmable SCID registers 13. The SCID field of each detected signal packet prefix portion from FEC12 is loaded into a subsequent SCID register 14 in sequence. The programmable register and the register receiving the SCID are connected to respective inputs of a comparison circuit 15 and compare the received SCID with the program guide SCID. If the SCID of a packet matches the program guide SCID, comparator 15 causes memory controller 17 to send that packet to a predetermined location in memory 18 for use by the microprocessor. If the received SCID does not match the program guide SCID, the corresponding packet is simply discarded.

The microprocessor waits for a programming command from a user via the interface 20. The interface 20 is shown as a computer keyboard, but it could also be a conventional remote control or a switch on the front panel of the receiver. The user may request to view the program provided by channel 4 (in the terminology of an analogue television system), the microprocessor 19 being programmed to scan the individual SCID program guide tables loaded in memory 18 for the channel 4 program components; and loads these SCIDs into corresponding programmable registers in an array register 13, which registers 13 are associated with respective component signal processing paths.

The received data packets containing audio, video and data program components must finally be sent to the corresponding audio 23, video 22 or auxiliary data 21, 24 signal processors, respectively, for a desired program. Data is received at a relatively constant rate, but the signal processor often requires the data to be input in bursts (e.g., depending on the type of decompression). In the exemplary system of fig. 3, each packet is first sent to a predetermined memory location in common memory 18, after which each processor 21-24 requests processing of a group packet from memory 18. The group of memory transfer elements provides a means for buffering or limiting the desired signal data rate.

The audio, video and data packets are loaded into respective predetermined memory locations to enable the signal processor to conveniently access the group metadata in a buffered manner. In order for the payloads of each group of packets to be loaded in an appropriate memory location, each SCID comparator should be associated with that memory location. This association may be implemented in hardware in the memory controller 17 or may be implemented programmatically. If the former, specific ones of the set of programmable registers 13 are always assigned to audio, video and data SCIDs, respectively. In the latter case, audio, video and data SCIDs may be loaded into any of the programmable register sets 13. The appropriate association will be implemented programmatically in the memory controller 17 when the respective SCIDs are loaded into the programmable registers.

In a steady state, after the program SCID is stored in the set of programmable registers 13, the SCID of the received signal packet is compared with the SCIDs in all of the programmable SCID registers. If a match is found with any of the stored audio, video and data SCIDs, the payload of the corresponding packet will be stored in the audio, video or data storage area or block, respectively.

Individual signal packets are passed from FEC12 to memory controller 17 through signal decryptor 16. Only the payload of the signal is scrambled and the header part of the data packet passes the decryptor unchanged. Whether a packet is descrambled or not is determined by a CF flag in the packet's prefix, and how the packet is descrambled (one of two alternative descrambling keys) is determined by a CS flag. If there is no SCID match for each packet, the decryptor simply does not work on any data that passes.

The decryptor is programmed with a decryption key provided by the smartcard device 31. The smart card is responsive to entitlement information contained in a particular data packet in the program guide to generate the appropriate decryption key. The system of the present example employs two levels of entitlement or program access, entitlement control messages ECM and entitlement management messages EMM. Entitlement control and management information for programs is often transmitted in the form of packets that are identified by the particular SCID contained in the packet stream that is formed from the program guide. The ECM information contained in these packets is used by the smart card to generate a decryption key for use by the decryptor. The EMM information contained in these packets is used by the user-specified smart card to determine the program content to which the user has access. The EMM entitlement information within these packets may be geographic location specific, group specific, or user specific. For example, the system includes a modem (not shown) for communicating accounting information from the smart card to a program provider, such as a satellite radio station. The smart card may be programmed according to, for example, the area code and the telephone exchange code of the receiver location. An EMM may include data that, when processed by a smart card, may entitle or deprive a particular program of reception within a particular area code.

The program provider may require the right to give some users very short lead times, such as pay-per-view programs. The identification information of the specific user may not be provided until a short time when the particular program is broadcast. It may not be possible to program EMMs according to the situation of the user during such a short lead time. A further coding layer may be added to the entitlement information on-the-fly by including an enable/disable receipt designation conditional access code for EMM and ECM data in each packet, thereby substantially enabling instant enable or disable receipt of certain programs.

The packet payload containing EMM and ECM entitlement data includes a 128 bit payload header, the 128 bits being arranged into specifically encoded groups of 4 32 bits. Each group is encoded with a conditional access code and each conditional access code may be encoded differently. Each user is assigned a specific conditional access code. A matched filter or E-code decoder 30 is used to detect a user specific bit pattern in the 128 bit header and if a match is found, the decoder communicates with the memory controller 17 and the smart card 31 so that the remainder of the entitled payload is provided to the smart card (via the memory 18). If no match is detected, the payload is not accepted by the particular receiver and the conditional access code may be periodically changed if the matched filter 30 is programmed. These codes may be provided periodically by the smart card, for more detailed information on the operation of the smart card concerning the viewer's rights, and for the reader to go through section 25 of the satellite handbook-the theory and practice of satellite television.

A match filter or E-code decoder is used to perform the second function, namely to detect a particular MPEG video header. These headers are 32-bit start codes (it is the reason that the headers of the entitled payloads are encoded into 32-bit groups). If video data is lost, an MPEG video decoder can only restart decompressing the video data at particular data entry points that are consistent with the MPEG start code. The decoder may be arranged to communicate with the memory controller 17 to inhibit the flow of video data into memory following a video packet loss and to resume writing video payloads into memory only after the next MPEG start code is detected by the decoder 30.

Fig. 4 shows an exemplary apparatus (decoder 30 of fig. 3) for detecting packets containing conditional access information or MPEG start codes. Whether the decoder 30 is set to detect the entitled payload or MPEG start code is determined by the currently received SCID. In fig. 4, it is assumed that the data provided by the decryptor 16 is 8-bit bytes and arranged in packets. That is, the first byte of an entitled payload or the first byte of an MPEG start code is precisely aligned according to a particular byte position, such as the beginning of a packet's payload, so as to detect specific headers or starting codewords whose positions in the bitstream or byte stream are precisely known. The data from the decryptor 16 is supplied to an 8-bit register 250, the register 250 having an 8-bit parallel output connected to respective first input terminals of a comparator 254, the comparator 254 being formed, for example, by a two-input exclusive nor (XNOR) circuit of groups of eight, the respective output terminals of which are connected to an AND gate AND a latch, the latch being a data latch for latching the output of the AND gate for each byte interval.

A 32-bit MPEG start code is stored in four bytes in an 8-bit register array 265. The conditional access code is stored in 8-bit bytes within an array of 16 8-bit registers 251. The loading of the register arrays 251 and 265 is controlled by the microprocessor 19 and/or by the smart card. The register 265 containing the start code is connected to a 4 out 1 multiplexer 266, the register containing the conditional access code is connected to a 16 out 1 multiplexer 257, and the output ports of the multiplexers 257 and 266 are connected to a 2 out 1 multiplexer 249. Each output connection of the multiplexer 249 is connected to a respective corresponding second input port of the comparator 254. (note that the input and output connections of multiplexers 249, 257 and 266 are 8-bit data buses), if the respective value present at each output connection of register 250 is the same as the output value present at each output connection of the corresponding multiplexer 249, a true signal is generated by comparator 254 circuit corresponding to the data byte.

To detect the start code, multiplexer 266 is scanned by counter 258 in synchronism with the first occurring bytes of data from the four payloads of decryptor 16 to sequentially connect the four different registers 256 to the comparators. In addition, to detect the conditional access code, multiplexer 257 is scanned by counter 258, sequentially connecting the different data in register 265 to comparator circuit 254.

The output of the comparator circuit is supplied to an accumulation and test circuit 255. Circuit 255 determines whether any of a predetermined number of byte matches have occurred. If they occur, a write enable signal is generated for the entitled data in the remainder of the particular payload being detected. In the present system, the header of the entitled payload contains 128 bits arranged as 4 32-bit conditional access codes. The conditional access filters 30 of different users are used to find different combinations of 128-bit bytes. For example, a user device may be used to match the first four bytes of the conditional access code. Another user device may be used to match the second four bytes of the conditional access code, and so on. In either of these example cases, circuit 255 will determine whether a match of the appropriate four consecutive bytes occurred.

Placing a user specific conditional access code in 16 registers in an array may simplify the circuit structure somewhat. Since each user has a four byte conditional access code, this code can be loaded four times in a set of 16 registers. On a transmitter, for four groups of four bytes, the station does not need to be concerned with the location with which the transmitted conditional access code is associated. Another arrangement is to employ only a single set of four registers to hold the user specific conditional access code, the 4 set of registers being repetitively scanned through the 128-bit header of the entitled payload.

For each function, transmission 2³²A possible assignmentEach of the weight codes is impractical because it will limit the bandwidth of other services, while it will also take a significant amount of time. This restriction can be somewhat mitigated by arranging the conditional access codes according to some logical grouping method. Where a packet may be defined by three bytes of each four byte conditional access code. In this method, all users in a group are addressed by setting the respective receivers of the group to ignore one byte of the four byte conditional access code. Thus each four byte access code would represent 256 users. The setting of the filter is done by sending all zeros at the first four byte position and arranging for the conditional access filter to detect this condition. If this condition is satisfied, the conditional access filter is reconfigured in circuit to detect a match of only three bytes of each four-byte set.

A third solution is provided to allow conditional access for all users. This is achieved by encoding the header of the entitled payload, e.g., by all zeroes (or all 1's). Thus, the conditional access filter is arranged to further comprise a detector of all zeros (element 261-.

The bits of each transmitted byte of data are connected to each end of an eight-bit OR gate (OR) 263. Whenever a bit is a logic "1," an OR gate (OR)263 produces a logic "1" output. The output of OR-gate 263 is connected to the input of one of two-input OR-gates 262, and the output and the other input of OR-gate 262 are connected to the data input and Q output of D-type latch 261, respectively. The clock input of the D-type latch is provided by timing circuit 259, the timing pulses being synchronized with the transferred input data bytes. If any bit in any data byte is a logic "1" after the latch is reset, latch 261 will display a logic "1" on its Q output until the next reset pulse. The Q output of latch 261 is connected to a not gate which indicates an output level of 0 when the latch indicates an output level of 1. Thus, if the output of the not gate is high after 128 bits (16 bytes) of the header pass through register 250, then these 128 bits are a 0 value. The latch is reset before each new payload is received. In response to detecting a high output level from the not gate after the passage of the header of the entitled payload, circuit 255 will generate a write enable signal for the data.

Fig. 5 is a flow chart of the operation of conditional access filter 30, starting with the detection of the associated SCID. Once the appropriate SCID is detected, the payload is loaded into filter 30{300 }. And compares the first four bytes of the header with the user specific conditional access code 302. If there is a match, a write enable of the entitled data {310} is generated. If not, check if the first four bytes are all 0{306 }. If all 0's are not detected, the second four bytes of the header are compared with the user specific conditional access code {308 }. If it is a match 312, a write enable 310 is generated. If there is no match, the third four bytes are compared with the user specific conditional access code 314. If it is a match 316, a write enable 310 is generated. If not, the fourth four bytes are compared with the user specific conditional access code 317. If there is a match 318, a write enable 310 is generated, and if there is no match, the last 12 bytes of the header are checked for all 0 320, if all 0's are detected in the last 12 bytes, a write enable 310 is generated, and if not all 0's, no write enable is generated and the process waits for the next packet to arrive 300. In another arrangement, the system can be programmed to look for all 0's of all 16 bytes in the header at the 320 step, thus recognizing that other fixed patterns other than all 0's can be used, such as all 1's or alternating 0 and 1's.

In step 306, if the first four bytes are all 0's, the three bytes of the second four bytes of the header are compared with the user specific conditional access code 354. In the arrangement of fig. 4, this may be accomplished by the arrangement unit 255 finding three matches for a unique four-tuple. If three of the four bytes are matched 326, a write enable 322 is generated, if there is no match, three of the third quadlet of the header are compared 330 with the user specific conditional access code, if three of the four bytes are matched 332, a write enable 322 is generated, if there is no match, three of the last four bytes are compared 336 with the user specific conditional access code, if there is a match, a write enable 322 is generated, and if there is no match, all zero conditions 320 are checked.

Note that a higher level of detection similar to steps 324-340 may be employed where only two of the respective four tuples are matched. This can be set by arranging, for example, that the first eight bytes are all 0's or that the first bytes are all 0's. Thus, the group of the respective corresponding conditional access codes becomes relatively large.

Considering the storage of the entitled payload in memory 18, the system writes the payload header to memory when receiving and checking the conditional access code. If a conditional access code is detected, a detected write enable simply allows the memory control to continue writing the payload. Conversely, if the conditional access code is not detected within the first 16 bytes of the payload, the remainder of the payload is not written to memory and the memory address of a conditional access payload is reset to overwrite the 16 bytes of the conditional access header of the payload.

Fig. 6 is another conditional access filter that can simultaneously compare up to 32 bits (4 bytes), which allows detection of the start code stored in 8-bit register 265 without the need to know the starting byte position in advance. (an eight-bit register is used because an 8-bit microprocessor data bus is used). The output ports of the registers are connected to a first set of inputs of multiplexer 298. The user specific conditional access codes are stored in a second register array 299 whose respective output ports are coupled to a second set of inputs of multiplexer 298. A set of outputs of multiplexer 298 is connected to respective first 8-bit input ports of comparators 270 and 273. Whether the output port of register 265 or 299 is connected to a comparator is controlled by the response of the accumulation and test circuit 297 to the microprocessor.

The input bytes from the decryptor 16 are connected to parallel or serial registers 274-277. Each register 274-277 has an output parallel port connected to the second 8-bit input port of the comparator 270-273, respectively. The system is timed such that four consecutive bytes of the current input signal are loaded into registers 274-277. The output of the comparator is connected to an or gate 278 and 281 through which the accumulation and test circuit 297 passes. A second input of the or-gate is connected to a respective control output connection of the integrating and test circuit 297.

As in the device of FIG. 4, the device of FIG. 6 includes an all zeros detector 261 and 263 for detecting all zeros in the first four bytes and all sixteen bytes.

For the detection of a four byte conditional access code, the unique four byte groups in turn are loaded into register 274-277 and tested against the user specific conditional access code in register 299. If all four comparators detect a match, AND gate 283 produces a logic "1" indicating a match. The AND gate produces a logic "0" if none of the comparators detects a match. For the detection of three of the set of conditional access codes of four input bytes, the accumulate and test circuit 297 applies a logic "1" value to one of the control lines connected to the or gate. This forces the output of the OR gate to a logic "1", effectively forcing a match from the associated comparator. With respect to four byte detection, detection of the conditional access code is accomplished for the unique four byte groups in sequence.

For the detection of the start code, the control lines of all or gates keep a logic "0". The input bytes are applied sequentially to registers 274-277 connected in a cascade. The match test with the start code stored in the storage register 265 is performed for each set of four input bytes in sequence.

Fig. 7 shows an exemplary arrangement of the memory controller 17 shown in fig. 3. Each program element is stored in a different contiguous data block of memory 18. Still other data, such as data generated by the microprocessor 19 or smart card (not shown), may also be stored in the memory 18.

The address is applied to the memory 18 through the multiplexer 105, and the input data is applied to the memory 18 through the multiplexer 99. The output data from the memory management circuit is supplied to the signal processor through another multiplexer 104. The output data provided by multiplexer 104 may be obtained from multiplexer 99, either by microprocessor 19, memory 18, or directly. The program data is assumed to have a standard graphics resolution and quality and to occur at a particular data rate. On the other hand, television signals for high definition HDTV, which occur at significantly higher data rates, may also be provided by this receiver. Practically all data provided by the FEC reaches the memory 18 via the multiplexer 99 and the memory I/O circuit 102, except that the high rate HDTV signal may reach the multiplexer 104 directly from the multiplexer 99. Data from the decryptor 16, the smart card circuit, the microprocessor 19 and the medium error code source 100 is provided to the multiplexer 99. The term "media error code" as used herein is meant to refer to a special code word inserted into the data stream to limit the respective signal processor (decompressor) from suspending the process until a predetermined code word, such as a start code, is detected and then resuming the process based on, for example, the start code.

The memory addresses from the program addressing circuits 79-97, from the microprocessor 19, from the smart card device 31 and from the auxiliary packet address counter 78 are provided to the multiplexer 105. The selection of a particular address during any particular time interval is controlled by a direct memory access DMA circuit 98. The SCID control signal from comparator 15 and the "required data" signal from the respective signal processor are applied to DMA98, in response to which contention for memory access is arbitrated. DMA98 cooperates with a service pointer controller 93 to provide the appropriate read or write address for the signal elements of each program.

Each address of a memory block of various signal components is generated by four groups of program components or service pointer registers 83, 87, 88 and 92. The start pointer for each memory block, which is used to store each signal element, is contained in a register 87 for each signal element. The start pointers may be a fixed value or they may be calculated by ordinary memory management methods in the microprocessor 19.

A pointer to the last address of the respective data block is stored in an array 88 of service registers, one for each possible program element. Like the starting address, the final or last addresses may be fixed values, or they may be calculated values provided by the microprocessor 19. The use of calculated values for the start and end pointers is preferable because it provides a more versatile system with less memory.

A memory write pointer or head pointer is generated by adder 80 and head of service register 83. There is a service header register for each potential program element. The value of a write or head pointer is stored in register 83 and provided to address multiplexer 105 in one memory write cycle. The first pointer is also connected to an adder 80, wherein the first pointer is incremented one unit at a time, the incremented pointer being stored in a corresponding register 83 for the next write cycle. The register 83 is picked up by the service pointer controller 93 for the corresponding program element currently being served.

In this example, it is assumed that the start and end pointers are both 16-bit pointers. Register 83 provides a 16-bit write or head pointer. Selecting a 16-bit pointer facilitates the use of a 16-bit or 8-bit data bus for loading the start and end pointers in registers 87 and 88. On the other hand, the memory 18 has an address of 18 bits. The 18-bit write address is formed by concatenating the most significant bit of a two-bit start pointer and a 16-bit start pointer, the bits of the start pointer being at the most significant bit positions of the combined 18-bit write address. The start pointer is provided by respective registers 87 to service pointer controller 93. The service pointer controller parses out the more significant bits of the start pointer from the start pointer stored in register 87 and connects these bits to the 16-bit head pointer data bus. This is shown by the databus 96, the databus 96 being combined with the head pointer databus from the multiplexer 85, shown by the bold arrow in figure 8.

In fig. 8, the upper, middle, and lower rows of boxes represent the bits of a start pointer, an address, and a head or tail pointer, respectively. The larger value box represents the more significant bit. Arrows indicate the bits of the respective addresses derived from the bit positions of the indicated start pointer or head/tail pointer, wherein bold arrows indicate steady state operations.

Similarly, a memory read pointer or tail pointer may be generated by adder 79 and tail of service register 92. There is one end-of-service register for each potential program element. The value of a read or tail pointer is stored in register 92 and provided to addressing multiplexer 105 in a memory read cycle. The tail pointer is also coupled to adder 79, wherein the tail pointer is incremented one unit at a time, the incremented pointer being stored in the appropriate register 92 for use in the next read cycle. The register 92 is selected by the service pointer controller 93 for the corresponding program element currently being served.

Register 92 provides a 16-bit tail pointer. The 18-bit read address is formed by concatenating the two most significant bits of the start pointer, which are at the most significant bit positions of the combined 18-bit write address, and the sixteen bits of the tail pointer. The service pointer controller may parse the more significant bits of the start pointer from the start pointer stored in register 87 and tie these bits to the 16-bit tail pointer data bus. This is shown by data bus 94, which data bus 94 is coupled to the tail pointer data bus from multiplexer 90.

The data is stored at addresses calculated in the memory 18. After storing one byte of data, the head pointer is increased by one unit and compared with the end pointer of this program component, if they are equal, the more significant bit of the head pointer is replaced by the lower 14 bits of the start pointer, and 0 is set to the lower two bit position of the head pointer part of the address. This is indicated in fig. 8 by the dashed arrow between the start pointer and the address. This operation is represented by arrow 97 pointing from the service pointer controller 93 to the head pointer data bus of multiplexer 85. It may be assumed that the lower fourteen bits of the start pointer are used in place of the bits of the head pointer. For this one write cycle, the bits of the head pointer are replaced with the lower start pointer bits, causing the memory to skip the memory block specified by the upper two start pointer bits. Thus, reprogramming the write address at the beginning of each data packet to a unique memory location in the data block is precluded.

If the head pointer was equal to the tail pointer (indicating where in the memory 18 data was read), a signal is sent to the interrupt area of the microprocessor indicating that a head-to-tail hit occurred. Further writing from this program channel to memory 18 is disabled until the microprocessor re-enables this channel. This situation rarely occurs and should not occur in normal operation.

Data is fetched from the memory 18 at the address calculated by the adder 79 and the register 92 at the request of each signal processor. After reading one byte of the stored data, the tail pointer is incremented by one unit and the logical channel tail pointer is compared with the end pointer in the service pointer controller 93. If the tail pointer and the end pointer are equal, the more significant bits of the tail pointer are replaced with the lower fourteen bits of the start pointer, the lower two positions 0 of the tail pointer portion of the address. This situation is represented by arrow 95 from controller 93 and pointing to the tail pointer data bus from multiplexer 90. If now the end pointer is equal to the head pointer, then the respective memory data block is defined as empty and no more bytes will be sent to the associated signal processor until more data for this program channel is received from the FEC. The actual replacement of the lower fourteen bits of the start pointer for the head or tail pointer portion of the respective write or read address can be achieved using appropriate multiplexing or using a three state interconnect.

The read or write control of the memory is done by the service pointer controller and the direct memory access DMA, units 93 and 94. The DMA is programmed to schedule read and write cycles. The scheduling depends on whether the FEC12 provides data to be written to memory, with FEC data write operations being prioritized so as not to lose incoming signal group metadata. In the example device shown in fig. 7, there are four types of devices that may be used to access memory. These are the smart card, FEC12 (more precisely decryptor 16), microprocessor 19 and application devices such as audio and video processors. Memory contention is managed in the following way. The DMA allocates blocks of memory data for respective program groups in response to data requests from the various processing units listed above, providing access to memory in a 95ns time slot in which a byte of data is read from memory 18 or written back to memory 18. There are two main access allocation patterns, defined as "FEC provided data" or "FEC not provided data", respectively. For each of these modes, time slots are allocated and assigned priorities as follows, assuming a maximum FEC data rate of 5 megabytes/second, or 1 byte transmitted every 200ns, then there,

FEC provides data:

1) the FEC data is written to the disc in a manner,

2) reading/writing by an application device/a microprocessor;

3) the FEC data is written to the disc in a manner,

4) microprocessor read/write;

and, no data is provided for FEC:

1) smart card read/write;

2) reading/writing by an application device/a microprocessor;

3) smart card read/write;

4) microprocessor read/write;

because FEC data writing cannot be delayed, the FEC (more precisely the decryptor) must guarantee access to the memory every 200ns interval when the data is supplied. Subsequent time slots are shared by the application device and the microprocessor. When the requesting device does not have data available, the requested slot is provided to the microprocessor for use.

The controller 93 communicates with the SCID detector to determine which write access memory in each of the start, head and end pointer registers to write to, and the controller 93 communicates with the DMA to determine which read access memory operation in each of the start, end and tail pointer registers to read from. DMA98 controls the selection of the corresponding address and data through multiplexers 99, 104 and 105.

FIG. 9 shows an example flow diagram of a DMA98 memory access process. The DMA determines whether a received packet 200 is detected or not based on the detection of SCID. If a SCID is detected indicating that there is data to be written to memory from the decryptor 16, a byte of program data from the decryptor is written to buffer memory 18{ 201 }. The block of memory data to be written is determined by processor 93 based on the current SCID. The next DMA determines whether any of the program component processors, including the smart card and the microprocessor, request data or read/write (R/W) access to the memory 18{202 }. If there is no data request for DMA, processing returns to step {200 }. If there is a R/W request for data, the DMA determines the priority of the request 203. This can be done by the usual interrupt process, or by a random order sequential one byte operation of the program processors requesting the data. For example, assume that an arbitrary order of access priority is video, audio I, audio II, smart card, and microprocessor. It may also be assumed that only video, audio II and the microprocessor are requesting memory access. In the present operation of step 203, one byte of video data will be read from memory. In the operation of the next step 203, a byte of audio II will be read from memory, in the next subsequent step 203, a byte of microprocessor data is written to or read from memory 18, and so on. Note that the addresses accessed by the smart card and microprocessor are provided by the smart card and microprocessor, respectively, but the addresses for the video, audio and program guide are derived from the address pointer device (80-93).

Once the priority of access is established 203, the necessary program processor processes the one byte data write to memory 18 or read 204 from memory 18. The next byte of data from the decryptor 16 is written to memory 205. A check 206 is done to determine if the microprocessor requests access. If the microprocessor requests access, it processes one byte of data. If the microprocessor does not request access, the process jumps to step 202 to determine if any program processors request access. In this way, incoming data is always guaranteed to be accessed every other memory access cycle, with the interleaved memory access cycles distributed throughout the program processor.

If there is no data currently from the decryptor 16, i.e. a SCID is not currently detected, the process 208 + 216 follows, the first smart card is checked 208 to determine if memory access is requested, if so, a byte of memory access 209 is given, otherwise a check 210 is done to determine if any program processor requests memory access. If there is an R/W request for data, the DMA determines the priority of the 211 request. The corresponding processor handles one byte of memory read or write access. If no program processor requests a R/W of data, processing jumps to step 213 where a test is performed to determine if the smart card requests memory access in step 213. If so, it processes a one byte memory access, otherwise the process jumps to step {200 }.

It should be appreciated that in the presently preferred example, the smart card is provided with a 2 to 1 access priority over all other program processors when in the "FEC no data" mode. This priority is programmed into a programmable state machine in the DMA device and is varied under microprocessor control. As already mentioned, the system may provide interactive services, the microprocessor 19 being responsive to interactive data to perform at least partially interoperable. In this way, the microprocessor 19 stores the memory 18 as both an application and a working memory. In this case, the system operator may change the memory access priority to provide a high frequency of memory accesses to the microprocessor 19. Reprogramming of memory access priorities may be made as a subset of the interactive application commands.

When a packet is lost, it is advantageous to insert a media error code into the video component signal stream to set the video signal decompressor to suspend decompression until a particular signal entry point appears in the data stream. It is not practical to predict where and within which video data packet the next entry point may occur. In order to find the next entry point as soon as possible, it is necessary to include a media error code at the beginning of the first video data packet after detecting a packet loss. The circuit of fig. 7 sets a media error code at the beginning of each video packet and then deletes the media error code in each packet if a preceding packet is not lost. Before the arrival of the video payload from the decryptor, the media error code is inserted by writing in the M write cycle memory 18 into the first M memory address locations reserved for the current video packet payload. Simultaneously, multiplexer 99 is controlled by DMA98 to apply the media error code from source 100 to the I/O port of memory 18. M is simply an integer number of memory locations that are to be used to store the media error code. Assuming that the memory stores 8-bit bytes and the media error code is 32 bits, M will be equal to 4.

The addresses for loading the media error codes into memory are provided by respective video component services registers 83 via multiplexers 82 and 85. It will be appreciated that in order to load media error codes onto memory location locations that are otherwise used to load video component data, the first M addresses provided by the pointer register will simply be the next M subsequent addresses. This address is typically generated by a video head pointer. These same addresses are coupled into an M-stage delay unit 84 to be stored in the memory 18 directly after the last byte of the media error code. The first M addresses are provided at the output of delay unit 84.

The time when the media error code is loaded into memory is synchronized with the determination of the missing data packet. Detection of an error or loss of a data packet is accomplished by an error detector 101 which responds to the CC and HD data of the current data packet.

If a packet loss is detected, the video component of the current packet is stored in the memory 18 starting from the next or (M +1) th address location. This may be done by setting multiplexer 85 to continue passing the undelayed first pointer from the corresponding register 83. On the other hand, if no packet loss is detected, the first M bytes of the video component in the current packet are stored in the memory location that last stored the media error code.

Detection of packet errors or losses is accomplished by an error detector 101 responsive to the CC and HD data of the current packet. The detector 101 checks the consecutive number CC in the current packet to determine if it differs by one unit compared to the CC of the previous packet. In addition, the TOGGLE bit of the current packet is checked to determine whether it exhibits the normal state of the corresponding video frame. If the CC value is incorrect, the state of the TOGGLE bit is checked. A first or second mode of error correction is established, respectively, based on whether one or both of the CC and token bits are erroneous. In the second mode, both the wrong CC and TOGGLE bits are initialized, setting the system reset to a packet containing a graphics layer header. In the first mode, only CC errors, the system is set to reset to a packet containing a slice header (a slice is a subset of the compressed data in a frame). In both the first and second modes, the medium error code written to memory is held in the respective payloads to instruct the decompressor to perform the recovery operation.

It has been found effective to integrate the SCID detector, decryptor, addressing circuitry, conditional access filters and smart card interface into a single integrated circuit to form the system. This will reduce the number of external lines that can lead to severe timing constraints.

Claims (2)

1. A method of processing a packet transport stream, comprising the steps of:

receiving a packet transport stream comprising a plurality of transport packets;

determining a packet identifier identifying a transport packet associated with the selected program;

analyzing the data packet transmission stream in response to the data packet identifier to identify and obtain a sequence of data packets to be transmitted;

detecting, in each transmission data packet, the presence of a counter portion providing count information indicative of the sequence ordering of the associated transmission data packet, said counter portion comprising a field having a predetermined number of bits that is sequentially incremented with each successive transmission data packet in the sequence of transmission data packets and wraps around to a zero value after a maximum value associated with the predetermined number of bits;

determining whether a desired transmission packet sequence has been received in response to a sequence of counter portions associated with the received transmission packet sequence;

detecting, in each transmitted data packet, the presence of a one-bit trigger portion providing information indicative of an error in the associated transmitted data packet; and

in response to the one-bit trigger portion, a determination is made as to whether an error exists in the associated transmission packet.

2. An apparatus for processing a packet transport stream, comprising:

a signal input for receiving a packet transport stream comprising a plurality of transport packets;

a register for receiving and storing the selected packet identifier in response to a user command for selecting a specific transport stream;

a comparator for comparing a packet identifier included in a transmission packet received at the signal input terminal with the selected packet identifier and selecting a sequence of transmission packets, wherein each transmission packet in the selected sequence includes a packet identifier corresponding to the selected packet identifier;

a detector for checking, in each selected transmission packet, a counter portion which provides count information indicating a sequence order of the transmission-related packet, the counter portion including a field having a predetermined number of bits which is sequentially incremented with each successive transmission packet in the transmission-packet sequence and wraps around to a zero value after a maximum value associated with the predetermined number of bits, and determining whether a desired transmission-packet sequence has been received in response to the sequence of the counter portion associated with the selected transmission-packet sequence, the error detector further checking, in each selected transmission packet, a one-bit trigger portion which provides information indicating an error in the transmission-related packet and determining whether an error is present in the transmission-related packet in response to the one-bit trigger portion; and

a signal processor for processing the selected sequence of transmission data packets to produce an output signal.