HK1057640A - Planar electron emitter apparatus with improved emission area and method of manufacture - Google Patents

Description

Planar electron emitter device with improved emission area and method for manufacturing the same

Technical Field

Another application for an emissive device is described in commonly assigned co-pending U.S. patent application No. _______ (HP case No.: 10004242-1), entitled "improved electron emitting device for data storage and method of making the same," the contents of which are incorporated herein by reference.

The present invention relates generally to an emitter device for use in ultra-high density storage systems, and more particularly to an improved solid state emitter that optimizes electron emission at a central location, thereby improving focusing accuracy.

Background

Over the years, many storage systems have made dramatic advances, from the first use of magnetic tape to the use of hard disk drives and today' S optical disk drives, as well as improved flash memory, such as S-RAM and D-RAM. One recent development utilizes field emission electron emitters in ultra-high density memory devices. A field emission emitter is generally fabricated in a geometry having a tip that emits an electron beam from an acute point at the end of the tip. A storage medium located near a field emitter is read and written using an electron beam. An array of field emitters may be matched to an array of storage regions within the storage medium, or a smaller array of field emitters may be moved relative to the storage medium for access at storage locations on the storage medium.

An example of an ultra-high density memory device utilizing field emitter technology is disclosed in U.S. patent 5557596. Each field emitter typically generates an electron beam that impinges on a storage area, thereby generating a signal current. Each memory region may be in one of several different states, most commonly a binary state represented by a high or low bit, either a 1 or a 0. The amplitude of the signal current resulting from the beam current impinging on the storage region depends on the state of the storage region. Thus, the information stored in the memory region can be read out by measuring the amplitude of the signal current.

The electron beam can also be used to write information in the storage area. The power of each electron beam may be increased in order to change the state of the storage area onto which the electron beam is projected. By changing the state of the storage area, an information bit can be stored or erased in the storage area depending on the intensity of the electron beam.

The speed and accuracy of information storage, retrieval, and access depends greatly on the efficiency of the field emitter. Furthermore, the manufacturing steps required for producing and manufacturing the field-tip emitter are extremely complex. In addition, because the storage medium is separate from the field emitter used to read and write information from, these components need to be placed in a protective enclosure under high vacuum, typically 10 degrees of vacuum^-7Or lower in order to protect the emitter tip and delicate surfaces of the storage array from the environment. High vacuum levels are expensive and difficult to achieve.

Further, in the planar electron emitter technology, when a uniform semiconductor layer is coated on an emitter electrode, electron emission tends to occur at the edge of the emitter due to the concentration of an electric field due to the geometry of an extraction electrode. This is undesirable because it causes the lines of electric force in this region to bend significantly, which causes the electron beam to become divergent rather than substantially collimated. It is advantageous to have the electron emission occur mainly in the center of the emitter, where the lines of force extracting the electric field are substantially straight.

There is a need in the art for a field emission electron emitter having higher efficiency than the prior art, which can be more consistently manufactured at lower cost than the prior art, is less susceptible to environmental influences, does not require the high vacuum environment required by the prior art, and has greater emission efficiency than the prior art in the central region of a planar electron emitting device.

Disclosure of Invention

In accordance with the present invention, a field emission device for use in an ultra-high density storage system is disclosed. The field emission device is a planar electron emitter, which comprises an emission electrode, an extraction electrode, and a planar emitter electron emission layer electrically connected with the emission electrode and the extraction electrode. The configuration of the planar electron emitter is such that electron emission is biased toward a central region of the emissive layer, which is more preferential than electron emission from outer regions thereof. One example of achieving this bias is achieved by fabricating the planar emitter electron emission layer such that it has an outer perimeter that is thicker in the depth direction than the interior of the planar emitter emission layer, which reduces electron beam emission at the outer perimeter when an electric field is applied between the emitter electrode and the extraction electrode. In the inner region, the electric field draws electrons at a higher rate from the surface of the planar emitter electron emission layer towards the extraction electrode than in the outer peripheral region. The planar emission device further includes a collecting electrode electrically connected to the planar electron emitter. To achieve an improved electron emission rate in the central region, the planar electron-emitting device has a top surface which is substantially concave.

In another embodiment, a planar emitter emissive layer includes a first layer of metal and a second layer of semiconductor deposited on the first layer of metal. The metal layer may be fabricated using a platinum, gold, silver or metal semiconductor composite layer, while the semiconductor second layer comprises a wide bandgap semiconductor and is of very weakly conductive n-type. Further, the planar electron emission device according to claim 1, further comprising a dielectric interposed between the emission electrode and the extraction electrode, and another dielectric interposed between the extraction electrode and the collection electrode.

A method for manufacturing a planar electron emitter for use in an ultra-high density storage device, comprising the steps of: forming an emitter electrode layer, forming an extraction electrode layer, exposing the emitter electrode layer by removing at least a portion of the extraction electrode layer, and depositing a semiconductor material over the emitter electrode in such a manner as to obtain a controlled thickness gradient extending from a central portion of the deposited semiconductor material towards an outer peripheral portion of the deposited semiconductor material. The method further includes, prior to forming the extraction electrode layer, forming a metal layer on the emitter electrode layer, wherein the depositing step places a semiconductor material on the metal layer. It is contemplated that additional processing steps may be included consistent with implementing the planar electron emitting devices described above. Including fabricating the planar electron emitter such that the semiconductor material deposited over the emitter electrode forms a concave top surface and forming the collector electrode with a desired insulating dielectric layer.

In particular, the planar electron emission device is intended for use in a storage apparatus having a storage medium with a storage region in one of a plurality of states representing information stored in the storage region. The field emitter generates an electron beam current, and information stored in the storage area is read and written by using the electron beam current.

Drawings

The features and advantages of the present invention will become apparent to those skilled in the art from the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of a substrate of a planar field emission electron emission device having a polycrystalline layer coated thereon;

FIG. 2 is a cross-sectional view of the planar field emission electron emission device of FIG. 1 with a metal layer deposited on the polycrystalline layer;

fig. 3 is a cross-sectional view of a planar field emission electron-emitting device according to fig. 2, wherein an insulating semiconductor layer is formed over the metal layer, thereby forming a schottky metal-semiconductor barrier;

FIG. 4 is a cross-sectional view of a planar field emission electron-emitting device according to FIG. 3, wherein additional insulating and metal layers are formed according to the present invention;

fig. 5 is a cross-sectional view of a finished planar field emission electron-emitting device according to the present invention, having an opening formed therein for exposing a surface of a semiconductor layer;

fig. 6 is a cross-sectional view of a planar field emission electron emission device having a semiconductor layer with a varying thickness in accordance with the present invention; and

fig. 7 and 8 are sectional views illustrating a method and stages for manufacturing the planar field emission electron emission device shown in fig. 6.

Detailed Description

An improved structure of a planar field emission electron emitter, which is typically used in ultra-high density memory devices, is shown in fig. 1-5. The emitter structure 100 utilizes solid state mechanisms to enhance and improve electron emission for use in structures such as ultra-high density storage devices, such as those disclosed in the previous U.S. patent 5557596, which is incorporated herein by reference; and for use in field emission based display systems such as that disclosed in U.S. patent 5587628, which is incorporated herein by reference. This construction is also based on the constructions described and shown in patent WO 00/70638 and french patent FR 9906254, published on 11/23/2000.

The solid state mechanism utilizes a thin metal layer disposed on the emitter electrode of a planar field emission electron emission device. Next, a thin layer of wide band gap semiconductor material is disposed on the metal layer, forming a schottky metal-semiconductor junction for enhanced electron beam formation and emission. Since the formation of the electron beam takes place at an interface that is protected from the environment, the emitter structure is less sensitive to environmental factors such as contamination. Thus, in prior art emitter structures, molecular desorption and adsorption are commonly found due to the absence of schottky metal-semiconductor junctions, and temporal and spatial instability of the emitted electron beam due to these effects is minimized. Furthermore, the solid state mechanism reduces the field required to emit electrons, thereby reducing the drive voltage requirements that have been a limitation of using planar emitter geometries, and also may eliminate the need for intrinsic low material work function materials as required in the prior art.

The barrier also provides high immunity against impurities migrating under the strong electric field gradients associated with the emitter tip structure. The electric field gradient is reduced in the direction of the emission area, thereby reducing the movement of impurities of the material. In addition, noise in the planar emitter geometry is also minimized due to current averaging over a larger emission area than would otherwise be provided in the tip geometry. This planar emitter geometry is also made possible by the use of schottky metal-semiconductor junctions and the reduction of the electric field required to emit electrons. The protective barrier also reduces the need for a high vacuum during the final manufacturing stage, since the impurities that have plagued the prior art now have only a small effect. This further reduces manufacturing costs and improves the lifetime of devices manufactured using the techniques of the present invention.

Each planar field emission electron emitter structure further comprises an additional electrode for electron extraction from the surface of the field emission electron emitter. The extraction and focusing electrodes generally operate in conjunction with one another to provide a suitable electric field required for first extracting the electron beam and then focusing the electron beam or for otherwise controlling the emitted electron beam. Generally, a planar emitter geometry provides a substantially collimated electron beam, while a tip emitter geometry provides a diverging electron beam.

The improved planar field emission electron emitter structures are fabricated using well-known semiconductor fabrication techniques, such as those implemented by those skilled in the art. Generally, for example, the methods and structures described are implemented on a silicon substrate, but may be readily substituted with other semiconductor materials, such as gallium arsenide or germanium instead of silicon, or the substrate may be a non-conductive substrate such as a glass or sapphire substrate. A method of manufacture will now be described in connection with fig. 1-5, wherein the various stages of the manufacturing process of a planar field emission electron emitter and the resulting structure at the completion of the stages are described.

Fig. 1 shows a cross-sectional view of a planar emitter device 100, starting with a substrate 110 on which emitters are fabricated from various layers of semiconductor material, metallic material, or oxide, according to techniques and procedures well known to those skilled in the art. First, an electrode layer 112 is made of a conductive material on a first substrate 110. The top surface of the substrate may be planarized using commonly employed methods such as chemical-mechanical polishing (CMP). The layer 112 is typically made of metal or doped polysilicon as a first part of an emitter electrode for use in the planar field emission electron emission device 100 according to the present invention. The conductive layer 112 may be optional in some embodiments.

Next, as shown in FIG. 2, a thin layer of metal 114 is deposited on the surface of the electrode layer 112 using conventional metal deposition techniques well known to those skilled in the art. The thin metal layer 114 may be composed of a high conductivity, corrosion resistant metal (platinum, tungsten, molybdenum, titanium, copper, gold, silver, tantalum, etc., and any alloys and multilayers thereof) that may be combined with a semiconductor to form a schottky metal-semiconductor barrier. The thickness of conductive layer 112 ranges from 0.1 to 0.5 microns and the thickness of metal layer 114 ranges from 10 to 100 nanometers (nm), preferably 20 nm. In addition, layers 112 and 114 may be combined to be made of the material comprising layer 114, with a thickness that provides suitable electrical conductivity.

Next, as shown in fig. 3, a second semiconductor layer 116 is deposited on the metal layer 114. Semiconductor layer 116 is typically formed of a wide bandgap semiconductor material, such as titanium oxide (TiO)₂). Other types of wide bandgap semiconductor materials are also suitable, including silicon carbide (SiC), diamond such as carbon, SiO₂，Al₂O₃Tantalum pentoxide, and the like.

The metal-semiconductor boundary provides a solid schottky metal-semiconductor barrier. When an electric field is applied, electrons are injected into an electric field controlled low or negative electron affinity region within the thin semiconductor layer 116. The emitting device 100 utilizes a metal layer as an electron container and includes an ultra-thin semiconductor material layer covering the metal layer. The semiconductor material is fabricated such that it serves to provide a negative electron affinity surface region that is induced when an electric field is applied to the structure. For example, the semiconductor layer 116 may be formed of: oxides, nitrides and oxynitrides of silicon, aluminum, titanium, tantalum, tungsten, hafnium, zirconium, vanadium, niobium, molybdenum, chromium, yttrium, scandium, and combinations thereof, but are not limited thereto. Electrons from metal layer 114 pass through thin semiconductor layer 116 near the surface of the metal layer and are emitted from the top of layer 116.

The thickness of the insulating semiconductor layer 116 is selected such that a negative electron affinity state is achieved upon application of an electric field. The lower boundary of the thickness is determined by the minimum thickness required to create such a region. The upper boundary of the thickness of semiconductor layer 116 is determined by the potential required to cause electrons to migrate within layer 116. The thicker the semiconductor layer 116, the higher the required potential. Thus, the thickness of the semiconductor layer 116 is in the range of 2-8 nm, preferably 5 nm.

After the schottky metal-semiconductor barrier is formed, additional conventional processing steps are performed as shown in fig. 4 in accordance with the present invention. These steps include providing electrodes on the surface of the emitter 100 that are close to the surface of the planar field emission electron emission device. Dielectric layers are also formed to provide isolation and insulation from the emitter surface and between additional electrode layers. Furthermore, after the formation of other structures, a schottky metal-semiconductor barrier is formed.

An insulating dielectric layer 118 is formed on the surface of the emitter 100 using conventional oxide generation and fabrication techniques well known to those skilled in the art. For example, the dielectric layer 118 may be composed of, but is not limited to, oxides, nitrides, and oxynitrides of silicon, aluminum, titanium, tantalum, tungsten, hafnium, zirconium, vanadium, niobium, molybdenum, chromium, yttrium, scandium, and combinations thereof. Dielectric layer 118 may be formed such that the insulating layer is conformal to layer 112. The layer 118 has a thickness in the range of 0.5-5 microns.

Next, a conductive layer 120 is deposited over oxide layer 118 using conventional processing techniques well known to those skilled in the art. The conductive layer 120 may be composed of a metal (aluminum, tungsten, molybdenum, titanium, copper, gold, silver, tantalum, etc., and any alloy thereof or a multilayer film thereof), doped polysilicon, graphite, etc., or a composite film of a metal and a nonmetal such as C. The conductive layer 120 generally serves as an extraction electrode in the emitter structure 100.

Next, after the conductive layer 120 is formed, an isolation and insulation layer of a dielectric material is coated in the layer 122. Layer 122 may be the same as layer 118 and fabricated in the same manner or from a similar substance to provide dielectric insulation between electrode metal layer 120 and subsequent conductive layer 124.

A conductive layer 124 is fabricated on the surface of the dielectric layer 122 using well-known fabrication techniques similar to those used to form the layers 114 and 120. Layer 124 may also be fabricated using the same metal as layers 114 and 120, but may also be fabricated using a different conductive metal as is commonly used by those skilled in the art. Furthermore, the conductive layer 124 acts as a collecting electrode, for example for collecting electrons emitted from the surface of the emitter during operation onto a storage medium in its vicinity.

A final patterning and etching is performed to open holes in the semiconductor layer 116 to expose the emitter surface. These techniques are well known to those skilled in the art and are used to form openings through conductive layers 120 and 124 and to etch the subsequent insulating dielectric layers 118 and 122 in such a way as to provide openings for the passage of electrons when used in their functional structure. The pores typically have a diameter of about 0.1-10 microns.

The thickness of the dielectric layer 122 is typically about half the diameter of the pores, which is in the range of 0.05-5 microns. The metal layer 120 typically has a thickness of about 0.05-0.3 microns. Also, the thickness of the conductive layer 124 typically ranges from 0.05 to 0.3 microns. Further, although it has been explained that the conductive layer 120 functions as an extraction electrode and the conductive layer 124 functions as a collection electrode, their operations may be combined so that electrons are extracted and collected in tandem. In another embodiment, the wide band gap semiconductor layer 116 and possibly the metal layer 114 are not formed until after the extraction electrodes 120 and 124 and associated dielectric layers 118 and 122 are deposited and form the holes. Layers 114 and 116 are now deposited directly on electrode 112 through these holes.

It is also contemplated that instead of manufacturing one emitter structure 100 at a time, an array of such emitting devices 100 is typically manufactured. For example, an array of 100 x 100 transmitters 100 may be fabricated for read and write operations within the ultra-high density storage system described previously. In addition, large arrays of such emissive devices may also be utilized in field emission display screens.

Although the emitter structure 100 has been illustrated with the electrode layer 112, such a layer is chosen such that the semiconductor substrate 110 is correctly and sufficiently doped such that it acts as an emitter electrode, on which the metal layer 114 is deposited. Furthermore, it has been explained with respect to the fabrication technique and the resulting structure shown in fig. 1-5 that the emitter is a planar electron emitter according to the present invention, but may have other geometries utilizing a schottky metal-semiconductor barrier approach. The use of a schottky metal-semiconductor barrier also enables the formation of smaller geometries with respect to the aggregate emitter electrode as well as the extraction electrode. The planar electron emitter shown in fig. 5 has a collecting electrode and an extracting electrode with a diameter of substantially 2 micrometers, which ranges from 1 to 10 micrometers. The collecting electrode provides the ability to collect electrons in a small spot (10-50 nm) on the anode. Without the use of a collecting electrode, the emission angle is about ± 10 ° for a planar electron emitter.

Fig. 6 illustrates an embodiment of the invention in which the semiconductor layer 216 disposed on the metal layer 214 is fabricated such that the outer edge 216a of the semiconductor material is thicker than the inner portion 216b thereof. Specifically, outer rim 216a has a thickness in the range of 10-15 nanometers, while central portion 216b has a thickness of approximately 5 nanometers. The thicker semiconductor material on the outer edge inhibits electron beam emission on the outer periphery, while the thinner semiconductor material in the central region provides enhanced electron emission than the outer periphery. This also greatly improves the emission efficiency of the emitter and the ability to focus the electron beam compared to the prior art.

The thicker outer perimeter of the semiconductor material is manufactured according to the steps shown in fig. 7-8. Fig. 7 is a cross-sectional view of a second embodiment of an electron emitter in accordance with another aspect of the invention during a processing step prior to deposition of the semiconductor layer.

The second embodiment includes many of the same features described with respect to fig. 1-5. At this time, the semiconductor emitter electrode 212 as initially described with reference to fig. 1 is formed, and the metal layer 214 is provided on the electrode layer 212. Next, alternating layers of insulating oxide material and metal are formed on the surface of the metal layer 214. Thereafter, a masking step and a passivation step are performed to form open areas directly above the metal layer 214 under the oxide and electrode layers. Thus, as shown in FIG. 7, there is a bottom substrate layer 210 on which an emitter electrode electron supply layer 212 has been formed, and a metal layer 214 is formed on this layer 212. These steps are consistent with the steps previously described with respect to fig. 1 and 2. Next, oxide layer 218 is formed and a portion thereof is removed to expose underlying metal layer 214. A second metal layer serving as the extraction electrode 220 is then formed. A second insulating layer composed of silicon dioxide or its equivalent is formed on the extraction electrode 220. Next, a final metal layer 224 is formed on the semiconductor insulating layer 222. In a subsequent processing step, each of these layers is opened again, thereby exposing the surface of the metal layer 214. Layers 218 through 224 are alternately deposited in sequence and a hole is formed through the layers in one step into layer 214.

Next, as shown in fig. 7, a separation layer 226 is fabricated on all surfaces except for the opened metal layer 214. The release layer 226 is typically made of aluminum or other suitable release material, and the release layer 226 is first formed by rotating the entire substrate about an axis normal to the surface of the substrate and producing a collimated beam of release material oriented at an angle relative to the axis normal to the surface. The parting layer 226 coats the entire surface except for the surface of the metal layer 214 that is masked by the geometry of the access holes.

Upon positioning the parting layer 226 in place, a plurality of discrete semiconductor material beams 228 are directed onto the substrate, as shown in the cross-sectional view of fig. 8, to create an insulating semiconductor layer, such as a titanium dioxide layer, on the parting layer 226 and on the exposed surface of the metal layer 214 on which the insulating semiconductor layer 216 is formed. The beam is directed at an angle relative to a vertical axis during deposition and the substrate is rotated about the axis. The parting layer 226 enables the remaining titanium dioxide or unwanted semiconductor material to be removed during a removal step well known to those skilled in the art. Because the semiconductor material diffuses within the somewhat divergent beam of coated material, the outer perimeter of the layer 216 created on the outside is thicker than the center portion due to the rotation of the semiconductor substrate and the angle at which the beam is applied.

Thereafter, the entire wafer is submerged in the parting layer solvent for removing the parting layer and excess semiconductor material or titanium dioxide applied thereto. Because the semiconductor layer 216 is physically bonded to the metal layer 214, it is able to withstand the split-layer solvent, resulting in the structure shown in fig. 6. This results in a semiconductor layer 216 having a thicker outer region relative to the central region. The increased thickness of the outer regions inhibits electrons from being emitted from these regions, while the thinner thickness of the semiconductor material makes electron emission easier, thus increasing the efficiency of the central region, which improves the focusing of the electron beam on the storage medium, thus enabling more accurate reading and writing during reading and writing operations of mass storage using the planar field emission electron emission device shown in fig. 5 and 6.

Other embodiments will be apparent to those skilled in the art from consideration of the specification or practice of the invention disclosed herein. It is intended that the examples be considered as exemplary only, with a true scope of the invention being indicated by the following claims.

It is to be understood that the above-described arrangements are only illustrative of the application of the principles of the present invention. Numerous changes and modifications may be made by those skilled in the art without departing from the scope and spirit of the invention, and it is intended that the appended claims cover such changes and modifications. Thus, while the present invention has been described in detail and with reference to the accompanying drawings in what is presently considered to be the preferred embodiments, it will be apparent to one of ordinary skill in the art that numerous changes and modifications, including but not limited to, variations in size, materials, shape, form, function and manner of operation, assembly and use may be made without departing from the scope and spirit of the invention as set forth in the claims.

Claims (10)

1. A planar electron emission device, comprising:

an emitter electrode;

an extraction electrode; and

a field-controlled solid state electron emitter having a schottky metal-semiconductor junction fabricated on the emitter electrode and electrically connected to the extractor electrode such that a potential disposed between the emitter electrode and the extractor electrode causes field emission of electrons from an exposed surface of the schottky metal-semiconductor junction, wherein a semiconductor layer of the schottky metal-semiconductor junction includes an outer perimeter portion that is thicker in depth than an inner portion of the semiconductor layer, thereby reducing electron beam emission at the outer perimeter portion, wherein an electric field applied between the emitter electrode and the extractor electrode draws emitted electrons from the surface of the planar electron emitter toward the extractor electrode at a higher rate at the inner portion than at the outer perimeter portion.

2. The planar electron emission device as claimed in claim 1, further comprising a collecting electrode electrically connected to the planar electron emitter.

3. The planar electron emission device of claim 1, wherein the planar electron emitter has a top surface that is substantially concave.

4. The planar electron emission device of claim 1, wherein the planar electron emitter comprises a first layer of metal and a second layer of semiconductor deposited on the first layer of metal.

5. The planar electron emission device as claimed in claim 1, further comprising a dielectric disposed between the emission electrode and the extraction electrode.

6. The planar electron emission device as claimed in claim 2, further comprising a second dielectric disposed between the extraction electrode and the collecting electrode.

7. The planar electron emission device of claim 4, wherein the second layer of semiconductor comprises a wide bandgap semiconductor.

8. A method for fabricating a planar electron emitter, comprising:

forming an emission electrode layer;

forming an extraction electrode layer;

exposing the emission electrode layer by removing at least a portion of the extraction electrode layer;

semiconductor material is deposited over the emitter electrode in such a manner as to obtain a controlled thickness gradient extending from a central portion of the deposited semiconductor material to an outer peripheral portion of the deposited semiconductor material.

9. A memory device, comprising:

a storage medium having at least one storage area, the storage area being in one of a plurality of states, thereby representing information stored in the storage area;

at least one planar electron-emitting device for generating a beam current for reading and writing information stored in the storage area; the planar electron emission device includes:

an emitter electrode;

an extraction electrode; and

a planar electron emitter electrically connected to the emission electrode and the extraction electrode and having an outer peripheral portion thicker in depth than an inner portion of the planar electron emitter.

10. A planar field emission electron emission device, comprising:

an emitter electrode;

an extraction electrode; and

a planar electron emitter electrically connected to the emitter electrode and the extraction electrode to provide an electric field for drawing electrons emitted from a surface of the planar electron emitter, wherein the configuration of the planar electron emitter is such that electron emission is biased to a central region, which is more preferential than electron emission in an outer region.