HK1056241B - Apparatus and method for dedicated interconnection over a shared external bus - Google Patents

Description

Apparatus and method for dedicated interconnection through shared external bus

Technical Field

Embodiments of the present invention relate to communications over an external computer bus. More particularly, embodiments of the present invention relate to a dedicated interconnect through a shared external computer bus.

Background

Known computers include a serial port that provides a dedicated connection to a peripheral device. For example, to transfer data to a peripheral device, a computer's processor may send data to a universal asynchronous receiver/transmitter ("UART") at a serial port address via an internal input/output (I/O) bus. A computer's UART serializes data, sending one bit of data at a time over a serial communication link (e.g., wire, serial cable) coupled to the UART. The term "coupled" includes direct connection, indirect connection, and the like. The peripheral at the other end of the serial communication link includes a UART that receives data. A UART-based serial port is typically coupled to a single peripheral device.

The computer may include a universal serial bus ("USB") root hub that includes one or more USB host ports. The USB host port may be coupled to a plurality of USB peripheral devices ("USB target devices") via a serial communication link. Each USB target device may be assigned a device address by a USB host (e.g., software and hardware of a USB-enabled computer). The USB host may include a USB driver that knows the device address of each USB target device. Each USB target device may have a corresponding device driver that communicates with the USB driver to perform data transfers to or from the USB target device.

When a device driver wants to transfer data to or from a USB target device, the device driver sends an I/O request packet ("IRP") to the USB driver requesting initiation of the data transfer. However, because USB is shared (i.e., multiple USB target devices can generally use the same bus at the same time), a single USB target device cannot generally perform a whole block of data transfer at a time over USB. Thus, data transmissions are typically divided into segments (e.g., transactions) that are transmitted over successive time periods (e.g., frames). By dividing the data transfer into transactions, the USB host can guarantee that a portion of the USB bandwidth can contribute to other USB target devices. In view of the foregoing, it can be appreciated that there is a significant need for methods and apparatus that can advantageously provide dedicated interconnects through a shared computer bus.

Disclosure of Invention

According to a first aspect of the present invention, there is provided an apparatus for controlling an external bus, the apparatus comprising: an external bus controller including a first register interface for receiving a first set of data and a second register interface for receiving a second set of data; the external bus controller sends the first set of data and the second set of data to an external bus port output; the external bus controller transmitting up to a first amount of data to the external bus port during each of a plurality of time periods; the up to the first amount of data includes at least a second amount of data, each at least second amount of data being received from a second register interface.

According to a second aspect of the present invention there is provided a system for communicating data over an external bus, the system comprising: a processor; a memory coupled to the processor for storing a plurality of instructions for execution by the processor; an external bus port; and an external bus controller coupled to the processor and the external bus port, the external bus controller including a first register interface to receive a first set of data and a second register interface to receive a second set of data; the external bus controller sends a first set of data and a second set of data to the external bus port; the external bus controller transmitting up to a first amount of data to the external bus port during each of a plurality of time periods, each up to the first amount of data being received from a first register interface; and the peripheral bus controller sends at least a second amount of data to the peripheral bus port within each of a plurality of time periods, each at least second amount of data being received from a second register interface.

According to a third aspect of the present invention there is provided a method of transferring data over a dedicated portion of a bandwidth of a shared external bus, the method comprising: receiving a first set of data from a first register interface; receiving a second set of data from a second register interface; up to a first amount of data is transmitted during each of a plurality of time periods, each up to the first amount of data including at least a second amount of data, each at least the second amount of data being received from a second register interface.

According to a fourth aspect of the present invention, there is provided a system for communicating data via an external bus, comprising: an internal bus controller; an external bus port; and an external bus controller coupled to the internal bus controller and the external bus port, the external bus controller including a first register interface to receive a first set of data and a second register interface to receive a second set of data, the external bus controller transmitting up to a first amount of the first set of data to the external bus port during each of a plurality of time periods, the external bus controller transmitting at least a second amount of the second set of data to the external bus port during each of the plurality of time periods.

Drawings

FIG. 1 shows a system according to one embodiment of the invention.

Fig. 2 shows an apparatus according to an embodiment of the invention.

Detailed Description

Methods and apparatus in accordance with embodiments of the present invention may advantageously provide dedicated interconnects through a shared external computer bus. According to one embodiment of the present invention, the shared external bus controller may include a first register interface and a second register interface. The first register interface may receive a first set of data and the second register interface may receive a second set of data. The external bus controller may send the first set of data and the second set of data to the shared external bus port.

FIG. 1 shows a system according to one embodiment of the invention. The computer 110 may include a processor 111 coupled to a memory 112. In one embodiment of the present invention, processor 111 is a Pentium ® III processor (Pentium ® is a registered trademark of Intel corporation) manufactured by Intel corporation of Santa Clara, Calif. The processor 111 may be coupled to an internal bus controller 113. In one embodiment, internal bus controller 113 is a Peripheral Component Interconnect (PCI) internal bus controller. In another embodiment, the internal bus controller 113 includes a plurality of bus controllers (e.g., north and south bridge chips, front and back side bus controllers, memory bus controllers and I/O bus controllers, etc.).

An external bus host 115 may be coupled to the internal bus controller 113. The external bus host 115 may include an external bus host controller 116. In one embodiment of the present invention, the external bus host 115 is a USB host (e.g., USB-enabled software and hardware systems), and the USB host includes a USB host controller. In another embodiment of the present invention, the external bus host 115 is a shared external bus host (e.g., software and hardware systems that support an external shared bus). In one embodiment, sharing an external bus may provide communication (e.g., data communicated in packets, by a time division multiple access protocol, a code division multiple access protocol, a frequency division multiple access protocol, etc.) for multiple devices that may typically use the same bus at the same time. The external bus host controller 116 may be coupled to a root hub 117, and the root hub 117 may include a port 118 and a port 119. In one embodiment, the root hub 117 may be a USB root hub and each port 118, 119 may be a USB host port.

In one embodiment of the present invention, the foreign bus host controller 116 is coupled to one of the foreign bus ports via one of the foreign bus port outputs of the foreign bus host controller 116. In another embodiment of the present invention, the external bus host controller is incorporated into an internal bus controller (e.g., a PCI bus controller that includes a USB host controller, etc.).

The computer 110 may include an external bus host controller driver. In one embodiment, the external bus host controller driver includes instructions to be executed by processor 111. The external bus host controller driver may be stored in a computer readable medium, such as memory 112 (e.g., Dynamic Random Access Memory (DRAM), Rambus ® DRAM (rdram), Static Random Access Memory (SRAM), flash memory, a hard disk, an optical disk, a magneto-optical disk, a compact disk read only memory (CD-ROM), a Digital Versatile Disk (DVD), non-volatile memory, or a combination thereof). In one embodiment, the external bus host controller driver may include multiple drivers (e.g., one external bus driver and one external bus host controller driver, etc.). In another embodiment, the external bus host controller driver may include a USB driver and a USB host controller driver.

According to one embodiment of the invention, the external bus host controller 116 includes a standard register interface and a standard interface logic. The standard register interface and standard interface logic may send data to or receive data from one or more standard device drivers. Examples of standard device drivers include keyboard device drivers, mouse device drivers, printer device drivers, and the like. The keyboard device driver may receive data from and send data to the keyboard 190 through the standard register interface and standard register interface logic. The mouse device driver and the printer device driver can receive and transmit data from and to the mouse 191 and the printer 192 through standard register interface and standard register interface logic, respectively. For example, in one embodiment, the standard register interface and standard register interface logic may schedule transactions to be broadcast over the USB. Transactions may be scheduled through a series of transaction tables, each of which may include one or more transactions targeted for one or more devices coupled to the external bus.

The external bus host controller 116 may include a dedicated register interface and dedicated interface logic. In one embodiment of the invention, computer 110 is a system under test executing system under test ("SUT") debug software, the special purpose register interface may comprise a debug port register interface, and the special purpose interface logic may comprise a debug port interface logic. Examples of systems under test include a computer, a computer motherboard, a computer system board, a processor board, a computer motherboard coupled to one or more input/output devices (e.g., keyboard, video card, monitor, mouse, USB device, network interface card, etc.). The SUT debugging software may include instructions to determine the functionality of system components, instructions to track system operation, instructions to communicate debug data to a debugging console, and the like.

A system under test, such as computer 110, may be coupled to debug console 150 via a shared external bus link 170, debug peripherals 130, and a shared external bus link 171. In one embodiment, debug console 150 comprises a computer that includes a processor 151 and memory 152. Debug console 150 may include a shared peripheral bus port 159. In one embodiment, the shared external bus port 159 is a USB port of a USB host. In another embodiment of the invention, the shared peripheral bus port 159 is at least part of a shared peripheral bus host. The debug console 150 may execute debug console debug software that may communicate with SUT debug software executing on the system under test through the debug peripherals 130.

Debug peripherals 130 may be coupled to computer 110 and debug console 150 via external bus link 170 and external bus link 171, respectively. In one embodiment, each external bus link 170, 171 includes a USB cable. In another embodiment, each external bus link 170, 171 comprises a communication link through which the shared external bus can communicate (e.g., a cable, a communication path, a wireless communication path, etc.). In one embodiment, the debug peripheral 130 may have a shared external bus target port 138, 139. In one embodiment, each shared external bus target port 138, 139 is a separate USB target port coupled via FIFO buffers (first-in-first-out buffers) 136, 137. In another embodiment, two separate USB interfaces are internally coupled as two FIFO buffers. One FIFO buffer may serve as a write buffer for the debug console 150 and as a read buffer for the computer 110, while the other FIFO buffer may serve as a read buffer for the debug console 150 and as a write buffer for the computer 110. In one embodiment, each FIFO may be 8 bytes. In another embodiment, each FIFO may be larger than 8 bytes, but the USB interface to each FIFO may only provide a maximum of 8 bytes of data for each read request.

The debug console side (console side) of the debug peripheral 130 is implemented in one embodiment according to the USB specification. The console side of the peripheral may be accessed using a standard USB driver. The system-under-test side (SUT side) of the debug peripheral may be implemented with certain exceptions according to the USB specification. In one embodiment, the SUT side may generate and respond to the access it addresses from the allowed reset. The default address may be a fixed address. In one embodiment, a typical USB device has an address assigned to it by a USB host, the SUT-side default address is 7Fh, with endpoint 01 h.

According to one embodiment of the invention, computer 110 may be an under-test system executing SUT debugging software. SUT debug software executing on computer 110 may communicate with debug console debug software executing on debug console 150 via debug peripherals 130. Debug communications (e.g., data sent from computer 110 to debug console 150, data sent from debug console 150 to computer 110) may be carried over a dedicated and unobtrusive portion of the shared external bus (e.g., a USB bus), regardless of whether standard communications are broadcast over the shared external bus (e.g., communications to keyboards, mice, printers, etc.).

Fig. 2 shows an apparatus according to an embodiment of the invention. Computer 200 may include a shared external bus host 201. shared external bus host 201 may include a dedicated register interface 230 and dedicated interface logic 235. In one embodiment, dedicated register interface 230 comprises a debug port register interface and dedicated interface logic 235 comprises debug port interface logic. The shared external bus host 201 may include a standard register interface 210 and standard interface logic 215. In one embodiment of the invention, standard register interface 210 and standard interface logic 215 may enable communication between one or more drivers 205 (e.g., device drivers, input/output device drivers, etc.) and standard shared bus peripherals (e.g., USB peripherals, etc.) coupled to a shared peripheral bus port 260 (e.g., a USB host port, etc.).

Standard bus sequencer logic 250 may receive data to be transferred from standard register interface 210 and/or special purpose register interface 230 to shared peripheral bus port 260. In one embodiment, standard register interface 210 comprises a standard USB register interface of a USB host controller. The standard USB register interface may receive data from a standard USB driver and a USB host controller driver. A USB transaction table of transactions may be generated and the transactions may be sent to a standard USB bus sequencer for transmission to the USB host port. In one embodiment of the invention, dedicated register interface 230 and dedicated interface logic 235 may receive data sent by driver 225 (e.g., a software driver, a debug software driver, etc.). Data (e.g., debug data traffic) received from the special purpose register interface 230 may be sent to the standard bus sequencer logic 250 for transmission to the shared external bus port 260.

The shared external bus host 201, including the dedicated register interface 230 and the dedicated interface logic 235, may operate in at least 3 ways in one embodiment. The first mode of operation may accommodate transferring data via the special purpose register interface 230 and the shared peripheral bus when the standard register interface 210 and the standard interface logic 215 are unable to transfer data to the shared peripheral bus port 260. For example, the state of the computer 200 may be such that the standard interface logic 215 sees the shared external bus port 260 as being disabled. When standard register interface 210 and standard interface logic 215 are operable (i.e., configured to transfer data via shared peripheral bus port 260), the second mode of operation may accommodate the transfer of data via dedicated register interface 230 and the shared peripheral bus. In either of the first mode of operation and the second mode of operation, in one embodiment, at least one set of data received from the special purpose register interface may be transferred to the shared peripheral bus port 260 and across a shared peripheral bus. For example, in one embodiment, when the shared external bus is USB, the dedicated port is capable of sending at least 8 bytes of data received via the dedicated register interface during each frame transferred over the USB (e.g., at least 8 bytes per millisecond, etc.). In another embodiment, a shared external bus master may control the operation of the shared external bus such that the bandwidth of the shared external bus comprises at least a minimum amount of bandwidth (e.g., 8 bytes per cycle, 16 bytes per cycle, 256 bytes per cycle, 1 kilobyte per cycle, etc.) for data received via the special purpose register interface. The remainder of the bandwidth of the shared external bus may be used for data received via the standard register interface. In a third mode of operation, dedicated register interface 230 and dedicated interface logic 235 are not enabled and are unable to transceive data via shared peripheral bus port 260 and the shared peripheral bus.

In one embodiment according to a USB system, a debug peripheral coupled to the USB may pause unless it receives appropriate data within a certain period. In a first mode of operation (e.g., when the standard register interface is disabled and the special register interface is enabled), the shared external bus host may periodically generate (e.g., every 2 milliseconds, etc.) a "keep alive" packet to keep the connected debug peripherals from stalling. In one embodiment, the keep-alive packet may be a separate 32-bit SYC field (i.e., a binary representation of KJKJKJKK). In a second mode of operation (e.g. when standard register interfaces and special register interfaces are enabled), normal transmission of SOF (start of frame) packets (i.e. packet identifiers and frame numbers) may keep the connected debug peripherals not halted. In one embodiment, in either of the first mode of operation and the second mode of operation, the external bus master may check for software requested special register interface data transfer transactions at least every 125 microseconds.

According to one embodiment of the invention, the system under test includes a shared external bus host including at least one standard register interface for shared communications over the shared external bus and a special register interface for dedicated communications over the shared external bus. In one embodiment, the shared external bus is USB. In another embodiment, the shared external bus is an IEEE 1394 bus, a local area network, a wireless communication path, a wireless local area network, or the like. The shared external bus host may include a host port that communicates with the debug console. In one embodiment, the debug console may include a target port. In another embodiment, the host port of the system under test communicates with the debug console via a debug peripheral. The debugging peripheral may include a pair of target ports, a first target port in communication with a system host port under test, and a second target port in communication with a host port of a debugging console.

The system under test may result from a reset and include instructions (e.g., software, firmware, hardware instructions, etc.) to locate the device that supports the special purpose register interface and to determine the address of the special purpose register interface. In one embodiment, such instructions are contained in system debug software under test. In another embodiment, such instructions are at least a part of a system BIOS (basic input/output subsystem), operating system, software application, software driver, and the like. In one embodiment, the special purpose register interface is located in a PCI capable entry that includes address information about where the special purpose register interface resides. The instructions may then decide whether a debug peripheral is present. For example, a debug peripheral may be generated by an allowed reset, may have a fixed address and may respond to accesses that address it.

The system under test may communicate with the debug console (with or without the use of debug peripherals) via a dedicated register interface and a shared external bus. The system under test can communicate via the special register interface whether a standard port is running. For example, in one embodiment, the system under test may be generated by a reset, and the instruction to establish communication over the shared external bus via the special register interface may be executed before the instruction to establish communication via the standard port is executed. In such an embodiment, the data communicated over the shared external bus via the special purpose register interface may simply be data traffic carried by the shared external bus. In another embodiment, the system under test may execute the instruction to establish communication over the shared external bus via the standard port before executing the instruction to establish communication via the special purpose register interface. In such an embodiment, data communicated over the shared external bus via the special purpose register interface may be interleaved with data traffic communicated over the shared external bus via the standard port.

In one embodiment according to the present invention, computer 200 may include software to determine whether a shared external bus host (e.g., a USB host, etc.) includes a dedicated register interface for data transfer over the shared external bus host by accessing a PCI capability table (the PCI capability table is defined by the PCI local bus specification (parts 6, 7, capability table, version 2.2, 1999, 12/18/1999)). In one embodiment, the dedicated port may be located by accessing each PCI device and determining whether to set bit 4 in the status register. When bit 4 is cleared, then the current device does not support the PCI capability table and the software can move to the next device (or function). When bit 4 is set, the software may read an offset (e.g., offset 34h) of the device configuration space. This byte field may be used as a pointer to the first entry in the capability table. The software may read the first Dword of the first entry. Byte 0 is the capability ID, and in one embodiment, when it equals a set value (e.g., 0Ah), then a special purpose register interface (e.g., debug register interface) has been located. When the value is not a set value (e.g., 0Ah), the software may decide whether byte 1 is zero. When byte 1 is zero, the device (or function) does not include an additional capability table in the table and the software can access the next device (or function). When byte 1 is non-zero, the software can use byte 1 as a pointer to the next capability in the table.

After software decides that a device supports a special register interface, it can look up the address where the control register and data buffer are located. The software may look up the information in bytes 2 and 3 of the entries of the capability table. Byte 2 may indicate which Base Address Register (BAR) is used to map the special register interface registers to address space when supporting a BAR. In one embodiment, software may determine the type of BAR (e.g., 32-bit, 64-bit, etc.) that may be used to determine the real address of the special-purpose register interface. Byte 3 may indicate how far (e.g., to 4K) the software register is mapped into the address space. In one embodiment of the invention, the shared external bus is a USB bus, and after locating the special register interface register, the link ID is determined and the link specific fields are initialized (if applicable).

According to one embodiment of the invention, instructions adapted to be executed by a processor to perform a method are stored in a computer-readable medium. The computer readable medium may be a device that stores digital information. For example, a computer-readable medium includes a ROM, which is well known in the art for storing software (e.g., microcode). The computer readable medium can be accessed by a processor adapted to execute instructions adapted to be executed. The term "adapted to be executed" is meant to encompass any instruction ready for execution by a processor in its present form (e.g., machine code), or requiring further action (e.g., compiling, decrypting, or providing access code, etc.) to prepare for execution by a processor.

Methods and apparatus according to embodiments of the present invention may advantageously provide dedicated communication coupling to peripherals. According to one embodiment of the present invention, the shared external bus controller includes a standard register interface and a special register interface. The shared external bus controller may transmit data received from the standard register interface and the special purpose register interface over the shared external bus. The shared external bus controller may transmit up to a first amount of data (e.g., 1500 bytes during each of successive USB frames) in each of a plurality of time periods. When the shared external bus controller receives data via the dedicated register interface, at least a second amount of data received from the dedicated register interface may be included within up to the first amount of data transmitted in each of the plurality of time periods (e.g., at least 8 bytes during each of the successive USB frames). In one embodiment of the invention, this communication of data received via the special purpose register interface may allow communication between the system under test and the debug console.

Embodiments of methods and apparatus for providing a dedicated interconnect over a shared computer bus have been described. In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the present invention may be practiced without these details. In other instances, structures and devices are shown in block diagram form. Moreover, those skilled in the art will readily appreciate that while specific orders of the methods are illustrated and described, it is contemplated that such orders may be altered while remaining within the spirit and scope of the invention.

In the foregoing detailed description, apparatus and methods according to embodiments of the invention have been described with reference to specific exemplary embodiments. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims (29)

1. An apparatus for controlling an external bus, the apparatus comprising:

an external bus controller including a first register interface for receiving a first set of data and a second register interface for receiving a second set of data; the external bus controller sends the first set of data and the second set of data to an external bus port output; the external bus controller transmitting up to a first amount of data to the external bus port during each of a plurality of time periods; the up to the first amount of data includes at least a second amount of data, each at least second amount of data being received from a second register interface.

2. The apparatus of claim 1, wherein the up to the first amount of data comprises up to a third amount of data, each up to the third amount of data being received from the first register interface.

3. The apparatus of claim 1, wherein the external bus controller comprises a shared external bus controller.

4. The apparatus of claim 1, wherein:

the first register interface comprises a standard register interface;

the second register interface comprises a special register interface.

5. The apparatus of claim 1, wherein:

the first register interface is in communication with a plurality of external bus device drivers;

the second register interface is in communication with the first driver.

6. The apparatus of claim 1, wherein said external bus controller comprises a universal serial bus host controller.

7. The apparatus of claim 6, wherein:

the first register interface comprises a standard universal serial bus register interface and standard universal serial bus interface logic;

the second register interface includes a dedicated register interface and dedicated interface logic.

8. The apparatus of claim 6, wherein:

the first register interface comprises a standard universal serial bus register interface and standard universal serial bus interface logic;

the second register interface includes a debug port register interface and debug port interface logic.

9. The apparatus of claim 6, wherein the external bus controller further comprises a universal serial bus driver and a universal serial bus host controller driver.

10. The apparatus of claim 9, wherein up to the first amount of data includes at least a second amount of data within each frame, each at least second amount of data being received from the second register interface.

11. The apparatus of claim 10, wherein up to the first amount of data includes up to a third amount of data within each frame, each up to the third amount of data being received from the first register interface.

12. A system for communicating data over an external bus, the system comprising:

a processor;

a memory coupled to the processor for storing a plurality of instructions for execution by the processor;

an external bus port; and

an external bus controller coupled to the processor and the external bus port, the external bus controller including a first register interface to receive a first set of data and a second register interface to receive a second set of data; the external bus controller sends a first set of data and a second set of data to the external bus port;

the external bus controller transmitting up to a first amount of data to the external bus port during each of a plurality of time periods, each up to the first amount of data being received from a first register interface; and is

The peripheral bus controller transmits at least a second amount of data to the peripheral bus port during each of a plurality of time periods, each at least second amount of data being received from a second register interface.

13. The system of claim 12, wherein:

the peripheral bus port comprises a shared peripheral bus port; and is

The external bus controller includes a shared external bus controller.

14. The system of claim 13, further comprising:

a debugging console for executing debugging console debugging software;

the external bus port sends each at least second amount of data to the debug console; and

the processor executes system debug software under test.

15. The system of claim 13, further comprising:

a debugging console for executing debugging console debugging software;

a debug peripheral;

the external bus port sends each at least second amount of data to the debugging peripheral;

the debugging peripheral sends each data with at least a second quantity to the debugging console;

the processor executes system debug software under test.

16. The system of claim 13, wherein

The external bus controller comprises a universal serial bus host controller;

the external bus port comprises a first universal serial bus host port;

the debugging peripheral comprises at least one first universal serial bus target port and a second universal serial bus target port;

the debug console includes a second universal serial bus host port.

17. A method of transferring data over a dedicated portion of a bandwidth of a shared external bus, the method comprising:

receiving a first set of data from a first register interface;

receiving a second set of data from a second register interface;

up to a first amount of data is transmitted during each of a plurality of time periods, each up to the first amount of data including at least a second amount of data, each at least the second amount of data being received from a second register interface.

18. The method of claim 17, wherein each of the up to first amount of data includes up to a third amount of data, each of the up to third amount of data being received from the first register interface.

19. The method of claim 17, wherein:

receiving the first set of data from the first register interface comprises receiving data from a plurality of external bus device drivers; and is

Receiving the second set of data from the second register interface includes receiving data from the first driver.

20. The method of claim 17, wherein sending up to the first amount of data during each of the plurality of time periods comprises sending up to the first amount of data during each of the plurality of time periods to a debug console, the debug console executing the debug console debug software.

21. The method of claim 19, wherein the plurality of external bus device drivers comprises a universal serial bus device driver.

22. The method of claim 17, wherein each of the plurality of time periods comprises each universal serial bus frame of a plurality of universal serial bus frames.

23. A system for communicating data over an external bus, comprising:

an internal bus controller;

an external bus port; and

an external bus controller coupled to the internal bus controller and the external bus port, the external bus controller including a first register interface to receive a first set of data and a second register interface to receive a second set of data, the external bus controller transmitting up to a first amount of the first set of data to the external bus port during each of a plurality of time periods, the external bus controller transmitting at least a second amount of the second set of data to the external bus port during each of the plurality of time periods.

24. The system of claim 23, wherein the peripheral bus port comprises a shared peripheral bus port and the peripheral bus controller comprises a shared peripheral bus controller.

25. The system of claim 23, wherein the internal bus controller comprises a peripheral component interconnect bus controller.

26. The system of claim 23, wherein the internal bus controller comprises a plurality of internal bus controllers.

27. The system of claim 24, further comprising a debug console executing debug console debug software, the external bus port transmitting each of the at least a second amount of the second set of data to the debug console.

28. The system of claim 24, further comprising:

a debugging console for executing debugging software of the debugging console, and

and the external bus port sends each second group of data with at least a second quantity to the debugging peripheral, and the debugging peripheral sends each second group of data with at least a second quantity to the debugging console.

29. The system of claim 24, wherein the peripheral bus controller comprises a universal serial bus host controller and the peripheral bus port comprises a first universal serial bus host port.