HK1052597B

HK1052597B - System and method for the demodulation of turbo-encoded signals via pilot assisted coherent demodulation

Info

Publication number: HK1052597B
Application number: HK03104754.5A
Authority: HK
Inventors: 林福云; 林福雲; N‧T‧辛迪胡沙雅纳; E‧A‧S‧埃斯特韦斯; N‧T‧辛迪胡沙雅納; E‧A‧S‧埃斯特韋斯
Original assignee: 高通股份有限公司
Priority date: 1999-05-13
Filing date: 2000-05-15
Publication date: 2006-11-24
Also published as: WO2000070836A1; CN1413403A; AU4852300A; CN1251461C; KR20020089127A; HK1052597A1; US20020097785A1; JP2003520463A; EP1177662A1; JP2011050064A; US6975669B2; BR0010475A; KR100715917B1; US6377607B1

Abstract

An efficient telecommunications receiver system for accurately decoding a received composite signal having a data signal component and a pilot signal component includes a first circuit for receiving the composite signal and extracting a pilot signal and a data signal from received composite signal. A second circuit calculates a log-likelihood ratio as a function of a channel estimate based on the pilot signal. A third circuit scales the log-likelihood ratio by a predetermined log-likelihood ratio scaling factor and provides an accurate log-likelihood value in response thereto. A fourth circuit decodes the received composite signal based on the accurate log-likelihood value and the data signal. The third circuit includes a carrier signal-to-interference ratio circuit for computing a first signal-to-interference ratio and a second signal-to-interference ratio based partly on the pilot signal.

Description

System and method for demodulation of TURBO encoded signals by pilot assisted coherent demodulation

Background

I. Field of the invention

The present invention relates to communication systems. In general, the present invention relates to systems and methods for computing log-likelihood (log-likelihood) ratios to facilitate receiver-optimized decoding with pilot-assisted coherent demodulation.

Description of the related Art

Cellular telecommunications systems are characterized by a plurality of mobile transceivers, such as mobile telephones, communicating with one or more base stations. Each transceiver includes a transmitter and a receiver.

In a typical transceiver, an analog Radio Frequency (RF) signal is received by an antenna and down-converted by an RF section to an Intermediate Frequency (IF). The signal processing circuit performs noise filtering and adjusts the signal amplitude through an analog Automatic Gain Control (AGC) circuit. The intermediate frequency section then mixes the signal with the baseband and converts the analog signal to a digital signal. The digital signal is then input to a baseband processor for further signal processing to output voice or data.

Similarly, the transmitter receives a digital input from the baseband processor and converts the input to an analog signal. The signal is then filtered and upconverted to an intermediate frequency by an intermediate frequency stage. The gain of the transmitted signal is adjusted and the intermediate frequency signal is up-converted to radio frequency in preparation for radio transmission.

The link between the transmitter and the receiver is a channel. One way to increase the channel information carrying capacity between a base station and an associated mobile station is to enhance the signal-to-interference ratio (SIR). The SIR is typically expressed as a ratio of the energy per received information bit to the interference density of the received signal. To increase system capacity, receivers in mobile stations and base stations must operate efficiently at lower signal-to-interference ratios (SIRs), or the channel SIRs must be increased. To increase SIR, the transmit signal power is typically increased, which increases cost and interference to other mobile stations, and is therefore impractical in many applications. Instead, special coding schemes are often employed to reduce the required SIR.

Encoding of communication signals involves adding redundant information to the signal. Errors introduced by the noisy channel are reduced to a desired level by strategically adding redundancy to the transmitted communication signal in the noisy environment. As Shannon gave in 1948, if the information rate of the communication signal is less than the channel capacity, the desired noise level can be achieved without reducing the information rate. If redundancy is not employed in a noisy environment, error-free performance is difficult or impossible to achieve.

Many encoding and decoding systems are designed to control noise and interference related errors that occur during the transmission of information in a communication system. Coding is an important factor in high reliability modern digital communication systems.

The ability to operate efficiently in noisy and fading environments is particularly important in Code Division Multiple Access (CDMA) wireless communication systems where Raleigh fading signal environments and co-channel interference from other users are prevalent. Doppler shift in the received signal causes Raleigh fading due to the movement of the mobile station. Co-channel interference occurs when the CDMA communication system maintains multiple system users, each added user contributing to an increase in co-channel interference. Co-channel interference is typically greater than other forms of channel noise such as externally applied white noise (AWGN).

In a Raleigh fading signal environment, the power level of the transmitted communication signal fluctuates according to the Raleigh distribution. The power typically fluctuates in the dynamic range of 10dB to 50 dB. The duration of a fade is a function of the mobile station (i.e., cellular telephone) velocity, the frequency channel assigned to the mobile station, and the overall signal environment. As mobile unit speed increases, the duration of the fade decreases, resulting in shorter error bursts. As the mobile unit speed decreases, the duration of the fade increases, resulting in longer error bursts.

To improve the performance of a wireless communication system in noise and Raleigh fading environments, an interleaver is often used after the signal encoder. The interleaver spreads the codewords output by the encoder so that the bits of a given codeword are transmitted at different times apart from each other. As a result, the individual bits of a given code experience independent fading, where the bits affected by the error burst belong to several code words, respectively. The received signal samples at the receiver are deinterleaved prior to decoding. Thus, the effect of the error burst is spread over the message to enable recovery of the data with the original error correction code. Several types of interleavers exist including diagonal, convolutional, inter-block, and block interleavers.

TURBO codes are serial or parallel connections of two or more constituent codes separated by one or more code interleavers. TURBO encoders and decoders are often employed to improve error control and reduce the required SIR. TURBO codes are typically decoded with a fairly efficient interleaving algorithm to achieve a low error rate when the signal-to-noise ratio (SNR) approaches the Shannon limit. As an essential part of TURBO codes, a code interleaver and a deinterleaver must be inserted between constituent code encoders and decoders, respectively. TURBO code performance depends on the code interleaver length and structure. Excellent TURBO code performance can be obtained by using an interleaver with a pseudo-random structure.

TURBO and convolutional decoders use the log-likelihood ratio (LLR) of the received signal to optimize decoder performance. The LLR is a probability metric that the decoder uses to determine whether to transmit a given symbol for a given particular received signal. The LLR requires a correct estimate of the channel coefficient, which is a measure of the complex scaling factor applied to the signal transmitted over the channel. Correct LLR values are particularly important in TURBO decoding applications that typically subject the LLR input to non-linear operation that may amplify incorrect portions of the LLR resulting in unacceptable decoder performance.

Existing methods of computing LLRs do not properly account for uncertainty in the channel coefficient estimates, resulting in sub-optimal detection and decoding. Existing receiver systems using TURBO codes achieve optimal decoding only if the channel coefficients are known correctly. In practice, it is difficult to know the channel coefficients exactly, and only channel estimates are available.

To obtain estimates of the channel, i.e., channel coefficients, which typically undergo a Raleigh fading, a reference signal, i.e., a pilot signal, is often broadcast along with the data signal. A pilot signal is a predetermined sequence (typically a constant signal) that the transmitter broadcasts to the receiver over the channel.

The base stations often broadcast different data signals along with a common pilot signal to be transmitted to users of mobile stations operating in the coverage area of the base station. The pilot signal is used by the mobile station to establish the phase and amplitude of the channel estimate, which are necessary for coherent detection of the associated data signal. The mobile station also transmits a pilot signal along with its traffic data signal. The base station performs coherent demodulation using the mobile station pilot signal in the same manner as described above.

The process of recovering the transmitted signal from the received modulated signal using the synchronous oscillator and the pilot signal is referred to as pilot-assisted coherent demodulation. To achieve effective coherent detection, a pilot-assisted coherent CDMA communication system must generate correct channel estimates from the received pilot signal.

Theoretically, the channel has equal impact on both the pilot signal and the data signal. The receiver provides estimates of the channel coefficients based on the known pilot signal and the received pilot signal and provides channel coefficient estimates in response thereto. The channel coefficient estimate is used to calculate LLR values. But the channel estimate has an error factor. This error factor may be unacceptably large when given by fast and deep fading to give the channel characteristics. The resulting incorrect portions are particularly problematic for communication systems using TURBO codes, where incorrect portions in the LLRs may result in significantly degraded performance.

Channel estimation values are currently used in LLR calculation circuits and corresponding methods. These circuits and methods generally do not take into account the uncertainty of the channel estimate. The channel tends to experience deep and fast Raleigh fading, which may result in erroneous channel estimates and poor decoding performance due to sub-optimal log-likelihood ratios based on the channel estimates.

Accordingly, there is a need in the art for an optimized method of decoding a received signal for a system employing pilot-assisted coherent demodulation. There is a further need for an efficient system that can correctly calculate log-likelihood ratios while taking into account channel estimate uncertainty.

Summary of The Invention

The need in the art is addressed by the efficient telecommunication receiver system of the present invention for decoding a received composite signal having a data signal and a pilot signal component. In an exemplary embodiment, the receiver system of the present invention is adapted for use with a wireless Code Division Multiple Access (CDMA) communication system and includes a first circuit for receiving a composite signal and extracting a pilot signal and a data signal from the received composite signal. A second circuit calculates an initial log-likelihood ratio as a function of the channel estimate from the pilot signal and/or the data signal. A third circuit scales the initial log-likelihood ratio by a predetermined log-likelihood ratio scaling factor and provides a correct log-likelihood value in response thereto. A fourth circuit decodes the received composite signal based on the correct log-likelihood value and the data signal.

In a particular embodiment, the pilot signal and the data signal include pilot samples and data samples, respectively. The third circuit includes a carrier signal-to-interference ratio circuit for calculating the first signal-to-interference ratio and the second signal-to-interference ratio based in part on the data and the pilot signal. The first signal-to-interference ratio is based on the data samples and the second signal-to-interference ratio is based on the pilot samples. The first signal-to-noise ratio and the second signal-to-noise ratio provide inputs to a scaling factor calculation circuit included in the third circuit.

In a more specific embodiment, the first circuit includes a despreader for despreading the received composite signal according to a predetermined spreading function and providing a despread signal in response thereto. The spreading function is a pseudo-noise sequence or a WALSH function. The first circuit further includes a decovering circuit that extracts a pilot signal and a data signal from the despread signal. The third circuit includes a circuit for calculating a primary carrier signal-to-interference ratio based on the pilot signal and the data signal; and includes a data noise variance estimation circuit for calculating a noise variance of the data signal based on the data signal and an energy signal derived from the data signal. The third circuit further includes a divider circuit for calculating a dominant carrier signal-to-interference ratio as a function of the absolute value of the energy signal and the noise variance of the data signal; and a data sampling signal-to-noise ratio circuit and a channel estimation signal-to-noise ratio circuit for calculating the first signal-to-interference ratio and the second signal-to-interference ratio, respectively, based on the dominant signal-to-noise ratio.

The third circuit calculates a log-likelihood ratio scaling factor according to the following formula:

where k is a log-likelihood ratio scaling factor; gamma ray_dIs a first signal-to-interference ratio; and gamma is_δIs the second signal-to-interference ratio.

The second circuit includes a low pass filter that filters the pilot signal and provides a filtered pilot signal as the channel estimate in response thereto. The first multiplier selectively multiplies the data signal by the complex conjugate of the channel estimate and provides a weighted signal in response thereto. The scaling circuit scales a real part of the weighted signal to generate an initial log-likelihood ratio. The third circuit includes an additional multiplier for multiplying the initial log-likelihood ratio by a predetermined scaling factor and providing the correct log-likelihood value in response thereto. The second circuit includes a filter providing a filtered pilot signal having a reduced interference component; and a complex conjugate circuit for calculating a complex conjugate of the filtered pilot signal.

The third circuit includes a circuit for multiplying the complex conjugate with the data signal to generate an approximate log-likelihood ratio. The approximate log-likelihood ratio is further scaled by additional scaling factors, calculated according to the above formula, to generate the correct log-likelihood value.

The path combining circuit optimizes the combined data signal and pilot signal based on the estimated value of the interference component of the combined received signal and provides an optimally combined signal to the third circuit in response thereto. The third circuit includes a scaling circuit that multiplies the optimally combined signal by a predetermined factor to generate a correct log-likelihood value.

On the other hand, the correct log-likelihood value is calculated for each path as described above. The combined log-likelihood value is generated by adding the respective log-likelihood values of all paths to be used by the convolutional decoder or TURBO decoder.

The third circuit includes a carrier signal-to-interference ratio calculation circuit that calculates a primary carrier signal-to-interference ratio. The carrier signal-to-interference ratio calculation circuit includes an interference estimation circuit that estimates an interference component of the received composite signal. The carrier signal-to-interference ratio calculation circuit includes a first portion for calculating the composite signal. The composite signal has a desired signal component and an interference and/or noise component. A signal extraction circuit extracts an estimated value of a desired signal component from among the received signals. The noise estimation circuit provides the correct noise and/or interference values based on the estimated values of the desired signal components and the composite signal.

In exemplary embodiments, the correct receiver system further comprises a circuit for generating and transmitting rate and/or power control messages to an external transceiver in communication with the efficient receiver system.

The novel design of the present invention is facilitated by the use of unique scaling factors applied to the log-likelihood ratio via the third circuit. The unique scaling factor takes into account the inherent error involved in estimating the channel characteristics from the pilot signal. By considering the uncertainty in the pilot signal estimation, the invention provides an optimized log-likelihood value that can greatly improve the performance of a communication system employing TURBO decoding and encoding. In addition, by correctly estimating the noise and interference components of the received signal, the unique carrier signal-to-interference ratio calculation circuit provides a carrier signal-to-interference ratio that is more correct than previously obtained.

Brief description of the drawings

Fig. 1 is a schematic diagram of a Code Division Multiplexing (CDM) transmitter constructed in accordance with the teachings of the present invention.

Fig. 2 is a schematic diagram of a CDM receiver of the present invention.

Fig. 3 is a schematic diagram of a Time Division Multiplexed (TDM) transmitter illustratively constructed in accordance with the invention.

Fig. 4 is a schematic diagram of a TDM receiver of the present invention.

Fig. 5 is a schematic diagram of a circuit for calculating carrier signal-to-interference ratio (C/I) and log-likelihood ratio (LLR) suitable for use with the forward link and receiver of fig. 2 and 3.

FIG. 6 is a more detailed diagram of a preferred embodiment of the C/I calculation circuit of FIG. 5.

Fig. 7 is a circuit diagram of LLR circuitry and accompanying transceiver circuitry suitable for use with the reverse link and receivers of fig. 2 and 3.

Fig. 8 is a more detailed schematic diagram of a preferred embodiment of an interference energy calculation circuit and an optimized path combining circuit for providing pilot samples and data samples to the LLR circuit of fig. 7.

FIG. 9 is a schematic diagram of an alternative embodiment of a C/I calculation circuit suitable for use with the circuit of FIG. 5.

Description of the invention

The present invention is described herein with reference to exemplary embodiments for particular applications, but it should be understood that the invention is not limited thereto. Those skilled in the art, having access to the exemplification provided herein, will recognize that the invention is capable of further modifications, applications, and embodiments within the scope of the appended claims.

Fig. 1 is a schematic diagram of a Code Division Multiplexing (CDM) transmitter 10 constructed in accordance with the teachings of the present invention. Various details of the transmitter, such as timing circuits, filters, and amplifiers have been omitted from the drawings for clarity. Those skilled in the art will readily be able to construct and implement the omitted circuitry.

The transmitter 10 includes a computer 12 including transmitter software executed by a baseband processor (not shown) in the computer 12. The computer 12 is connected to a TURBO encoder 14 and a time division combiner 16. The TURBO encoder is coupled to a channel interleaver 18, and the channel interleaver 18 is coupled to a first input of a first multiplier 20. A first WALSH function generator 22 is connected to a second input of the first multiplier 20. The output of the first multiplier 20 is connected to a first input of a combiner 24.

The output of the time division combiner 16 is connected to a first input of a second multiplier 26, a second input of which is connected to a second WALSH function generator 28. The output of the second multiplier 26 is connected to a second input of the combiner 24. The output of the combiner 24 is connected to a quadrature pseudo noise sequence (PN) spreader 30. The output of the PN spreader is input to a modulator 32, which modulator 32 is connected to an antenna 34.

In operation, data, including, for example, voice data or other file data, is sent from the computer 12 to the TURBO encoder 14. The TURBO encoder 14 encodes the data signal. The TURBO encoder 14 is a standard TURBO encoder and operates according to TURBO encoding principles and methods known in the art.

The encoded data signal output from the TURBO encoder 14 is then interleaved by a channel interleaver 18, ready for WALSH encoding, Pseudo Noise (PN) spreading, and modulation. The channel interleaver 18 may be implemented by an existing interleaver such as a block interleaver.

The computer 12 also provides a predetermined pilot signal, which in this particular embodiment is a constant equivalent to 1, to the time division combiner 16 along with a control signal. The control signals contain rate control or power control information for transmission to respective receivers (as described in more detail below) to facilitate power and/or rate control and to improve efficiency and throughput of the communication system.

The time division combiner 16 mixes the control signal with the pilot signal according to an existing time division combining method. The synthesized signal is input to a second multiplier 26 multiplied by a predetermined WALSH function provided by a second WALSH function generator 28. Likewise, the interleaved data signal output by the channel interleaver 18 is provided to a first multiplier 20 multiplied by another predetermined WALSH function provided by a first WALSH function generator 22.

The generated WALSH codes output by the first multiplier 20 and the second multiplier 26 are combined by the combiner 24, spread by the PN spreader 30, then modulated into radio frequencies by the modulator 32, and prepared for transmission over a channel by the antenna 34.

The generated signal transmitted by the antenna 34 is a composite signal having a data signal, a pilot signal, and a control signal. Once broadcast over the channel, the composite signal will experience multipath fading and channel interference, which must be efficiently detected and compensated for by the receiver system receiving the transmitted signal.

Those skilled in the art will appreciate that the WALSH function may be provided by a pseudo-noise function generator or a combination of the WALSH function generator and the pseudo-noise function generator in place of the first WALSH function generator 22 and the second WALSH function generator 28 without departing from the scope of the present invention. Furthermore, the transmitter 10 may be implemented in a base station and/or a mobile station.

The terms signal-to-interference and signal-to-noise are equivalent terms in this detailed description.

Fig. 2 is a schematic diagram of a CDM receiver 40 of the invention suitable for use with the CDM transmitter of fig. 1. The transmitter 40 includes a receiver antenna 42 connected to a demodulator circuit 44. The demodulator circuit 44 is connected to an automatic gain control circuit 46, and the automatic gain control circuit 46 is connected to an analog-to-digital converter (ADC) 48. The output of the ADC48 is connected to a first receiver multiplier 50. The output of the ADC48, representing the digital samples, is also provided as an input to the C/I estimation and LLR calculation circuit, as described in more detail below.

The other input of the first receiver multiplier is connected to the pseudo-noise sequence generator 52 output. The output of the first receiver multiplier 50 is connected in parallel with the inputs of the second receiver multiplier 54 and the third receiver multiplier 56. The first and second receiver WALSH generator circuits 58, 60 also provide inputs to the second and third receiver multipliers 54, 56, respectively. The outputs of the second receiver multiplier 54 and the third receiver multiplier 56 are connected to the inputs of a first accumulator 62 and a second accumulator 64, respectively. The output of first accumulator 62 is connected to a sample splitter and a despreader which provides an output to a carrier signal-to-interference ratio (C/I) estimation circuit and a Log Likelihood Ratio (LLR) calculation circuit as described in more detail below.

In operation, the antenna 42 of the receiver 40 receives signals transmitted over a channel, such as RF signals transmitted by the transmitter 10 of FIG. 1. The received RF signal is converted to an intermediate frequency signal and then converted to a baseband signal by the demodulator 44. The gain of the baseband signal is adjusted by an automatic gain control circuit 46 and then converted to a digital signal by an analog-to-digital converter (ADC) 48. The baseband signal is then multiplied by a PN sequence generator 52 and a first receiver multiplier 50, which is related to the PN sequence used in the PN spreader. In this particular embodiment, the PN sequence and its reciprocal are the same because, with a binary operation (in GF 2), the reciprocal of 1 is 1 and the reciprocal of 0 is 0.

The first receiver multiplier 50 then outputs a partially despread signal, which is split into two separate paths. The second receiver multiplier 54 on one path multiplies the partially despread sequence by the WALSH function provided by the first receiver WALSH function generator 58. The WALSH function provided is related to the WALSH function provided by the first WALSH function generator 22 of FIG. 1. The resulting samples of the despread signal are input to a first accumulator 62, which accumulates a predetermined number of samples. The accumulated despread data samples are provided to a sample separator 66. The sample separator 66 outputs the pilot signal and the control signal extracted from the despread signal to the C/I estimation circuit and the LLR circuit, as described in more detail below.

Likewise, the despread signal samples output by the third receiver multiplier 56 are accumulated by a second accumulator 64, which second accumulator 64 outputs a data signal comprising the data signal samples to the C/I estimation circuit and the LLR circuit as described in more detail below.

In this particular embodiment, the present invention is suitable for use with Binary Phase Shift Keying (BPSK) or Quadrature Phase Shift Keying (QPSK) modulation and demodulation methods, but those skilled in the art will appreciate that other modulation and demodulation methods may be used without departing from the scope of the present invention.

Fig. 3 is a schematic diagram of a Time Division Multiplexed (TDM) transmitter 70 illustratively constructed in accordance with the invention. TDM transmitter 70 is identical to CDM transmitter 10 of fig. 1, except that time-division combiner 16, multipliers 20 and 26, WALSH function generators 22 and 28, and adder 24 of fig. 1 are replaced with time-division combiner 72.

Fig. 4 is a schematic diagram of a TDM receiver 80 of the present invention. TDM receiver 80 is identical to CDM receiver 40 in fig. 2, except that accumulator 82 and TDM sample separator 84 replace multipliers 54 and 56, WALSH function generator circuits 58 and 60, accumulators 62 and 64, and sample separator 66 in fig. 2. Accumulator 82 receives the digital spread samples from multiplier 50, accumulates the samples, and then provides the accumulated samples to TDM sample splitter 84. A TDM sample separator 84 extracts data samples, pilot samples, and control samples from the accumulated and despread digital signal. The data samples, pilot samples, control samples, and digital samples output by the ADC48 are provided to the C/I estimation and LLR circuits as described in more detail below.

Fig. 5 is a schematic diagram of a circuit 90 for calculating carrier signal-to-interference ratio (C/I) and log-likelihood ratio (LLR) values suitable for use with the forward link and receivers 40 and 80 of fig. 2 and 4, respectively. The circuit 90 includes a carrier signal-to-interference ratio (C/I) calculation circuit 92, a low pass filter 94, and an LLR circuit 96.

The C/I calculation circuit 92 receives as inputs the data samples, the pilot samples, and the control samples. An additional channel estimation input is provided by the output of low pass filter 94. Low pass filter 94 is a pilot signal filter that receives the pilot samples, filters the pilot samples, and provides channel estimates to C/I calculation circuit 92 in response thereto. The C/I calculation circuit 92 outputs the C/I ratio to the LLR circuit 96 in response to the data samples, pilot samples, and control samples received from the receiver in fig. 2 or 4 and in response to the channel estimate received from the low pass filter 94.

The C/I calculation circuit 92 may calculate the C/I ratio based on information extracted from the data samples, information extracted from the pilot samples, or information extracted from a combination of the samples. If the C/I ratio is calculated based on the data samples and the pilot samples, C/I calculation circuit 92 combines the data sample based estimation and the pilot sample based estimation according to the following equation:

wherein, (C/I)_outIs the C/I ratio output from the C/I calculation circuit 92; k is a predetermined constant less than or equal to 1; (C/I)_dIs based on the C/I ratio of the data samples, and (C/I)_pIs based on the C/I ratio of the pilot samples. The system for providing the correct C/I value is described in more detail below.

The output of the C/I calculation circuit 92 can be expressed as:

wherein E is_sIs the average energy per data symbol, and σ_z ²Is the noise variance of the data samples.

The C/I calculation circuit 92, i.e., the C/I estimator, may or may not control sampling. It will be appreciated by those skilled in the art that control sampling may be omitted without departing from the scope of the invention. In this particular embodiment, if the C/I calculation circuit 92 uses control samples, it represents the same set of additional data samples as the data symbols.

Those skilled in the art will appreciate that the data samples, pilot samples, and control samples may be provided to the C/I calculation circuit as a composite signal without departing from the scope of the present invention. Furthermore, control sampling may also be omitted.

The LLR circuit 96 includes a receive (C/I) from the C/I computation circuit 92_outA data sample signal-to-interference ratio (SIR) circuit 98 and a channel estimation SIR circuit 100. The LLR circuit 96 also includes a correct scaling factor calculation circuit 102 that receives inputs from the data sample SIR circuit 98 and the channel estimate SIR circuit 100.

The LLR circuit 96 further includes a multiplier 104 that receives the complex conjugate of the channel estimate from the conjugate circuit 103 coupled to the output of the low-pass filter 94 and receives the data samples as input. Real part extraction circuit 105 computes the real part of the output of multiplier 104, the output of which is an approximate scaled LLR estimate for the data bit corresponding to the data sample. The output of real part extraction circuit 105 is connected to scaling circuit 106, which scales the output of real part extraction circuit 105 by a predetermined constant factor and provides an approximate LLR value as an output in response thereto. The predetermined constant factor is application specific and can be readily determined by one skilled in the art to meet the needs of a given application.

The output of the scaling circuit 106 is connected to an input of the LLR multiplier 110, the other input of which is connected to the output of the correct scaling factor calculation circuit 102. As described in more detail below, the output of the LLR multiplier 110 represents the correct LLR values corresponding to the data samples that were provided to the TURBO decoder to facilitate decoding of the data samples.

The data sample SIR circuit 98 calculates the data sample SIR by multiplying the received C/I ratio by another predetermined scaling factor based on the C/I ratio provided by the C/I calculation circuit 92. The scaling factor is application specific and can be readily determined by one skilled in the art to meet the needs of a given application. The generated data sample SIR is expressed by the following equation:

wherein, γ_dIs the data sample SIR; e_sIs the average received energy per data symbol; and σ_s ²Is the noise variance per data symbol. The generated data sample SIR is provided to the correct scaling factor calculation circuit 102.

The channel estimated SIR circuit 100 calculates the channel estimated SIR based on the C/I ratio received from the C/I calculation circuit 92 by multiplying the received SIR by a predetermined scaling factor, which is application specific and can be readily determined by one skilled in the art. The channel estimation SIR is expressed by the following formula:

wherein is as defined above, gamma_aIs the channel estimate SIR; e_sIs the average received energy per data symbol; and σ_a ²Is the noise variance per data symbol time interval of the channel estimate provided by the low pass filter 94. The channel estimate SIR is also provided to the correct scaling factor calculation circuit 102.

The correct scaling factor calculation circuit 102 calculates correct LLR scaling factors based on the data sample SIRs provided by the data sample SIR circuit 98 and the channel estimate SIRs provided by the channel estimate SIR circuit 100 according to the following equation:

where k is the correct LLR scaling factor and the remaining variables are as defined in equations (3) and (4).

A multiplier 104 multiplies the complex conjugate of the channel estimate output by the low pass filter 94 with the data samples. The result is sent to real part extraction circuit 105, and real part extraction circuit 105 takes the real part of the product, and scaling circuit 106 scales the real part by a predetermined constant factor to generate an approximate LLR estimate. The approximated LLR estimate is input to the LLR multiplier 110.

The output of the scaling circuit 106 represents an LLR ratio suitable for use in decoding a convolutionally encoded signal, but produces sub-optimal results when decoding a TURBO encoded signal.

According to the present invention, the correct scaling factor represented by equation (5) is provided by the correct scaling factor calculation circuit 102, and the LLR ratio value output by the scaling circuit 106 is scaled by the LLR multiplier 110.

The output of the LLR multiplier 110 represents the correct LLR value, as described in more detail below, to facilitate efficient decoding of the TURBO encoded signal by the TURBO decoder.

FIG. 6 is a more detailed diagram of a preferred embodiment of the C/I estimation circuit 120, the C/I estimation circuit 120 corresponding to the C/I calculation circuit 92 of FIG. 5. The C/I estimation circuit 120 is suitable for use in the forward link. In this embodiment, the C/I estimation circuit 120 includes a PN despreader 122 instead of the multiplier 50, PN sequence generator 52, and accumulator 82 of the receiver 80 of fig. 4. The M-array WALSH decover circuit 124 replaces the TDM sample splitter 84 of fig. 4.

From left to right and top to bottom, the C/I estimation circuit 120 includes a PN despreader 122, an M-array WALSH decover circuit 124, and total received signal energy (I)_o) A calculation circuit 126, a first constant circuit 136, a pilot filter 128, a subtractor 132, a first multiplier 134, a pilot energy calculation circuit 138, a look-up table (LUT)140, a second multiplier 142, and a C/I accumulation circuit 144. In C/I estimation circuit 120, PN despreader 122 receives the digital in-phase (I) and quadrature (Q) signals output by ADC48 of fig. 4 or 5. PN despreader 122 provides inputs in parallel to M array WALSH decover circuit 124 and Io calculation circuit 126. The M array WALSH decover circuit 124 provides an input to the pilot filter 128 and to the constant divider circuit 130 in the path weight combining circuit 158.

The output of the energy calculation circuit 126 is connected to the positive terminal of a subtractor circuit 132. The negative terminal of the subtractor circuit 132 is connected to the output terminal of the first multiplier 134. A first input of the first multiplier 134 is connected to an output of a first constant circuit 136. A second input of the first multiplier 134 is connected to an output of a pilot energy calculation circuit 138. The pilot filter 128 provides an input to a pilot energy calculation circuit 138.

The output of subtractor 132 is connected to a look-up table (LUT) 140. The output of the LUT 140 is connected in parallel with a first input of the second multiplier 142 and a first input of the third multiplier 146 in the path weighted combination circuit 158. A second input of the second multiplier 142 is connected to an output of the first multiplier 134. The output of the second multiplier 142 is connected to a C/I accumulator circuit 144, the output of which is provided to the input of the LLR circuit 96.

The path weight combining circuit 158 includes a second constant generating circuit 150, a fourth multiplier 148, a third multiplier 146, a constant divider circuit 130, a complex conjugate circuit 152, a fifth multiplier 154, and a path accumulator circuit 156. In the path weight combining circuit 158, the fourth multiplier 148 is connected at a first end to the output of the pilot filter 128, which is also connected to the pilot energy calculation circuit 138 in the C/I estimation circuit 120. A second terminal of the fourth multiplier 148 is connected to a second constant generating circuit 150. The output of the fourth multiplier 148 is connected to a second input of the third multiplier 146. The output of the third multiplier 146 is provided to the input of a complex conjugate circuit 152. The output of the complex conjugate circuit 152 is connected to a first input of a fifth multiplier 154. The output of the constant divider circuit 130 is connected to a second input of the fifth multiplier 154. The output of the fifth multiplier 154 is connected to an input of a path accumulator circuit 156. An output of the path accumulator circuit 156 is connected to a second input of the LLR circuit 96. The output of the LLR circuit is connected to the decoder input (see 48 in fig. 1).

In operation, PN despreader 122 receives the I and Q signals and despreads the L fingers, i.e., the L independent paths (1). PN despreader 122 despreads the I and Q signals with the inverse of a pseudo-noise sequence used to spread the I and Q signals prior to transmission over the channel. The construction and operation of PN despreader 122 is well known in the art.

The despread signal is output by PN despreader 122 and input to M-array WALSH decover 124 and I_oA calculation circuit 126. I is_oThe calculation circuit 126 calculates the total received energy per chip (I) including both the desired signal component and the interference noise component_o)。I_oThe calculation circuit provides I according to the following formula_oEstimated value of (^ I)_o)：

Where N is the number of chips per pilot burst, 64 in this particular embodiment, and represents the received despread signal output by PN despreader 122.

Those skilled in the art will appreciate that I may be calculated prior to despreading by PN despreader 122 without departing from the scope of the present invention_o. For example, I_oCalculation circuit 126 may receive direct inputs of the I and Q signals received from ADC48 of fig. 2 and 4 instead of the input provided by PN despreader 122, in which case I_oThe output of the computation circuit 126 will provide the pair I_oAn equivalent estimate of (c).

The M-array WALSH decover circuit 124 decovers orthogonal data signals, referred to as data channels, and pilot signals, referred to as pilot channels, according to methods well known in the art. In this particular embodiment, the orthogonal data signal corresponds to a data channel s represented by the following equation:

where M is the number of chips per WALSH symbol, ^ E_s，lIs the modulation symbol energy of the 1 st multipath component, [ lambda ] [ theta ]_lIs the phase of the data channel s, and X_lIs the information exposure (barring) component of the data channel s. The decovered data channel represented by equation (2) is provided to a decoder (as described more fully below) and to a constant divider circuit 130 in a path weight combining circuit 158.

The present invention is suitable for use with signals that include various WALSH codes, but those skilled in the art will readily adapt the present invention for use with other types of codes.

The pilot channel is input to a pilot filter 128. The pilot filter 128 is an averaging filter that acts as a low pass filter that removes higher frequency noise interference components from the pilot channel. The output p of the pilot filter 128 is represented by the following equation:

where M is the number of chips per WALSH symbol, ^ E_p，lIs the pilot chip energy of the 1 st multipath component, and θ_lIs the phase of the filtered pilot channel p.

An energy estimate of the filtered pilot channel p, which is the square of the complex magnitude of the filtered pilot channel p as represented by equation (8), is calculated by the pilot energy calculation circuit 138. Multiplying the square of the complex magnitude of the filtered pilot channel p by a predetermined scaling factor c, expressed by the following equation:

wherein, I_orIs that the received energy of the desired signal, i.e. the equivalent of the noise interference component, is small_o。E_pIs the pilot chip energy. The scaling factor c is a forward link constant known in many wireless communication systems.

The scaling factor c is multiplied by the energy of the filtered pilot channel p by a first multiplier 134 to generate the received desired signal (I with little noise interference component_o) Accurate estimation of energy ^ I_or，lThe received desired signal is associated with the 1 st multipath component of the received signal I and Q signals.

From I by subtractor 132_oSubtracting the correct estimate from the estimate ^ I_or，lGenerating an interference energy (N) associated with the 1 st multipath component_t，l) Is measured correctly. Then N is added_t，lIs provided to LUT 140, and N is provided_{t, l into}Is output to the third multiplier 146 of the path weighted combination circuit 158 and the fourth multiplier 142An input. The second input of the second multiplier 142 is coupled to the output of the first multiplier 134 and the ^ I is provided from the second input of the second multiplier 142_or，l. The second multiplier 142 outputs a carrier signal-to-interference ratio (C/I) associated with the 1 st multipath component according to the following formula_lCorrect estimation of (2):

the correct C/I value is then accumulated on the L path in the received signal by C/I accumulator circuit 144. The accumulated C/I values are then provided to LLR circuit 96 and the constituent rate/power request generation circuits (not shown) as is well known in the art.

In the path weight combining circuit 158, the fourth multiplier 148 multiplies the filtered pilot channel p by the constant k provided by the second constant generating circuit 150. The constant k is calculated according to the following formula:

wherein E is_sIs the modulation symbol energy, E_pIs the pilot symbol energy and M is the number of WALSH symbols per chip as described above. For both the reverse link and forward link transmissions, E_sTo E_pThe ratio of (a) is often known or determinable.

The output of the fourth multiplier 148 provides an estimate of the channel coefficient a as expressed by:

wherein, E_s，lIs the modulation symbol energy estimate of the 1 st multipath component, [ lambda ] theta ^ theta_lIs the phase estimate of the pilot signal.

The channel estimate is then multiplied by the interference energy N associated with the 1 st multipath component by a third multiplier 146_t，lThe reciprocal of (c). Interference energy N_t，lIncluding both interference and noise components. The complex conjugate circuit 152 then calculates the conjugate value output by the third multiplier 146, which represents the maximum ratio path combining weight. The maximum ratio path combining weight is then multiplied by the corresponding data symbol output by the divider circuit 130 by a fifth multiplier 154. The data symbol d is represented by the following formula:

wherein the variables are given as in equations (2) and (7).

The output of the fifth multiplier 154 represents the optimally weighted data signals, which are then accumulated by the path accumulator circuit 156 over the L paths that include the signals. The resulting optimally combined data signal is provided to an LLR circuit 96 that facilitates optimal soft decoder computation to a decoder (as described in more detail below and illustrated in fig. 5).

Note that only one path is shown in fig. 5, so there is no combiner. Otherwise, the data samples, pilot samples, and control samples should be interpreted as multiple parallel data streams, each from a different antenna.

Those skilled in the art will appreciate that the constants c and k provided by the first constant generating circuit 136 and the second constant generating circuit 150, respectively, may be different constants or variables than those represented by equations (3) and (6) without departing from the scope of the present invention.

Fig. 7 is a schematic diagram of LLR circuitry 170 and accompanying transceiver circuitry 172 suitable for use with the reverse link and receivers 40 and 80 of fig. 2 and 4, respectively. The LLR circuit 170 includes a conjugate complex circuit 174 whose output is connected to the input of a first multiplier 176. The output of first multiplier 176 is connected to the input of real part extraction circuit 105, and real part extraction circuit 105 provides an output to a first input of second multiplier 178. A second input of the second multiplier 178 is connected to an output of a constant factor circuit 188. The output of the second multiplier 178, which represents the coarse scaled LLR values, is connected to an input of an LLR generator 179. The output of the LLR generator 179 is connected to an input of a TURBO decoder 180, and the TURBO decoder 180 provides decoded data bits to a data or speech processing unit 182 connected to a receiver, such as the receiver 40 in fig. 2 or the receiver 80 in fig. 3. The data or voice processing unit 182 provides output to the speaker of the w wireless telephone (not shown) or to other devices or computer applications (not shown).

The pilot samples and the data samples are provided by the receiver in fig. 2 or fig. 4 to LLR generator 179. The pilot samples are also provided as inputs to a low pass filter 186, the output of which is connected to the input of the conjugate complex circuit 174.

In operation, pilot samples that have been filtered by the low pass filter 186 are input to the complex conjugate circuit 174 in the LLR circuit 170. Conjugate complex circuit 174 calculates conjugate values of the filtered pilot signal and outputs them to first multiplier 176. The first multiplier 176 multiplies the conjugate filtered pilot samples with the receiver (see fig. 2 and 4) data samples. The multiplied signals are then scaled by a predetermined constant factor by a second multiplier 178 and constant factor circuit 188. The predetermined constant factor is application specific. Those skilled in the art can readily calculate the appropriate factor and configure the corresponding circuit providing that factor to meet the needs of a given application.

The generated scaled signal output from the second multiplier 178 is provided to an LLR generator 179, the LLR generator 179 performing substantially the same functions as blocks 92, 98, 100 and 102 in fig. 5.

The output of the LLR generator 179 represents a correct LLR value that is input to the TURBO decoder 180 as an LLR value suitable for use with TURBO codes and applications characterized by relatively low channel signal-to-interference ratios and large multipath spreading factors, such as reverse link applications.

The construction of the TURBO decoder 180 is well known in the art, and the TURBO decoder 180 decodes the received data samples with the correct LLR values. The generated data samples are sent to a signal processing circuit, such as a data or voice processing unit 182, or to a computer connected to a receiver terminal running data processing software.

In this embodiment, controller 182 and transmitter 184 correspond to computer 12 and high efficiency transmitter 10 of FIG. 1, or computer 12 and transmitter 70 of FIG. 3, respectively.

Fig. 8 is a more detailed schematic diagram of a preferred implementation of the interference energy calculation circuit 190 and the optimized path combining circuit 158 for providing pilot samples and data samples to the LLR circuit of fig. 7. The correct interference energy calculation circuit 190 is optimized for reverse link transmission and includes the path weight combining circuit 158 and the LLR circuit 96 of fig. 6.

The operation of the interference energy calculating circuit 190 is the same as that of the C/I estimating circuit 120 of fig. 6, except for the calculation of Nt. The interference energy calculation circuit 190 includes a PN despreader 122, an M-array WALSH decover circuit 124, and a pilot filter 128. The M-array WALSH decover circuit 124 decovers, i.e., extracts, the pilot channel and the data channel from the despread I and Q signals output from the PN despreader 122.

In the interference energy calculation circuit 190, the pilot channel is provided to the positive input of the pilot subtractor circuit 192 and to the pilot filter 128. The pilot filter 128 suppresses noise and interference components in the pilot channel and provides a filtered pilot signal to the negative input of the pilot subtraction circuit 192. Pilot subtractor circuit 192 subtracts the pilot channel from the filtered pilot channel to output a signal representing interference and noise per symbol, which is a calculation of power using the interference energy thereinThe channel between the transmitting base station (not shown) of the path 190 and the transceiver system (see the transmitter and receiver in fig. 1 and 2 and fig. 3 and 4). The interference and noise signal energy (N) of each symbol is calculated by the interference energy calculation circuit 194 in accordance with the following formula_l，t)：

Where M is the number of chips per WALSH symbol, N is the number of chips in the pilot burst (64 chips), and · is the output of the pilot subtractor circuit 192.

The interference energy calculation circuit 190 is employed when the constant value c provided by the first constant generation circuit 84 in fig. 6 is unknown. The constant k used by multiplier 148 may be unknown prior to demodulating the symbols on the reverse link. Thus, in fig. 8, the multiplication is performed just before LLR calculation decoding. This is the case for many reverse link applications.

Fig. 9 is a schematic diagram of another embodiment of a C/I calculation circuit 210 suitable for use with the circuit 90 of fig. 5. C/I calculation circuit 210 is a specific embodiment of C/I calculation circuit 92 in FIG. 5. The C/I calculation circuit 210 may be used with the C/I estimation circuit 120 of FIG. 6, or in place of the C/I estimation circuit 120 of FIG. 6.

The C/I calculation circuit 210 is suitable for use with the forward link and includes a normalization circuit 212. The normalization circuit 212 is connected in parallel with a square averaging circuit 214 and a squaring circuit 215. The output of the squaring circuit 215 is connected to a noise variance estimation circuit 216. The square average circuit 214 is connected in parallel with an absolute value circuit 218 and a noise variance estimation circuit 216. The output of the absolute value circuit 218 is connected in parallel with the noise variance estimation circuit 216 and a first input of a multiplier 220. A second input of the multiplier 220 is connected to an output of the noise variance estimation circuit 216.

In operation, the received data samples are normalized by normalization circuit 212 by predetermined application-specific normalization factors, which can be readily determined by one skilled in the art to meet the needs of a given application. The normalized data samples are provided to a square averaging circuit 214 which calculates an average of the squares of the complex normalized data samples. The squaring circuit 215 also calculates the normalized data sample squares, which are provided to the noise variance estimation circuit 216. The output of the squaring and averaging circuit 214, which represents an energy estimate of the data samples, is also input to a noise variance estimation circuit 216, and the noise variance estimation circuit 216 calculates a noise variance estimate for the data samples according to the following equation:

wherein σ² _zIs the noise variance of the normalized data samples; i | ^ a (n) ventilation²Is the absolute value of the square average circuit output, i.e., the output of the absolute value circuit 218; x is the number of²(n) represents the output of the square averaging circuit; n is an estimated time variable; and N is the number of data samples from which the noise variance of the data samples is calculated. N is application specific and can be readily determined by one skilled in the art to meet the needs of a given application.

The generated noise variance of the channel estimation value is output to a divider 220, and the square of the absolute value of the channel estimation value, i.e., the output of the absolute value circuit 218, is divided by the noise variance σ² _zTo generate a C/I ratio based on reasonably correct data samples. The resulting dominant signal-to-noise ratio, i.e., the data-based C/I ratio, is combined with the C/I ratio of the pilot estimate, e.g., generated by 120 in FIG. 6, to arrive at a C/I ratio that is based on the pilot estimate(1) A combined C/I estimate is generated. The combined C/I estimates are input to the data sampling SIR circuit 98 of fig. 5 and the channel estimation SIR circuit 100 of fig. 5.

The invention is thus described herein with reference to specific embodiments for particular applications. Those skilled in the art, having benefit of this disclosure, will appreciate that many additional modifications, applications, and embodiments are possible within the scope of the invention as defined by the appended claims.

It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.

Claims

1. A high efficiency telecommunications receiver system for correctly decoding a received composite signal having a data signal component and a pilot signal component, comprising:

first means for receiving said composite signal and extracting therefrom a pilot signal and a data signal;

second means for calculating log-likelihood ratios as a function of channel estimates from the pilot signals; and

third means for scaling said log-likelihood ratio by a predetermined log-likelihood ratio scaling factor and providing a correct log-likelihood value in response thereto, wherein the third means derives the predetermined log-likelihood ratio scaling factor by calculating the first and second signal-to-interference ratios; and

fourth means for decoding the received composite signal in dependence on the correct log-likelihood values and the data signal,

wherein said third means comprises a carrier signal-to-interference ratio calculation circuit for calculating a primary carrier signal-to-interference ratio.

2. The system of claim 1, wherein the pilot signal and the data signal comprise pilot samples and data samples, respectively.

3. The system of claim 2 wherein said third means includes a carrier signal-to-interference ratio circuit for calculating a first signal-to-interference ratio and a second signal-to-interference ratio based in part on said pilot signal.

4. The system of claim 3 wherein said first signal-to-interference ratio is based on said data samples and said second signal-to-interference ratio is based on said pilot samples, said first signal-to-noise ratio and said second signal-to-noise ratio providing inputs to a circuit for calculating said scaling factor included in said third means.

5. The system of claim 1, wherein the first means comprises: a despreader for despreading said received composite signal in accordance with a predetermined spreading function and providing a despread signal in response thereto.

6. The system of claim 5, wherein the spreading function is a pseudo-noise sequence or a WALSH function.

7. The system of claim 5, wherein the first means further comprises: a decovering circuit for extracting the pilot signal and the data signal from among the despread signals.

8. The system of claim 1, wherein the third means comprises: means for calculating a primary carrier signal-to-interference ratio based on the pilot signal and the data signal.

9. The system of claim 8, wherein the third means comprises: a data noise variance estimation circuit for calculating the data signal noise variance from the data signal and an energy signal derived from the data signal.

10. The system of claim 9, wherein the data noise variance estimation circuit comprises: means for calculating the noise variance of the data signal according to the following formula,

wherein σ_z ²Is the noise variance of the data signal;is the absolute value of the energy signal; x is the number of²(n) is the energy signal; n is a discrete time variable; and N is the number of data samples for which the noise variance of the data signal is calculated.

11. The system of claim 9, wherein the third means comprises: a divider circuit for calculating the primary carrier signal-to-interference ratio as a function of the absolute value of the energy signal and the noise variance of the data signal.

12. The system of claim 11, further comprising: and the data sampling signal-to-noise ratio circuit and the channel estimation signal-to-noise ratio circuit are used for respectively calculating a first signal-to-interference ratio and a second signal-to-interference ratio according to the main signal-to-noise ratio.

13. The system of claim 12 wherein said third means calculates said log-likelihood ratio scaling factor according to the formula:

wherein k is the log-likelihood ratio scaling factor; gamma ray_dIs the first signal-to-interference ratio; and gamma is_{_}Is the second signal-to-interference ratio.

14. The system of claim 13, wherein said first signal-to-interference ratio γ is expressed by the following formula_d：

Wherein E_sIs the average energy of the pilot signal, and σ² _sIs the noise variance of the received composite signal.

15. The system of claim 13, wherein said second signal-to-interference ratio γ is expressed by the following formula_{_}：

Wherein E_sIs the average energy of the pilot signal, and σ_a ²Is the noise variance of the pilot signal output by the low pass filter.

16. The system of claim 1, wherein the second means comprises: a low pass filter for filtering the pilot signal and providing a filtered pilot signal as a channel estimate in response thereto.

17. The system of claim 16, wherein the second means comprises: a first multiplier for selectively multiplying the data signal by the complex conjugate of the channel estimate and providing a weighted signal in response thereto.

18. The system of claim 17, wherein the second means comprises: a scaling circuit for scaling a real part of the weighted signal by a predetermined constant factor and generating an initial log-likelihood ratio in response thereto.

19. The system of claim 18, wherein the third means comprises: a second multiplier for multiplying said initial log-likelihood ratio by said predetermined scaling factor and providing said correct log-likelihood value in response thereto.

20. The system of claim 1, wherein the second means comprises: a filter for providing a filtered pilot signal having reduced interference components; and a complex conjugate circuit for providing a complex conjugate of the filtered pilot signal as an output.

21. The system of claim 20, wherein the third means comprises: means for multiplying said complex conjugate by said data signal to generate a result, scaling by a predetermined constant factor to generate in response said result of a coarse log-likelihood ratio, corresponding to said coarse log-likelihood ratio further scaled by said predetermined log-likelihood ratio scaling factor of said third means to generate a correct log-likelihood value.

22. The system of claim 1, further comprising: an optimized path combining circuit for optimally combining the data signal and the pilot signal in accordance with an interference component estimate of the composite received signal and providing an optimally combined signal to the third device in response thereto.

23. The system of claim 22, wherein the third means comprises: a scaling circuit for multiplying the optimally combined signal by the predetermined log-likelihood ratio scaling factor to generate the correct log-likelihood value.

24. The system of claim 23 wherein said optimized path combining circuit includes means for providing said estimate of said interference component, said providing means including a low pass filter for filtering said pilot signal to provide a filtered pilot signal.

25. The system of claim 24, wherein said means for providing said estimate further comprises: a subtractor for subtracting the filtered pilot signal from among the pilot signals and providing the estimate of the interference component in response thereto.

26. The system of claim 1, wherein said carrier signal-to-interference ratio calculation circuit includes means for estimating an interference component of said received composite signal.

27. The system of claim 26 wherein said means for estimating an interference component comprises a low pass filter for filtering said pilot signal to provide a filtered pilot signal; a received signal energy calculation circuit for providing a value representative of the total energy of said received composite signal; and means for combining the pilot signal and the value to generate the primary carrier signal-to-interference ratio.

28. The system of claim 27, wherein the second means comprises: and the data sampling signal-to-noise ratio circuit and the channel estimation carrier signal-to-interference ratio circuit are used for respectively generating the first signal-to-interference ratio and the second signal-to-interference ratio according to preset scaling factors.

29. The system of claim 1, wherein the carrier signal-to-interference ratio calculation circuit comprises: for receiving a first portion of the composite signal, the composite signal having a desired signal component and an interference and/or noise component; signal extraction circuitry for extracting the desired signal component estimate from among the received signals; and a noise estimation circuit for providing a correct noise and/or interference value in dependence on said estimate of said desired signal component and said composite signal.

30. The system of claim 29, wherein said carrier signal-to-interference ratio calculation circuit further comprises: means for calculating the primary carrier signal-to-interference ratio using the correct interference energy value.

31. The system of claim 30, further comprising: means for calculating optimal path combining weights for a plurality of signal paths comprising said signal using said correct noise and/or interference values and in response providing an optimal composite signal path to said third means for calculating said log likelihood ratio based on said carrier signal-to-interference ratio and said optimal composite signal path.

32. The system of claim 31 wherein said fourth means further comprises a TURBO decoder for decoding said received signal using said log-likelihood values.

33. The system of claim 32, further comprising: means for generating and transmitting rate and/or power control messages to an external transceiver in communication with the high efficiency receiver system.

34. A system for providing correct log-likelihood values to improve receiver performance in a wireless communication system, comprising:

first means for extracting a pilot signal and a data signal from among the received composite signals;

second means for calculating a carrier signal-to-interference ratio from said pilot signal and said data signal and providing a first signal-to-interference ratio and a second signal-to-interference ratio in response thereto;

third means for calculating a log-likelihood ratio scaling factor based on the first signal-to-interference ratio and the second signal-to-interference ratio;

fourth means for calculating log-likelihood ratios as a function of channel estimates from the pilot signals; and

fifth means for scaling said log-likelihood ratio by said log-likelihood ratio scaling factor and providing said correct log-likelihood value in response thereto.

35. A system for improving signal-to-noise ratio in a receiver employing reference symbol assisted demodulation, comprising;

means for combining information in said channel transmitted reference signals with information in corresponding known transmitted reference signals to obtain an estimate of the channel transmitted by the transmitter and received by the receiver for said reference symbols;

means for calculating a log likelihood ratio estimate for a data signal received by the receiver over the channel, the log likelihood ratio estimate being a function of the received data signal, the channel estimate, and the signal-to-noise variance;

means for applying a scaling factor to the log likelihood ratio estimate to provide a correct log likelihood ratio, the scaling factor being based on a noise variance of the channel estimate, the noise variance of the data signal, and an average of received energy per bit in the data signal; and

means for demodulating the received data signal using the correct log-likelihood value.

36. A communication system employing pilot-assisted coherent demodulation, comprising:

a transmitter having a TURBO encoder for encoding a data signal and transmitting the data signal with a pilot signal;

a first receiver portion having a TURBO decoder and a priori knowledge of the pilot signal for receiving the data signal and the pilot signal and providing the channel estimate based on the received pilot signal;

log-likelihood computation circuitry in communication with said first receiver portion, said log-likelihood computation circuitry providing a correct log-likelihood ratio by computing a log-likelihood ratio estimate for a data signal received by said receiver over said channel, said correct log-likelihood ratio being a function of a noise variance of said data signal, a noise variance of said estimate of said channel, an average received energy per information bit included in said data signal, and applying a scaling factor to said log-likelihood ratio estimate; and

a second receiver portion for demodulating the received data signal using the log-likelihood ratio as a metric.