HK1051572B - Apparatus and method for programmable parametric toggle testing of digital cmos pads - Google Patents

Description

Apparatus and method for testing digital CMOS with programmable parameter binary

Technical Field

The present invention relates generally to the field of digital CMOS devices and, more particularly, to a method and apparatus for verifying electrical parameters of an integrated circuit I/O driver.

Background

While Integrated Circuits (ICs) may have been fully tested prior to mounting to a printed circuit board, the board is typically tested at the time of installation to verify that the Integrated Circuits (ICs) are not damaged. For example, since electrostatic discharge may damage drivers (buffers) coupled to input/output pads, it is also necessary to test the circuit board to ensure that there are no shorts or opens on the I/O pads.

Generally, a single power bus supplies all of the I/O drivers. Therefore, it is important to test the power distribution among the drives to ensure that they are distributed as required. In performing the above-described measurement, parametric testing is an indispensable test item. In the parametric test, electrical characteristics (e.g., input and output current characteristics) of peripheral devices (e.g., input and output buffers) mounted on the periphery of a logic device are tested.

Known methods of testing for these faults typically include providing a complex, time consuming set of patterns for test conditions to obtain pad logic, such as providing serial scan paths through an integrated circuit device for testing purposes. Logic functions are tested by passing carefully designed digital sequences through a serial scan path. Other methods require additional external pins for accessing the device to the test method. This approach wastes pins because these tests typically only occur or are performed infrequently during device manufacturing.

In response to this problem, a boundary scan technique has been developed, and a device capable of boundary scan has the following configuration: the peripheral unit region of the IC chip contains memory circuits for testing, each of which is connected to a signal line connected to an external port, the memory circuits are connected to each other to constitute a shift register serving as a test mechanism, and the IC chip is mounted on a circuit board with the use of the test mechanism to perform a function test. Each IC chip has a data input terminal, a data output terminal, and a test control terminal connected to each terminal of the IC chip to perform a desired test, data for the test being serially inputted to the data input terminal of the IC chip, serially shifted by a control signal, and serially outputted via the data output terminal. In this way, data can be written to and read from the memory circuit, in other words, the serial shift operation of test data allows each IC chip to be tested individually. However, devices incorporating boundary scan circuitry increase the unit cost of the device and, more importantly, such circuitry consumes a significant amount of silicon material.

United states patent No. 5,764,079 to Pater et al discloses a programmable logic device having the ability to observe and control the logic state of nodes within a buried layer. United states patent No. 5,706,296 to wheatsel discloses a scan cell for use at an input/output terminal including memory circuitry for storing test data from a test data path and a latch circuit coupled to the memory circuitry for receiving and selectively latching the test data stored in the memory circuitry. In addition, U.S. patent No. 5,648,973 to Mote Jr discloses a method of switching output pins of an IC chip using JTAG.

Therefore, there is a need for a test method for testing I/O drivers on IC pads on a circuit board without requiring complex test patterns. It is desirable to provide parametric testing within a few test vectors on a tester, which is desirable with a minimum required amount of IC silicon, and to provide an I/O pad testing scheme without having to specify additional dedicated pins on the chip.

Summary of The Invention

An IC device with parametric test capability contains core logic circuitry, input and output drivers, a coupling circuit associated with each input of the core logic circuit and a selector circuit associated with each output of the core logic circuit, each of the coupling circuit and the selector circuit having first and second inputs and an output, each input of the core logic circuit being coupled to the first input of the circuit associated with the input, each output of the core logic circuit being coupled to the first input of the selector circuit associated with the output, the coupling and selector circuits being connected to form a test chain, i.e. the output of each coupling circuit is fed to the second input of the other coupling circuit or to the second input of the selector circuit, and the second input of each selector circuit is coupled to the second input of another selector circuit or to the second input of a coupling circuit.

Drawings

FIG. 1 shows a preferred embodiment of the circuit of the present invention.

FIG. 2 is a data register placed in a test mode.

Figure 3 shows another scenario of putting into test mode.

Figure 4 shows another arrangement for coupling the bi-directional sections in a test link.

Fig. 5 and 6 illustrate the circuit of the present invention independent of the I/O pad arrangement.

Best mode for carrying out the invention

Referring to the preferred embodiment of the circuit schematically illustrated in FIG. 1, a digital Integrated Circuit (IC) device includes a core logic circuit 100 having a plurality of I/O lines. Including "pure" input lines 172 and 174 (only input lines), "pure" output lines 182 and 184 (only output lines), and bidirectional portions, each of which consists of a set of lines, such as one input line 192, one output line 194, and one output enable line 193. FIG. 1 shows a second set of bi-directional lines 196-198. It should be noted, of course, that fig. 1 illustrates only one example of a symbolic IC device, and that there are many more I/O lines than those shown in fig. 1 for an actual device, which are also not shown. But utility lines such as power and ground lines are believed to exist.

Except that input lines 172 and 174 are coupled to input drivers (buffers) 132 and 134, respectively, which input drivers (buffers) 132 and 134 are in turn coupled to input lands 112 and 114. Except that output lines 182 and 184 are coupled to the "0" inputs of multiplexers 162 and 164, respectively, the outputs of 162 and 164 are coupled to output drivers (buffers) 136 and 138, respectively, and the outputs of 136 and 138 are coupled to output pads 120 and 122, respectively.

For the bidirectional line set 192 and 194, the input line 192 is coupled to the input driver 142 with its input coupled to the pad 116, the output line 194 is coupled to the "0" input of the multiplexer (selector) 152, the output of 152 is coupled to the output driver 144, which is also coupled to the pad 116, the output enable line 193 is coupled to the "0" input of the selector 154, and the output of 154 is coupled to the output enable line of the output buffer 144.

For the bidirectional line set 196 and 198, the input line 196 is coupled to the inputs of the input drivers 146, 146 to the pad 118, the output line 198 is coupled to the "0" input of the multiplexer 156, the output of the multiplexer 156 is coupled to the output driver 148, the output of the driver 148 is also coupled to the pad 118, the output enable line 197 is coupled to the "0" input of the multiplexer 158, and the output of the multiplexer 158 is coupled to the output enable line of the output buffer 148.

The plurality of NAND gates 102-108 are associated with only input lines 172 and 174 and with input lines 192-196 of the bidirectional line groups 192-194 and 196-198. A first input of nand gate 102 is coupled to input line 172, and similarly, a first input of nand gate 104 is coupled to input line 174, and first inputs of nand gates 106 and 108 are coupled to input lines 192 and 196 of the bidirectional line segment, respectively.

The output of each nand gate is coupled to the input of an adjacent nand gate. Thus, the output of NAND gate 102 is coupled to a second input of NAND gate 104; the output of NAND gate 104 is coupled to a second input of NAND gate 106; the output of NAND gate 106 is coupled to a second input of NAND gate 108; NAND gate 108 is coupled to second inputs of multiplexers 162 and 164. Looking back at NAND gate 104, it can be seen that its output is also coupled to a second input of multiplexer 152, and the output of NAND gate 106 is also coupled to a second input of multiplexer 156.

In furtherance of the discussion of FIG. 1, each multiplexer 152 and 164 is controlled by a test control line T1. In addition, the "1" inputs of multiplexers 154 and 158 are coupled to a second test control line T2.

The provenance of test control signals T1 and T2, discussed with reference to fig. 2, is provided with an n-bit register 200 in core logic circuit 100, which is accessed in a conventional manner by setting the register address on address line 206. The 0 and 1 bits of the register 200 are connected to control lines T2 and T1, respectively, and are simply set and reset as needed in a conventional manner by setting the appropriate data on the data lines 208 and writing to the register 200 by asserting the Chip Select (CS) pin 202 and the Write (WR) pin 204. Resetting the chip will clear the register and put the device into normal operation mode.

Referring to FIG. 3, another method of providing control lines T1 and T2 is shown, where it can be seen that two input pads 302 and 304 are coupled to latches 312 and 314, respectively, and the outputs of latches 312 and 314 are control lines T1 and T2. The third input pad 306 is coupled to the clock input of the latch. As shown, latches 312 and 314 may be reset via reset pins 332 and 334, respectively. If the pads 302, 304, and 306 are made as pull-down pads on the chip, the pads do not have to be soldered to the chip package, the control signals T1 and T2 are set by setting the desired logic levels on the pads 302 and 304, and the pads 306 are asserted to latch data onto the signal lines T1 and T2. Another embodiment shown in fig. 3 shows: the signals T1 and T2 may be generated in other ways in which the control lines T1 and T2 are provided directly with the I/O pads specified for the particular semiconductor device. The embodiment of fig. 2 is preferred for the case where the register access mechanism is typically part of the core logic circuitry function, and therefore this configuration is appropriate for providing a way of generating the control signals T1 and T2.

Referring to fig. 4, another embodiment of constructing a bidirectional wire set in accordance with the present invention is shown. Fig. 4 shows the portion of fig. 1 associated with bi-directional line groups 192 and 194, with the same reference numerals used to identify common circuit elements. Fig. 4 additionally adds a multiplexer (selector) 402 whose "0" input is coupled to the output of nand gate 106, while the "1" input of the selector receives the output of a preceding nand gate (not shown). The multiplexer has its selector input connected to the T2 signal line. While the embodiment shown in fig. 4 will work in accordance with the present invention, the circuit shown in the embodiment of fig. 1 is preferred because it consumes less silicon material. The embodiment of fig. 4 is additionally provided with a multiplexer, whereas the circuit of fig. 1 is not required to be provided with a multiplexer.

The discussion will turn to the operation of the circuit of fig. 1 in accordance with the present invention. First, normal operation of the device occurs when there is no signal on the T1 and T2 control lines. In the preferred embodiment, normal operation of the device is achieved by writing the appropriate bit value to register 200. In normal operating mode, output lines 194 and 198 of the bidirectional line section are coupled to output drivers 144 and 148, respectively, via multiplexers 152 and 156. Likewise, output drivers 136 and 138 are coupled to only output lines 182 and 184 via multiplexers 162 and 164.

When a binary test pad is required, the T1 and T2 control lines are set accordingly, with two test modes: in test mode 1, the bidirectional pads 116 and 118 are programmed to function as input pads, which is achieved by asserting signals T1 and T2. The access signal T1 does not affect the input drivers 132 and 134. Output drivers 136 and 138 are disconnected from output lines 182 and 184 of core logic circuit 100 and coupled to the "1" inputs of multiplexers 162 and 164, respectively. Output drivers 144 and 148 of the bidirectional line section are disconnected from output lines 194 and 198 and coupled to the "1" inputs of multiplexers 152 and 156, respectively. Similarly, the output enable terminals of drivers 144 and 148 are coupled to the T2 signal line via multiplexers 154 and 158. However, in test mode 1, the driver 144 and 148 outputs are tri-stated because the T2 signal is not asserted. Therefore, the bidirectional part is made the input terminal in test mode 1.

In test mode 2, the bidirectional pads 116 and 118 are programmed to function as output pads. This is accomplished by the access signal T1 and the do not access signal T2, the access signal T1 acting as described above, the do not access signal T2 having an additional effect on the enable outputs of the bidirectional pad drivers 144 and 148 via the respective multiplexers 154 and 158. Thus, regardless of the state of the "1" inputs of multiplexers 152 and 156, the outputs of NAND gates 104 and 106 are now driven to pads 116 and 118 via drivers 144 and 148, respectively. Thus, the bidirectional part becomes an output terminal in test mode 2.

The parametric binary testing of the pads according to the invention is started by selecting the desired test mode (mode 1 and mode 2) described above. A single low-level pulse is then applied to the input pad on top of the test link as shown in fig. 1. Thus, when the first input pad is accessed to L0, all other input pads (including the bidirectional portion if test mode 1 is used) are accessed to HI. The pulse will propagate down the test link, delayed by the nand gates along the propagation path and eventually reach the output pad. The above process is repeated for each input pad, wherein a low level pulse is applied to the next input pad, as a result of which the switching levels (Vil and Vih) of each input driver will be tested and the switching levels (Vol and Voh) of the output drivers will be switched.

As mentioned above, the test chain must start with a pure input (input only) pad, and of course, having a pure output (output only) pad at the beginning of the test chain would prevent parametric testing of that pad. Also, having a bi-directional portion at the beginning of the test link may prevent testing of the bi-directional pad in the output mode (test mode 2), although such pads may be tested in the input mode state (test mode 1), similar constraints occur at the end of the link, in other words, the link must be terminated with a pure output pad. Ending the link with a pure input pad then the pad cannot be tested, and likewise ending the link with a bidirectional pad does not test the pad in test mode 1 state, although the pad can be tested in test mode 2. Finally, it is noted that the circuit of the present invention allows any sequential arrangement of pads between the beginning and the end of the link, as is illustrated in the embodiments of fig. 5 and 6.

Fig. 5 and 6 show that: the bi-directional pads can be interspersed with pure input pads and pure output pads, also indicating that pure output pads do not have to be clustered at the end of the link, and instead pure input pads do not have to be clustered at the beginning of the link, this freedom of ordering allowing the design of the logic circuit being fabricated to be free of artificial constraints, which are usually imposed by parametric testing requirements. The I/O pads may be arranged in any order that facilitates the design of the functional blocks that comprise the core logic. Only the link is required to start with a pure input pad and end with a pure output pad. Even this restriction can be relaxed to allow the bidirectional pads to be placed before the link or at the termination, as long as it is remembered that the leading bidirectional pad cannot be tested as the output and the trailing bidirectional pad cannot be tested as the input.

Another advantage of the present invention is that only a few vectors are needed to fully test the switch levels of all input/output pads. In fact, only the same vector as the number of input pads is required. In addition, the input and output drivers of the bidirectional pad can be tested by this scheme, and with an addressable set test control signal T1 and T2, an additional increase of test mode pins can be avoided with a data register, which would otherwise consume a large amount of silicon, and the test mode can be conveniently selected by writing to the register.

Claims (11)

1. A test circuit adapted for testing input and output circuits of an integrated circuit, the integrated circuit comprising input-only lines, output-only lines, and bidirectional line groups, each bidirectional line group comprising an input line, an output line, and an output enable line, the test circuit comprising:

a plurality of first coupling circuits, each first coupling circuit associated with a pure input line, each first coupling circuit having a first input, a second input and an output, the first input of each first coupling circuit being connected to its associated pure input line;

a plurality of first selector circuits, each associated with a pure output line, each first selector circuit having first and second inputs, an output and a control input selectively coupling the output to either the first input or the second input, the first input of each first selector circuit being connected to its associated pure output line;

a plurality of second coupling circuits, each second coupling circuit associated with a bidirectional line group, each second coupling circuit having a first input and a second input and an output, the first input of each second coupling circuit being connected to the input line of its associated bidirectional line group; and

a plurality of second selector circuits, each associated with a bidirectional line group, each second selector circuit having first and second inputs, an output and a control input selectively coupling the output to either the first input or the second input, the first input of each second selector circuit being coupled to the output line of its associated bidirectional line group; and

a test select signal line coupled to the control input of each of the first and second selector circuits;

combining all of the coupling circuits and selector circuits described above into a single test link, wherein the starting circuit of the test link is one of the first coupling circuits, wherein the outputs of the first and second coupling circuits are each coupled to the second input of one of the coupling circuits or one of the selector circuits, wherein the second inputs of the first and second selector circuits are each coupled to the second input of one of the coupling circuits or one of the selector circuits, and the terminating circuit of the test link is one of the first selector circuits.

2. The test circuit of claim 1, further comprising means for setting and unsetting logic states on the test select signal line.

3. The test circuit of claim 1, further comprising a data register having a plurality of bits, the first bit coupled into the test select signal line, whereby the first and second selector circuits are operated by writing a certain data into the data register, setting or resetting a leading bit of the data register.

4. The test circuit of claim 1, further comprising a plurality of third selector circuits, each third selector circuit having first and second inputs, an output and a control input, the control input selectively coupling the output to either the first input or the second input, each third selector circuit associated with one of the sets of bidirectional lines, each third selector circuit having its first input connected to the output enable line of its associated set of bidirectional lines, the control input of each third selector circuit connected to the test select line; the test circuit also has a second test select signal line coupled to the second input of each third selector.

5. The test circuit of claim 4, further comprising first means for setting and unsetting the logic value on the test select signal line and second means for setting and unsetting the logic value on the second test select signal line.

6. The test circuit of claim 4, further comprising a data register having a plurality of bits, a first bit coupled to the test select signal line and a second bit coupled to the second test select signal line, whereby the selector circuit is operated by writing a data to the data register to set or reset the first bit and the second bit of the data register.

7. The test circuit of claim 1, wherein the second input of the start circuit is coupled to a power supply line.

8. A digital integrated circuit device having logic circuitry for facilitating parametric testing of I/O buffers therein, said digital integrated circuit device comprising:

a plurality of input pads, output pads and bidirectional pads;

a plurality of input buffers, each buffer having an input terminal connected to one of the input pads or one of the bidirectional pads, and an output terminal;

a plurality of first output buffers, each first buffer having an output terminal connected to one of the output pads and an input terminal;

a plurality of second output buffers, each having an output terminal connected to one of the bidirectional pads, an input terminal and an output enable terminal;

an enable device coupled to the output enable terminal for setting an enable signal on a selected one of the second output buffers;

a core logic circuit having a plurality of core input and output terminals, each core input terminal being coupled to the output terminal of one of the input buffers;

a plurality of coupling circuits, each having a first input connected to one of the core inputs, a second input and an output;

a plurality of selector circuits, each selector circuit having a first input terminal, a second input terminal and an output terminal, and a selector input terminal controlling connection of the first input terminal or the second input terminal to the output terminal, the first input terminal of each selector circuit being connected to one of the core output terminals, and the output terminal thereof being connected to the input terminal of one of the first output buffers or one of the second output buffers; and

circuit means for setting selector signals, the circuit means having an output connected to the selector input of each selector circuit;

the coupling circuits and the selector circuits are connected to form a single link, the first circuit of the link being one of the coupling circuits and the last circuit of the link being one of the selector circuits, wherein the output of each coupling circuit is connected to the second input of the other coupling circuit or one of the selector circuits, and wherein the second input of each selector circuit is connected to the second input of the other selector circuit or one of the coupling circuits.

9. The digital integrated circuit device of claim 8, wherein said circuit means is an addressable data register having at least one bit coupled to the selector input of each selector circuit.

10. The digital integrated circuit device of claim 8, wherein the second input of the start circuit of the link is connected to a power supply line.

11. The digital integrated circuit device of claim 8, wherein the enabling means comprises a plurality of control lines from the core, each control line having an associated second selector circuit, each second selector circuit having first and second input terminals, an output terminal and a selector terminal; wherein a first input terminal of each second selector circuit is coupled to one of the output enable lines, the selector is coupled to an output terminal of the circuit arrangement, and the output terminal is coupled to an output enable terminal of one of the second output buffers; the digital integrated circuit device further includes second circuit means for setting the second selector signals, the second circuit means having an output coupled to the second input of each of the second selector circuits.