HK1046194A - Offset compensation in analogue-digital converters - Google Patents

Description

Bias compensation in analog-to-digital converters

Technical Field

The invention relates to a method and a device according to the preambles of the respective independent claims 1 and 4.

Background

The digitization of analog signals requires the use of analog-to-digital converters. High sampling speeds are required to convert a real-time analog signal to digital form. One way to achieve the sampling speed required for real-time conversion is to use so-called parallel analog-to-digital converters.

An example of such a parallel analog-to-digital converter is disclosed in us patent specification 5,585,796.

A problem with such an analog-to-digital converter is that the analog-to-digital conversion branches have mutually different bias voltages. A parallel analog-to-digital converter comprises several time-division multiplexed branches, each branch having a unique bias voltage, which may result in undesired frequency components in the output signal of such an analog-to-digital converter.

This problem has been solved with analog bias compensation of the correlated double sampling type as disclosed in "10-bit 5MS/s successive approximation ADC cell used in a70MS/s ADC array for 1.2um CMOS" A10-bit 5MS/s complementary approximation ADC cell used in a70MS/s ADC array in 1.2um CMOS ", IEEE Journal of Solid State diagnosis, Vol.29, No.8, pp.866-872, August 1994, J.Yuan and C.Svensson.

A disadvantage of this technique is that such analog bias compensation requires a certain amount of time to implement, in this case four clock cycles, thus increasing the time required for one branch conversion.

Summary of The Invention

The present invention addresses the above-mentioned problems by providing a bias compensation method for a parallel analog-to-digital converter according to claim 1 and a parallel analog-to-digital converter according to claim 4.

It is an object of the present invention to provide a digital bias compensation method that at least alleviates the above-mentioned problems.

In this respect it is a particular object of the invention to provide a method for bias compensation in a parallel analog-to-digital converter, which allows a large compensation of the bias voltage without affecting the signal-to-noise ratio of the output signal.

An advantage of the invention is that the analog devices in the analog-to-digital converter that affect the bias voltage can be less accurate but still do not affect the accuracy of the output signal.

Another advantage of the present invention is that such a method can be easily implemented.

An advantage of a preferred embodiment of the invention is that the bias voltage can be removed for each branch by subtracting the average value of the analog-to-digital converter output signal, thus allowing the bias voltage to be larger.

The present invention will be described in detail below by way of preferred embodiments with reference to the accompanying drawings.

Brief description of the drawings

Fig. 1 is a schematic block diagram illustrating a first embodiment of a parallel analog-to-digital converter of the present invention.

Fig. 2 is a schematic block diagram illustrating a second embodiment of the parallel analog-to-digital converter of the present invention.

Fig. 3 illustrates an embodiment of a complex sample and hold unit and sign changing means.

Detailed description of the preferred embodiments

Fig. 1 illustrates an exemplary embodiment of a parallel analog-to-digital converter in accordance with the invention. A parallel analog-to-digital converter comprises at least two analog-to-digital converters, which are referred to in this document as branches. In this embodiment shown in fig. 1, the parallel analog-to-digital converter comprises three branches 35. As shown in fig. 1, the input of each branch is connected to a sample-and-hold unit 30, which comprises a sign changing device. The analog input signal 10 is applied to these sample-and-hold units which are connected to the inputs of the respective branches. The analog signal is sampled at a given frequency in a sample-and-hold unit. The sampling frequency is controlled by the time control unit 50. The sign of the sample values is also changed within the sample-and-hold unit. The sign change in each sample-and-hold cell is done separately, changing the sign of the signal in a pseudo-random manner. Instead of one symbol changing device for each branch, it is also possible to use a common symbol changing device for all branches.

The symbol change is controlled by a symbol control unit 40, which may be a Pseudo Random Binary Sequence (PRBS), which is well known to those skilled in the art and therefore need not be described in detail. After the signal has been passed to the sample and hold unit and the sign has been changed in a pseudo-random manner, the signal can be said to be zero-mean noise.

The signal then passes through the respective analog-to-digital converters. A so-called bias voltage is applied to each of these analog-to-digital converters. The different branches typically each have a unique bias voltage. The branches within a parallel analog-to-digital converter are time-multiplexed. The conversion of the analog signal into a digital signal in a parallel analog-to-digital converter is carried out by the branches at a certain time offset with respect to one another. This offset repeats as a signal with a particular pattern.

The time division multiplexing of the individual branches is controlled by a time control unit 50. After passing through the respective branches, the signal can be said to include noise and a bias voltage.

The output signals of the branches can be respectively reconstructed into original signals through a sign changing device as shown in figure 1, and the influence of bias voltage can be reduced. The sign of the output signal of each branch is changed in the sign changing means 90 in the same pseudo-random pattern as the sign of the input signal, this pseudo-random sequence will now act on the bias voltage instead of on the signal. This recovers the signal (with the correct sign) while the bias voltage contains energy that appears as noise in this frequency domain. Thus, the distortion spikes in the output signal spectrum disappear and are replaced by noise.

The output signals 100 of the respective sign changing means 90 are multiplexed in the same order as the demultiplexing, resulting in a digital representation of the analog input signal.

Fig. 2 illustrates another embodiment of the parallel analog-to-digital converter of the present invention. This embodiment also achieves a reduction of the influence of the respective biases of the branches on the output signal. The bias voltage may be substantially removed by subtracting the average value of the output signal from each branch before the output signal is passed to a sign changing means.

Fig. 2 illustrates an embodiment of an analog-to-digital converter comprising three branches 35. Connected to the inputs of the branches shown in fig. 2 are sample-and-hold units each further comprising a sign changing means. The analog input signal 10 is applied to these sample-and-hold units which are connected to the inputs of the respective branches. The analog signal is sampled at a given frequency in a sample-and-hold unit. The frequency at which the sampling is performed is controlled by the time control unit 50. The sign of the sample values is also changed within the sample-and-hold unit. The sign change in each sample-and-hold cell is done separately, changing the sign of the signal in a pseudo-random manner. The symbol change is controlled by a symbol control unit 40, which may comprise a Pseudo Random Binary Sequence (PRBS), which is well known to those skilled in the art and will therefore not be described in detail. After the signal has been passed to the sample and hold unit and the sign has been changed in a pseudo-random manner, the signal can be said to comprise zero-mean noise.

The signal then passes through the respective analog-to-digital converters. A so-called bias voltage is applied to each of these analog-to-digital converters. The different branches typically each have a unique bias voltage. The branches within a parallel analog-to-digital converter are time-multiplexed. The conversion of the analog signal into a digital signal in a parallel analog-to-digital converter is carried out by the branches at a certain time offset with respect to one another. This offset repeats as a signal with a particular pattern.

The time division multiplexing of the individual branches is controlled by the control unit 50. After passing through the respective branches, the signal can be said to include noise and a bias voltage.

By passing the output signal of each branch of fig. 2 first through an adding operation 60, then through a dividing operation 70, and finally through a subtracting operation 80 before being passed to the sign changing means 90, the original signal can be recovered, greatly reducing the influence of the bias voltage. An average value is first subtracted from the output signal of each of said branches to reduce the bias voltage significantly, and the signal is then brought to the correct sign by changing the sign in the sign changing means 90 in the same pseudo-random pattern as the sign of the input signal. Since the correct signal has a random characteristic of zero mean, the average of the output data of the branches is determined entirely by the bias voltage. This bias is not completely removed because the formation of the average is limited by numerical accuracy.

Instead of subtracting an average from the corresponding branch, the bias voltage may also be determined by artificially generating a sequence of periods having the same frequency as the spectral components in the digital signal derived from the bias voltage.

The general approach to interference suppression is to generate an interference basis based on measurements or artifacts and then adaptively estimate the corresponding weights. In the case shown, the bias voltage O can be expressed as a linear combination of some basis functions B and weights w.

The simplest is to select the basis functions as unit vectors for each bias voltage. Standard logarithms, such as LMS (least mean square) logarithms, can then be used, the sign-sign version of the dedicated LMS being suitable for implementation, since no multiplication, division or addition is required, but only one counter can be used instead.

The M different bias voltage levels produce M spectral components in the digital signal.

Fig. 3 illustrates a method of implementing the sign changing means within the sample and hold unit. The analog input signals applied to the parallel analog-to-digital converters are preferably differential. An advantage of a differential system is that it is less sensitive to disturbances and disturbances than a system that contains a signal conductor and a return conductor (the most common being ground). Signal information in a differential system arrives over two conductors, the value on one conductor being va and the value on the other conductor being vb. As shown in fig. 1, assuming the value on conductor 1 is va and the value on conductor 2 is vb, then the signal can be represented as S ═ va-vb.

By closing the reopening switches 11 and 22 very quickly, the signal applied to the input of the analog-to-digital converter is sampled by two sampling capacitors c1 and c 2. The charge stored in the capacitor is used later as an input signal to the analog-to-digital converter.

Qsignal＝cs1*va-cs2*＾vb。

cs1 and cs2 are generally the same. To implement the sign changing means (clipper), i.e. to implement the multiplication with-1 and +1, only two additional switches 12 and 21 are required. These switches are used to sample in opposite sign. Suppose vb is-va and CS1 is CS2 is CS. The normal (+1) sample will then be

Qsignal＝CS*va-CS*(-va)＝2*CS*va。

The sign inversion sampling will be

Qsignal＝CS*(-va)-CS*va＝-2*CS*va。

In order to reconstruct the signal after having been converted into digital form, a multiplication with-1 is required. This is simple and well known in the case of binary numbers and will not be described in detail here.

The invention is of course not limited to the exemplary embodiments of the invention described and illustrated above, since many variations can be realized within the scope of the appended claims.

Claims (13)

1. A method of bias compensation for a parallel analog-to-digital converter comprising at least two branches in which analog-to-digital conversion is performed with a time offset with respect to each other, said method being characterized by:

multiplying the analog input signal applied to the analog-to-digital converter by +1 or-1 in accordance with an arbitrary pattern; and

the output signal of the analog-to-digital converter is multiplied by +1 or-1 in the same arbitrary pattern as used to multiply the input signal.

2. A method according to claim 1, characterized by subtracting the average value of the output signal of each branch before multiplying the output signal by said arbitrary pattern.

3. A method according to claim 1, characterized by subjecting the output signal to interference suppression before multiplying said output signal by said arbitrary pattern.

4. A method according to claim 3, characterised in that said processing is an LMS (least mean square) processing.

5. A method according to any preceding claim, characterised in that said arbitrary pattern is generated by controlling a sign changing means with a PRBS (pseudo random binary sequence) generator.

6. A parallel analog-to-digital converter comprising at least two branch circuits (35) for analog-to-digital conversion in respective branch circuits (35) with a mutual time offset, characterized in that said parallel analog-to-digital converter comprises: means for multiplying the analog input signal applied to the analog-to-digital converter by +1 or-1 in accordance with an arbitrary pattern; and means for multiplying the output signal of said analog-to-digital converter by +1 or-1 in the same arbitrary pattern as the multiplication of the input signal.

7. A parallel analog-to-digital converter according to claim 6, characterized in that the means for multiplying the analog input signal applied to the analog-to-digital converter by +1 or-1 in an arbitrary pattern are common for all branches.

8. A parallel analog-to-digital converter according to claim 6, characterized in that the means for multiplying the analog input signal applied to the analog-to-digital converter by +1 or-1 in an arbitrary pattern are dedicated to each branch.

9. A parallel analog to digital converter according to any of claims 6 to 8, characterised in that the parallel analog to digital converter comprises means for averaging the output signal of each branch in the parallel analog to digital converter and means for subtracting the average from the output signal.

10. A parallel analog-to-digital converter according to claim 9, characterized in that said means for multiplying the input signal to said analog-to-digital converter and the output signal of said analog-to-digital converter by +1 or-1 according to an arbitrary pattern is a sign changing means controlled by a PRBS (pseudo random binary sequence) generator.

11. A parallel analog-to-digital converter according to any of claims 6-10, characterized in that the analog-to-digital converter is of the successive approximation type.

12. A parallel analog-to-digital converter according to any of claims 6-11, characterized in that the parallel analog-to-digital converter comprises subjecting the output signal to an interference suppression process before multiplying the output signal by the arbitrary pattern.

13. A parallel analog-to-digital converter according to claim 12, characterized in that said processing is an LMS (least mean square) processing.