HK1044061A1

HK1044061A1 - Concurrent display and data communicating using leds

Info

Publication number: HK1044061A1
Application number: HK02105612.5A
Authority: HK
Inventors: Kwok-Hung Pang Grantham; S. Yang Edward; Sun-Kin Yeung Chris; Kin-Ming Hong Michael; Yang David; Liu Hugh-Sing; Kwan To-On; Ko Ming-Him; Chan Chi-Ho
Original assignee: 弗西蒂技术有限公司
Priority date: 1998-03-20
Filing date: 1999-03-19
Publication date: 2002-10-04
Also published as: CN1334949A; EP1072026A4; JP2002527917A; EP1072026A1; WO1999049435A1

Abstract

A concurrent signaling and data communication system based on the modulation and encoding of digital information using the visible light emitted by light emitting diodes (LEDs) is provided. A general-purpose system includes a transmitter (14a) and receiver circuit (16) coupled to respective computer system (10, 12). The transmitter (14a) is further coupled to an LED beacon (14b), LED dot matrix display (22), or other configuration of LEDs that can be used for simultaneous display and data communication. The computer (10) coupled to the transmitter (14a) is used to control the data communication function of the LEDs, and also may be used to control the display function. A separate computer may also be used to control the display function distinct from the data communication function. The computer (12) coupled to the receiver interprets the data communicated over the optical link between the transmitter (14a) and receiver (16), and may display this information to a user of the system. Two transmitter and receiver designs are provided, one for a non-multi-tasking environment, and the other design for a multi-tasking environment. Several applications of the general-purpose system are provided, including a vehicle speed limiting application, a vehicle location and guidance system application, and a portable traveler information and location system application.

Description

System and method for concurrent display and data communication using light emitting diodes

This application claims priority from four provisional applications filed in the united states within the year of filing date of this application-united states serial No. 60/078,686; 60/078,684, respectively; 60/082,626, respectively; and 60/078,691.

The present application relates to the field of LED display systems and data communications. In particular, the present invention provides a concurrent display and data communication system and method using LEDs as concurrent display and data communication components. The present invention also provides for various applications of the inventive concurrent display and data communication system.

The present invention provides a concurrent signaling and data communication system based on the modulation and encoding of digital information using visible light emitted by one or more Light Emitting Diodes (LEDs). A general system in accordance with the invention includes transmitter and receiver circuits coupled to respective computer systems. The transmitter is also coupled to an LED beacon, LED dot matrix display, or other LED configuration that can be used for simultaneous display and data communication. A computer coupled to the transmitter is used to control the data communication functions of the LEDs and also to control the display functions of the system. A separate computer may alternatively be used to control display functions other than data communication functions. A computer coupled to the receiver interprets the data communicated over the optical link between the transmitter and receiver and may display this information to a user of the system. Two transmitter and receiver designs are provided, one for a non-multitasking distribution environment and the other for a multitasking distribution environment. Several applications of the general system are provided, including a vehicle speed definition application, a vehicle location and guidance system application, and a portable traveler information and location system application.

In addition, the general-purpose system includes one or more executable computer programs running on one or more computers coupled to the LED transmitters. These executable computer programs provide software control for the data transfer functions of the system and also provide display control for the LED beacons or display dot matrix displayed characters, decoration patterns or messages. The receiver includes a lens system for focusing light from the LED onto a photodetector. Using appropriate electronics and an executable computer program within a receiving computer, the information of the light emission from the LEDs is demodulated to provide emission data. The receiver is located a distance from the LED and is designed to demodulate the light emission data and then store or display the encoded message at the associated computer. To eliminate flicker in the LEDs caused by the modulated data signal, the frequency at which the LEDs are turned on/off by the transmitter is made high enough so that the light emitted by the LEDs appears to the human eye as constant illumination.

In accordance with the teachings of the present invention, the LED can be used as a communication device for the transmission and broadcasting of information and data, in addition to its conventional function as an indication and illumination device. Thus, the LED display (or lighting) component becomes part of an open space, wireless optical communication system.

In one aspect, the invention provides a new short-range beacon to support vehicle-to-roadside communications. Many applications are provided where such data transfer is most advantageous. For example, a traffic light may be constructed with LEDs having the concurrent data transmission function (and display function) described herein. Motorists use the receiver to get messages from traffic lights. These messages may include location and current traffic information such as street name, speed limit, road conditions, or location of the nearest hospital or gas station. Or the driver can check his e-mail via an optical data link. Other applications include file transfer from one computer to another, or a portable two-way information transmission and reception system. With such a two-way system, a student can use his/her notebook computer to download his/her job questions over an optical data link to the instructor's computer located at the front of the classroom.

According to another aspect of the present invention, there is provided a concurrent signaling and data communication system comprising a data display and communication system, a data receiving system, and one or more LEDs coupled to the data display and communication system, the LEDs emitting a visible display signal and a modulated data communication signal to operate as concurrent components.

Another aspect of the invention provides a vehicle speed limiting system comprising a concurrent display and data communication component operating as both a visual display component and a data communication component, wherein the data transmitted by the concurrent display and data communication component is vehicle speed limiting data, and an in-vehicle data processing receiver for receiving the transmitted vehicle speed limiting data from the concurrent display and data communication component and for processing the received data.

Yet another aspect of the present invention provides a vehicle location and guidance system. The system includes a concurrent display and data communication component operating as both a visual display component and a data communication component, wherein data transmitted by the concurrent display and data communication component includes location and direction information, and an in-vehicle data processing receiver for receiving the transmitted location and direction information from the concurrent display and data communication component and for processing the received data, the receiver including a central processing unit, a visible light receiver module, and a positioning module.

Yet another aspect of the present invention provides a portable travel information and location system. The system includes a concurrent display and data communication component operating as both a visual display component and a data communication component, and a portable travel information system for receiving data transmitted by the concurrent display and data communication component and displaying the data to a user of the portable travel information system.

It should be noted that these are merely some of the many aspects of the present invention. Other aspects not specifically listed will become apparent upon reading the detailed description set forth below.

The present invention provides a number of advantages over currently known data communication systems. Not all of these advantages may be present in practicing the claimed invention, but only a list of types of advantages that may be provided, individually or in combination, is set forth below. These advantages include: (1) the ability to concurrently operate LED beacons or other types of displays to simultaneously display the pattern of indicator lights for certain operating conditions and also to transmit modulated digital data; (2) providing two types of receiver/transmitter circuitry, one for a non-multitasking distribution environment and the other for a multitasking distribution environment; (3) the optical link between the transmitter and receiver of the present invention is in a portion of the electromagnetic spectrum not currently managed by the FCC or other similar regulatory agency; (4) short-range operation; (5) the cost is low; and (6) ease of scheduling.

These are but a few of the many advantages of the present invention, as described in detail in relation to the preferred embodiments. As will be realized, the invention is capable of other and different embodiments, and its details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description of the preferred embodiment are to be regarded as illustrative in nature, and not as restrictive.

FIG. 1 is a schematic diagram of a universal concurrent display and data communication system using one LED light beacon as a concurrent component in accordance with the present invention;

FIG. 2 is a schematic diagram of a universal concurrent display and data communication system using an LED dot matrix display as a concurrent component in accordance with the present invention;

FIG. 3 lists an exemplary communication protocol for one data frame of the present invention;

FIG. 4 is a block diagram of a preferred digital data transmitter for use in the concurrent display and data communication system of the present invention;

FIG. 5 is a block diagram of a preferred digital data receiver for use in the concurrent display and data communication system of the present invention;

FIG. 6 is a block diagram of an alternative digital data transmitter having a memory buffer for use in the concurrent display and data communication system of the present invention;

FIG. 7 is a schematic illustration of operating conditions associated with the alternative digital data transmitter of FIG. 6 including a serial input/output device having a lower read time than a PC coupled to the data transmitter;

FIG. 8 is a schematic illustration of operating conditions associated with the alternative digital data transmitter of FIG. 6 including a serial input/output device having a read time higher than a PC coupled to the data transmitter;

FIG. 9 is a block diagram of an alternative digital data receiver having a memory buffer for use in the concurrent display and data communication system of the present invention;

FIG. 10 is a schematic illustration of operating conditions associated with the alternative digital data receiver of FIG. 9 in which no idle bytes are received;

FIG. 11 is a schematic representation of operating conditions associated with the alternative digital data receiver of FIG. 9 in which idle bytes are received between frames;

FIG. 12 is a timing diagram for explaining the source of errors in a frame;

FIG. 13 is a diagram of a vehicle speed limiting application of the concurrent display and data communication system of the present invention using LEDs for traffic lights, street lights, message signs or road signs;

FIG. 14 is a diagram of a visible LED transmitter associated with the application shown in FIG. 13;

FIG. 15 is a block diagram of an in-vehicle system associated with the application shown in the vehicle speed limiting application of FIG. 13;

FIG. 16 is a block diagram of a visible light emitter module associated with the in-vehicle system shown in FIG. 15;

FIG. 17 is a diagram of a car locating and guidance system of the concurrent display and data communication system of the present invention using LEDs for traffic lights, street lights, message signs or road signs;

FIG. 18 is a block diagram of an inertial positioning module associated with the application of the system shown in FIG. 17;

FIG. 19 is a diagram of a portable travel information system of the concurrent display and data communication system of the present invention using LEDs for traffic lights, street lights, message signs or signposts;

FIG. 20 is a block diagram of a preferred portable travel information and location unit; and

FIG. 21 is a schematic view of an exemplary user interface for the portable travel information and location unit shown in FIG. 21.

1. Concurrent display and data communication system using LEDs

Turning now to the drawings, FIG. 1 sets forth a schematic diagram of a universal concurrent display and data communication system using one LED light beacon 14B as a concurrent component according to the present invention. This section of the present invention describes the general application of the system of the present invention in terms of communication and signaling between two computer systems using an optical channel (or link) operating in simplex mode (i.e., unidirectional data transfer). Also disclosed in this section are two designs (design one and design two) for using the present invention in a digital data transmitter and a digital data receiver. These designs are discussed below in conjunction with fig. 4, 5, 6 and 9. The following discussion related to digital communications also includes: (i) error rate; (ii) designing a protocol; and a coding scheme.

Fig. 1 shows data communication and signaling between two computers 10, 12 using an LED beacon 14B. On the transmitter side, computer 10 is coupled to an LED beacon 14B through transmitter circuitry 14A via a parallel port 18, parallel port 18 being generally associated with computer 10. An embodiment of the transmitter circuit 14A is described in detail below. In addition, computer 10 operates an executable computer program for formatting and controlling data transmission over the optical link. One or more LEDs14B may be used to emit optical signals, with the LEDs14B currently operating as a visual signaling device and a data communication component (i.e., the light emitted by the LEDs14B function as both a signaling mechanism as well as a data communication mechanism). On the receiver side, there are preferably one or more photodetectors associated with the receiver circuitry 16, and with parallel interface circuitry 18 to another computer 12, which computer 12 may be a PC, workstation, notebook, or embedded processor. Also coupled to the receiver (although not shown) is a suitable lens element for focusing the visible light from the beacon 14B to an associated photodetector or other light detecting element. The data communication signal transmitted from the LED transmitter 14B to the receiver 16 is preferably formatted into a plurality of data frames received by the computer 12, and may be unpacked and displayed on the computer.

Fig. 2 is a schematic diagram of a universal concurrent display and data communication system according to the present invention using an LED dot matrix display 22 as the concurrent component. The LED display panel 22 is used to provide visual message signals in the form of concurrent display of information, as well as data transmission. The transmission side of the system comprises two computers 10A, 10B. One of the computers 10A is used to control the data communication function of the concurrent LED display 22, while the other computer 10B controls the information display function of the LED matrix 22. These computers 10A, 10B are coupled to the LED array 22 by a suitable interface circuit 20. the interface circuit 20 may include a transmitter circuit (similar to the embodiment of 14A in fig. 1 and 14A discussed below), and may also include circuitry for controlling the display function of the array 22. As an alternative, instead of the computers 10A, 10B for controlling the lattice 22, only one computer may be used to manage both functions via the interface circuit 20. An executable computer program runs on both computers, one for controlling the data communication functions of the display and the other for visual display control of characters, decoration patterns or messages on the display panel 22.

Generally, there are two types of operating systems for IBM-compatible Personal Computers (PCs), as shown in fig. 1 and 2: DOS, Windows. DOS OS is an older type of operating system for PCs. It is characterized by its single task (i.e., non-multitasking distribution), command-driven environment, DOS OS being used for all IBM-compatible PCs before Microsoft's introduction of Windows 3.1 or 95. The first design (design one, below) of the data transmitter and receiver (no memory buffer) shown in fig. 4 and 5 is a version of the transmitter and receiver for a non-multitasking allocation environment. In the Windows95 environment, the OS has occasional interrupts for all running programs as if in a multitasking distribution environment. These interruptions will affect the data transfer process and may lose some data. There is no such problem in the DOS environment. Thus, the preferred design of the digital data transmitter and receiver of fig. 4 and 5 cannot be used in the Windows95 environment while the alternative version (design two) shown in fig. 6 and 9 is provided for the multitasking distribution environment. This second design is based on the addition of a memory buffer to the interface circuit.

Before turning back to a discussion of two designs for a data transmitter (14 or 22) and receiver (16), it is beneficial to consider several data communication aspects of the present invention, including: (i) error rate; (ii) designing a protocol; and (iii) a coding scheme.

A. Bit Error Rate (BER)

The inventors have established tests for the bit error rate ("BER") of the data universal communication system described in this application. Factors such as frame size, data rate, lighting environment, distance, and bit pattern of the data frame are varied so that the BERs under different conditions have different characteristics. The test is established using a direct line of sight between the transmitter and the receiver. These factors vary as follows: (1) oscillator frequency: 62.5kbps/125kbps/250kbps/500 kbps; (2) environment: normal/dark/interference; (3) distance: 2.5ft/3 ft; (4) signal mode: 0101./0011.; and (5) frame size: 1kbyte/2kbyte/5 kbyte.

Programs written in the C + + language facilitate the above-described testing. The program may record various combinations of conditions including average bit error rate, maximum bit error within a frame, and distribution of bit errors. Each test may use a 1 megabyte transfer of data. A combination of all the conditions with a bit rate of less than or equal to 500kbps may be used and the test may be repeated a number of times. This test makes the BER so low that it cannot be tested by existing experimental equipment. Thus, the BER of the present invention is considered acceptable.

B. Protocol design

Fig. 3 shows an example of a communication protocol suitable for data transmission over the optical link shown in fig. 1 and 2 between a transmitter (14 or 22) and a receiver (16), using which a digital data stream communicated from the transmitter to the receiver is converted into a set of data frames 30. Each frame 30 is preferably comprised of 1024 bytes, although other frame sizes may be used. In a preferred frame, there are 48 data blocks, 20 bytes each. A start byte 34 ("Stx") is added at the beginning of each data block 36. In addition, a synchronization byte 32 ("Sync") is added at the beginning and near the end of each frame 30, with two idle bytes 38 at the end of the frame.

The number of bytes used for the Sync32 should generally be longer than one data block 36 so that the receiver can distinguish between 18-byte data blocks 36 even if they have a pattern exactly equal to the Sync bytes 32. The function of the Stx bytes 34 is to indicate the start of the data block 36 and to allow the Sync bytes 32 and the data bytes 36 to be distinguished. Operationally, the receiver counts the number of Sync bytes 32. If the number of received Sync bytes 32 is greater than a certain value (e.g., greater than 25) that is greater than the size of the data block 36, the receiver may know that it is at the beginning of a frame or at the end of a frame. 32 bytes are assigned to the Sync byte 32 at the beginning of the frame and 30 bytes at the end to give some margin for counting the number of Sync bytes.

At the end two idle bytes 38 are added to separate the frames 30. These idle bytes 38 are also used to synchronize timing between the transmitter (14 or 22) and the receiver 16. When no data is transmitted, the free bytes 38 are continuously sent from the transmitter (14 or 22).

At the beginning of the data transmission, the receiver 16 will receive an idle byte 38, which is also used for synchronization. Upon receiving the Sync byte 32, the receiver 16 will stop the synchronization process and count the Sync byte 32. If the number of Sync bytes 32 reaches a certain amount (e.g., 25), the receiver processes the following bytes as a data block 36. The receiver 16 then resets the counter and counts the number of Sync bytes 32 again. If the number of Sync bytes 32 reaches a certain amount (e.g., 25), the receiver 16 will know that it is at the end of the frame 30 and then use the idle bytes 38 again for system synchronization.

It should be noted that although a particular protocol is depicted in fig. 3, this is but one example of the many types of formatting and framing that may be used with the present invention.

C. Coding scheme

The human eye is very sensitive to light intensity. In the preferred optical link between the transmitter and receiver described herein, the digital data communication process should not affect the light intensity of the LEDs, otherwise the display process of the LEDs will appear to flicker. Accordingly, an encoding scheme for maintaining a constant light intensity during normal data communication is provided. The preferred encoding scheme is to use Manchester encoding. In Manchester encoding, one data bit is mapped into two data bits. For example, data "0" is mapped as "01" with a rising edge, while data "1" is mapped as "10" with a falling edge.

There are three advantages to using Manchester encoding. Firstly, it is easy to implement. Second, it provides an additional timing signal from the transmitter to the receiver. Third, it maintains constant led brightness with a 50% duty cycle. However, this coding scheme requires two bits to represent one data bit and thus bisects the system bandwidth. Using Manchester encoding, a 1024 byte data frame as described in fig. 3 transmits only 512 bytes of actual data. Although Manchester encoding is the preferred encoding scheme of the present invention, it should be recognized that many other encoding techniques may be used and are within the scope of the present invention.

Having described the universal concurrent display and data communication system of the present invention, and several problems associated with optical data communication links, two designs for the transmitter (14 or 22) and the receiver (16) are now presented. Fig. 4 and 5 depict the first design, while fig. 6-12 depict the second design. As indicated previously, one is designed for a PC (or embedded) computer (or other non-multitasking operating system) that is preferably used to operate DOS, while the other is designed for a multitasking operating system such as Microsoft Windows. It should be noted that these two designs are merely illustrative of the types of transmitters and receivers that may be used to operate the preferred concurrent display and data communication system. Other designs are possible and within the scope of the invention.

Turning to the drawings, FIG. 4 is a block diagram of a preferred digital data transmitter 40 for use in the concurrent display and data communication system of the present invention. The design one is preferably used for operating a non-multitasking operating system PC, workstation, or embedded computer. The transmitter 40 may be coupled to the beacon LED14 shown in fig. 1, or the LED dot matrix display 22 shown in fig. 2. The preferred transmitter 40 includes: a parallel port interface 42; a data latch 44; an interface control circuit 43; a system oscillator 56; a system control circuit 50; baud rate prescaler 58; a cycle counter 54; a parallel-to-serial converter 48; and a data transmitter 46.

The parallel port of the PC (10A, 10B or 12) replaces the RS232 port (serial port) for digital data transmission. This is preferable because the RS232 protocol can change the brightness of LEDs and has a low data rate. The general function of the transmitter 40 is to convert parallel data from the PC into a serial data string of data so that it can be transmitted over the optical link between the transmitter and the receiver. Similar protocols and coding schemes as described above may also be used. In this case, the software (an executable program) running on a computer coupled to the transmitter 40 includes software instructions for formatting the data according to the selected protocol and coding scheme.

The transmitter 40 includes a system oscillator 56 that provides a high frequency signal ("SYSOSC") to a baud rate prescaler 58, the baud rate prescaler 58 being a binary counter for frequency division of the oscillator signal. The circuit 58 provides a programmable system clock frequency ("syssc") for the transmitter 40 so that the transmission rate varies based on the application and conditions under which the system is operable.

Data latch 44 receives the parallel digital signal from parallel port 42 of the PC. The data latch 44 is an octal D-type flip-flop with a 3-state output. When it receives a signal from the PC, the parallel data input to the data latch 44 is latched onto the output of the parallel-to-serial converter 48 (buffered data, 8 bits).

The loop counter 54 and system controller 50 circuitry are used to control the timing of the transmissions. Coupled to these circuits is the SysINIT signal, which is the system initialization signal from the PC. The loop counter 54 is a preset synchronous 4-bit up/down counter. Which provides a 3-bit counter S [0..2] for decoding the state by system control circuitry 50. system control circuitry 50 provides a system control function for its operation. When the signals S [0..2] from the cycle counter 54 are all zero, the transmitter clock signal TXCLK is low and latches the data on the input of the parallel-to-serial converter 48.

The GetBuff signal from the system control circuit 50 is coupled to the clock signal of the interface control circuit 43, and the interface control circuit 43 may be a J-K flip-flop. The falling edge of GetBuff transitions the state of the J-K flip-flop so that BuffCLR is low to indicate that the transmitter 40 is ready to receive data from the parallel port for transmission.

The parallel-to-serial conversion circuit 48 is for converting parallel data into serial data and is controlled by a timing signal TXCLK from a system control circuit 50, wherein the parallel-to-serial conversion circuit 48 is an 8-bit parallel input/serial output shift register.

Interface control circuit 43 is also used to generate handshake signals back to the PC. Interface control circuit 43 is a dual J-K flip-flop with a reset negative edge flip-flop. With J and K inputs connected to its own output. When data is not being transmitted, the StrData signal is 0, which clears the flip-flop so its output is 1. When StrData is set to 1 during data transmission, the output of the flip-flop is set to 0. The function of this flip-flop is therefore to provide a buffered clear signal (BuffCLR) back to the personal computer.

The interface control circuit 43 is also used to generate an error signal back to the PC. The interface control circuit 43 generates an error signal back to the PC when StrDATA is not set low after the 8-bit data byte is transferred. In this case, the system error signal (SysERR) is set to 0 and sent to the PC to indicate that there is an error of double transmission of 8-bit data (copy transmission).

After a particular 8-bit data byte is converted by converter 48 into an appropriate serial data stream, the data ("TxData") appears to data transmission circuitry 46, which data transmission circuitry 46 amplifies the serial signals for coupling to a light source (e.g., the LED beacon of fig. 1, or the dot matrix display of fig. 2).

Fig. 5 is a block diagram of a preferred digital data receiver 60 for use in the concurrent display and data communication system of the present invention. The receiver module 60 is designed such that digital data can be received using one or more photodetectors or other types of light detection devices. The receiver 60 receives the transmitted optical signal and converts the received serial data into parallel 8-bit data with appropriate timing and then transfers the data to a connected PC through its parallel port. The preferred embodiment of the digital data receiver 60 shown in fig. 5 comprises: a parallel port interface 62; a data latch 66; a data receiver 68; a serial-to-parallel converter 70; an interface control circuit 76; a sync synchronization circuit 78; a system oscillator 82; baud rate prescaler 80; a cycle count circuit 74; and a system control circuit 72. The operation of these preferred components is described below.

Receiver 60 includes a system oscillator that provides a high frequency signal ("SYSOSC") to a baud rate prescaler 80, and baud rate prescaler 80 is a binary counter for frequency division of the oscillator signal. Using these circuits 80, 82, different system clock frequencies for the receiver 60 may be selected to match the transmission rate of the associated transmitter 40.

The serial-to-parallel circuit 70 is an 8-bit serial-in/parallel-out shift register that is used to convert serial data to parallel data to the data latches 66. The serial-to-parallel circuit 70 is controlled by a timing signal RXCLK from a system control circuit 72. The data latch 66 latches the parallel digital data for the PC's parallel port 62. The data latch 66 is an octal D-type flip-flop with a 3-state output. When the PC is to get data, the signal GetDATA from the PC enables the output of the data latch 66. Then, as the signal for storing buffered data ("StrBUFF") arrives at the data latch 66, the parallel data of its input is latched to its output.

The cycle counter 74 and system controller 72 circuitry are used to control the timing of the receipt of incoming data at the receiver. The synchronization counter signal synctr from the sync synchronization circuit 78 is used for system synchronization purposes. The cycle count circuit 74 is a preset synchronous 4-bit up/down counter. Which provides a 3-bit counter S [0..2] (row 3 to 8 decoders) for decoding the state of system control circuit 72, system control circuit 50 provides a system control function for its operation.

The system control circuit 72 is a 3 to 8 row decoder. Which accepts the counter output from the cycle count circuit 74S [0..2 ]. When all of the input bits S [0..2] are high, a signal StrBUFF is sent to the data latch 66 by the system control circuit 72 to latch the data. This data is latched at 1/8 of the master clock frequency to latch the shifted data from the serial-to-parallel circuit 70 at the appropriate time. The StrBUFF signal is also sent to the interface control circuit 76, which propagates a data ready signal ("DataRDY") to the PC. If the interface control circuit 76 is unable to receive the GetDATA signal, a system error signal SysERR is sent to the PC. This indicates that there is an error in the rewriting of the input 8-bit data.

To synchronize the system clock with the received data, the PC sends a SysSYNC signal to the sync clock circuit 78. This enables the baud rate prescaler 80 and the count value of the cycle count circuit to be paused and reset by the synctr signal until the sync clock circuit 78 receives a falling edge of the input data via RXDATA. It then sends a SysLOCK signal to the PC to indicate that the system has synchronized with the incoming data.

Having described in detail the preferred design of transmitters and receivers for a non-multitasking operating system, a second design (design two) will now be described. This second design is preferably used for computers with multitasking operating systems. Fig. 6-12 depict a preferred embodiment of the design.

Fig. 6 is a block diagram of a preferred digital data transmitter 110 with a memory buffer for use in the concurrent display and data communication system of the present invention. This design (design two) is best used for computers with multitasking operating systems such as Microsoft Windows. In existing designs, the transmitter 110 is coupled to a parallel port 18 of a PC (or laptop or embedded computer) via a parallel port interface 126. A preferred embodiment of the circuit comprises: a timing control circuit 112; a handshaking circuit 114; a first address generator 116 for the transmitter; a serial input/output (5IO) circuit 118; a multiplexer 120, a dual port RAM buffer 122; and a second address generator 124 for the PC.

The transmitter is preferably designed to enable data to be transmitted through a parallel port 18 in the PC. However, in the environment of Windows95, there are periodic interrupts to the parallel port, and data is not transferred during the interrupts. Thus, a transmitter without a memory buffer during an interrupt period experiences a significant delay in transmitting data. Thus, a digital data transmitter with a memory buffer is provided so that data can be transmitted over the optical link without interruption.

Another advantage of the configuration shown in fig. 6 is that the transmitter implements certain required communication protocols in hardware. This may simplify software design and timing control of the transmitter. The computer then focuses on writing data to the memory buffer.

The dual port RAM122 serves as a memory buffer within the transmitter 110. This type of memory is used because dual port RAM allows simultaneous reading and writing of data, which also simplifies the design. Techniques for paged memory management may also be used. The dual port RAM122 is divided into two portions called memory pages. When the PC writes data to one page of memory, the transmitter is reading and sending data out of another page of memory. After the write and read from one page are complete, the memory pages are swapped, and the transmitter is reading data for transmission from the swapped page to which the PC has written the data. A serial I/O circuit 118(SIO) is used to convert parallel data from the PC into a serial data stream for transmission to the receiver.

There are also two operating conditions that should be considered in relation to the timing of data reading and writing when implementing the design shown in fig. 6. In the following description, tPC denotes the time it takes for the PC to finish writing a page, and tSIO denotes the time it takes for the SIO circuit 118 to finish reading a page. Two conditions shown in fig. 7 and 8 are described below.

Fig. 7 is a schematic representation of operating conditions associated with the digital data transmitter of fig. 6 including a serial input/output device read time lower than a PC coupled to the data transmitter, and tPC < tSIO, i.e., SIO read time lower than PC write time. As shown in FIG. 90, when the SIO118 is reading a block of data relatively slowly, the PC writes a block of data, and the PC simply waits for the SIO circuitry 118 to complete the data read and then swap the memory pages.

Fig. 8 is a schematic illustration of an operating condition associated with an alternative digital data transmitter including a serial input/output device read time that is faster than a PC coupled to the data transmitter- (2) tPC > tSIO, i.e., the SIO read time is faster than the PC write time. As shown in this figure, when a PC writes one block of data slower than the SIO118 reads one block of data, the SIO118 sends only free bytes (described previously) after the SIO118 has read and sent the block of data. After the PC has finished writing one block of data, the memory pages are then swapped for another page of transfer.

Turning to fig. 6, a block diagram of a digital data transmitter using a dual port RAM as a memory buffer is shown. Coupled to the circuit shown in fig. 6 is a parallel port interface 126. The interface connects the 8-bit data lines, four output control pins and two input control pins to the transmitter circuitry for data transfer and handshaking. An 8-bit data line represents a byte of data that is transmitted (serially) by transmitter 110. The four output control pins are referred to as # INIT, # PCstore, FrameStx, and PCNext. The two input control pins are referred to as TerPC and TerSIO.

The # INIT output control pin is used to initialize the transmitter. # PCStore is a signal indicating that data is to be written to the dual port RAM 122. The FrameStx is used to reset the address generators (address counters) of the PC and SIO124, 116. PCNext is used to increment an address counter for each 8-bit data byte. TerSIO is used to indicate whether SIO118 has finished sending out data for one memory page. And TerPC is used for indicating whether the PC has finished writing one memory page data.

The two address counters 124, 116 of the PC and SIO are preferably separate counters. These two counters are incremented by signals PCNext and INC (from timing control circuit 112) to generate the address of dual port RAM 122. These two counters are reset by the FrameStx signal from the PC. They also generate two signals called TerSIO and TerPC to indicate the end of memory access by SIO and PC, respectively.

A handshake circuit 114 is included for swapping memory pages and also determining when to select a free byte sent by SIO 118. Handshaking circuit 114 reads two signals, TerSIO and TerPC, from the two address generators and produces three outputs called PC-MSB, SIO-MSB, and SelSync. The PC-MSB is the most significant bit of the address of the dual port RAM122 on the PC side of the memory and the SIO-MSB is the most significant bit of the address of the dual port RAM122 on the SIO side of the memory. When PC-MSB is set high, SIO-MSB must be set low, and vice versa. When the handshaking circuit 114 observes that TerSIO and TerPC have been set, it transforms the state of PC-MSB and PC-SIO so that the memory pages can be swapped. In addition, handshake circuit 114 sets SelSync high when TerPC is set low after TerSI. The SelSync signal is used to select whether the SIO118 sent free bytes or dual port RAM data.

Timing control unit 112 is used to generate three signals for timing control of SIO 118. These signals are BitShift, StrBuff and INC. BitShift is a clock signal for SIO118 to shift to convert parallel data into serial output data. StrBuff is issued every 8-bit cycle so that 8 bits of data in parallel are stored in a buffer on SIO118 for transmission. And INC is used to augment address generator 116 on the SIO side of dual port memory 122. SIO118 is a shift register to shift parallel data lines to serial outputs (TxDataOutput) to drive LEDs of a concurrent display and data communication system.

Fig. 9 is a block diagram of a digital data receiver having a memory buffer in accordance with the concurrent display and data communication system of the present invention. This design is used in conjunction with a transmitter (not shown) as shown in fig. 6. The preferred receiver 150 design includes: a parallel port interface 168; a synchronization circuit 152; the SIO circuit 154; a latch 156; a dual port RAM buffer 158; an address generator 160 for the SIO side of dual port RAM buffer 158; a handshaking circuit 162; a timing control circuit 164; and an address generator 166 for the PC side of the dual port RAM buffer 158.

The design of the receiver is similar in many respects to the design of the transmitter with memory buffers shown in fig. 6, except that a synchronization circuit 152 and a Sync counter have been added. Dual port RAM158 serves as a memory buffer within the receiver, similar to the corresponding transmitter circuitry. The paged memory management techniques described above may also be used. According to this technique, the dual port RAM158 is divided into two memory pages. When the PC reads data from one page in memory, the receiver will receive and write data to another page. After completing the writing and reading of one page, the memory pages are swapped, and then the PC reads the data for transmission from the swapped page to which the receiver just written. Serial I/o (sio) circuitry 154 is used to convert serial data to parallel data in a manner opposite that used by the transmitter circuitry of fig. 6.

Several operating conditions related to the reception of idle bytes from the transmitter, as well as the source of error frames, should be considered in implementing the design shown in fig. 9. Fig. 10-12, described below, illustrate these three conditions.

Fig. 10 is a schematic illustration of operating conditions associated with the digital data receiver of fig. 9 in which no idle bytes are received. This occurs when the transmitter does not send out any idle bytes during data transmission. This also occurs when the PC of the transmitter is sending out data faster than the SIO of the transmitter can send. Fig. 10 shows the timing (130) required for the receiver to receive data in this case. The PC of the receiver will wait for another memory page to be filled by the SIO154 of the receiver. After the SIO154 has received one page, the PC starts reading data from the page that was just written by the SIO.

Fig. 11 is a schematic illustration of operating conditions associated with the digital data receiver of fig. 9 in which idle bytes are received between frames. This situation occurs when the PC of the transmitter sends out data slower than the SIO of the transmitter. Fig. 11 shows the timing required for the receiver to receive data in this case. The PC of the receiver will wait for the start of the next incoming frame. After the SIO154 has received a page start, the PC begins reading data from the page that was just written by the SIO.

The time for the receiver to receive a frame and the idle byte should be longer than the time for the PC to read a page of memory (i.e., a frame). Also, errors may occur and there is a possibility that one frame is lost. However, if the time for the PC to write to the memory page on the transmitter side is longer than the time for the PC to read out the memory page on the receiver side, it is not related to the SIO transmission rate. This feature is explained in fig. 12.

Fig. 12 is a timing diagram explaining the source of errors in a frame. As shown in the figure, the time to transmit the idle byte is based on the time Tpc Tx. If Tpc tx increases, the time for transmitting the idle byte also increases. This means that the time allowed for the receiver PC to read out the page also increases. Thus, as long as TpcRx < Tpctx, the receiver can receive all frames without errors. In practice, this can be achieved by adding some delay to the transmitter PC if the receiver PC cannot catch up with the transmission.

Turning to fig. 9, a block diagram of digital data using a dual port RAM as a memory buffer is shown. Coupled to the circuit shown in fig. 9 is a parallel port interface 168. The interface 168 includes an 8-bit data line byte, three output control pins, and three input control pins for data transfer and handshaking purposes. An 8-bit data line represents a byte of data that is transmitted (serially) by transmitter 110. The four output control pins are referred to as # INIT, # PCstore, FrameStx, and PCNext. The three input control pins are referred to as TerPC, TerSIO, and Error.

The # INIT control pin is used to initialize the transmitter. The FrameStx is used to reset the address generator 166 (address counter) on the PC side. PCNext is used to increment an address counter for each 8-bit data. TerSIO is used to indicate whether the SIO154 has completed a receive operation and stored a memory page data to dual port RAM 158. TerPC is used to indicate whether the PC has completed reading data for one page of memory. The 8-bit data lines are used for the actual data transfer.

The two address counters 166, 160 (for PC and SIO) are counters. These two counters are incremented by signals PCNext and INC to generate the address of dual port RAM 158. These two counters are reset by the FrameStx signal from the PC. They also generate two signals, TerSIO and TerPC, to indicate the end of memory access by SIO and PC, respectively.

A handshake circuit 162 for swapping memory pages also generates an Error signal (Error) to the PC. Handshaking circuit 162 reads two signals, TerSIO and TerPC, and produces three outputs called PC-MSB, SIO-MSB, and Error. The PC-MSB is the most significant bit of the address of the dual port RAM158 on the PC side and the SIO-MSB is the most significant bit of the address of the dual port RAM158 on the SIO side. When PC-MSB is set high, SIO-MSB must be set low, and vice versa. When the handshaking circuit 162 observes that TerSIO and TerPC have been set high, it transforms the state of PC-MSB and PC-SIO so that the memory pages can be swapped. In addition, handshake circuit 162 sets Error high when TerPC is set low after TerSI. The Error signal is used for the PC to alert the data frame that may be lost.

The timing control unit 164 is used to generate three signals-BitShift, StrBuff, and INC for timing control of the SIO 154. BitShift is a clock signal for SIO154 to shift to convert serial data into parallel input data. StrBuff is issued every 8 bit cycle to shift the parallel 8 bits of data stored in latches 156. And an address generator 160 for INC for adding SIO.

A synchronization circuit 152 is added to the receiver. This unit is used to synchronize the timing between the transmitter and the receiver and to count the number of Sync bytes received. Which is read out from RxData and 8-bit parallel data to generate a ValidData signal to the timing control circuit 164. When the circuit has counted enough Sync bytes, ValidData is set so that the frame is available to be written to dual port RAM 158.

Having described in detail the general system of the present invention for concurrent display and data communication using LEDs (including both types of designs for transmitters and receivers), it is to be understood that the teachings and disclosure of the system can be applied to a variety of applications. Three of these numerous applications are described in detail below-a vehicle speed limiting application, (b) a parking and guidance system application, and (c) a portable travel information and location system. However, it should be noted that this is only three possible applications in the general system described above. The principles and concepts of the general concurrent display and data communication system may be applied to a variety of other applications not specifically described.

2. Vehicle speed limiting system

Fig. 13-16 depict a vehicle speed limiting application using a concurrent display and data communication system with LEDs embedded in traffic lights, street lights, message signs, signposts, or the like as concurrent components.

The system shown in fig. 13 may include several components installed in a vehicle, such as: a visible light receiver module 190, a central processing module 196, alarm or display units 192, 194, and a vehicle speed sensor 198. The receiver module 190 may operate similarly to the two receiver designs described above for the general system. Outside the automobile, the system may include one or more concurrent sources of display and data communication information using LEDs, such as street lights 180, traffic lights 182, message signs 184, or road signs 186. Other types of concurrent display/data communication components may also be used for this application.

According to the system shown in fig. 13, visible light emitted by a traffic light 182, a street light 180, a message sign 184 or a Light Emitting Diode (LED) within a road sign 186 in a prescribed area is modulated so that a visible signal from the LED has a speed limit value. Each of these light sources includes an appropriate transmitter circuit for modulating the light source with appropriate data and powering the LEDs (similar to the general principles associated with the general system described above). In this manner, the LEDs operate as a display component (e.g., part of the traffic light 182) and a data communication component (as a speed limit for the data being communicated). A vehicle 188 moving within a defined area has a receiver module 180 for detecting modulated visible light energy emitted by each of the traffic lights 182, street lights 180, sign boards 184 or road signs 186. A receiver module 190 on the car 188 demodulates and processes the received visible signal to obtain speed limit information. The processing unit 196 performs a comparison between the vehicle speed from the odometer and the transmitted speed limit information. The in-vehicle system may also provide one or more types of warning and display units 192, 194 to signal the driver if its vehicle exceeds the transmitted speed limit information, wherein the warning and display units 192, 194 may add an audio indication. Alternatively, some incremental speed may be used to provide a warning indicator when the vehicle exceeds the transmitted speed by a predetermined amount, such as 5 miles per hour. In addition, the system also signals the vehicle control unit 210 to reduce the vehicle speed to match the speed limit. In this way, the system is fully closed loop.

Fig. 14 is a diagram of a visible LED transmitter 200 associated with the application shown in fig. 13. The transmitter 200 may be mounted near the concurrent display components 180, 182, 184, or 186, or may be placed in some location, such as at the bottom of a light pole or in some auxiliary electronics housing. The circuit includes a control circuit ("MCU") 202, a plurality of driver circuits 204, and one or more LEDs 206 connected to each driver circuit 204. The MCU202 packs the appropriate vehicle speed limit data into appropriate data blocks according to the particular data protocol. Examples of coding and protocol schemes for a general system are described above. The data is then used to drive the LED array 206. The data block from MCU202 includes a sync byte that triggers in-vehicle receiver module 190. Error correction coding techniques may also be used. Driver/buffer circuit 204 provides sufficient current to drive a set of series-connected LEDs 206, although in this alternative there may be one driver for each LED 206. Driver 204 and LEDs 206 are repeatedly arranged to form the desired LED array size. It should be noted that the above teachings and principles with respect to general transmitter and receiver design, as well as the discussed encoding techniques, data communication protocols, etc., may be used for any of the applications described herein.

Fig. 15 is a block diagram of an in-vehicle system related to the vehicle speed limit application of fig. 13. The in-vehicle system may include a central processing module 196, visible light emitter module 190, vehicle speed module 198, alarm unit 192, and display unit 194. The central processing module 196 preferably controls the other modules. Which receives data from the visible light transmitter module 190 and the vehicle speed module 198. The purpose of the vehicle speed module 198 is to determine the current speed of the vehicle. The reading may be derived from sensor data, such as from an odometer. The sensor data is transmitted to the central microprocessor 196 via a serial interface. Data from the vehicle speed module 198 and the visible light emitter module 190 is processed by the central processing module 196 and outputs appropriate information to the display 194 and alarm 192 units. Also shown is an optional vehicle control unit 210 coupled to the central processing unit 196 for automatically adjusting the speed of the vehicle to coincide with the transmitted speed limit. In this manner, the in-vehicle system acts as a closed-loop remote-actuated control system that prevents the vehicle from exceeding the calibrated speed limit.

Fig. 16 is a block diagram of a visible light receiver module associated with the automotive system shown in fig. 15. It should be noted that the teachings and disclosure of the two receiver design of the general system can also be applied to the design shown in fig. 16. As shown, the receiver module 220 may include a light detection sensor 222 (e.g., a photodetector, photodiode array, CCD, etc.), a differential amplifier 224, positive pulse detector 226 and negative pulse detector 228, and data recovery circuitry 230. The light detection sensor 222 detects visible light energy and converts it to a voltage proportional to the received light intensity. The differential amplifier 224 is used to reduce the effects of 50Hz noise introduced by fluorescence, which is located near the system. The differential amplifier 224 amplifies high frequency signals such as high to low or low to high. The output of the differential amplifier 224 includes positive and negative pulses. These pulses are separated by positive and negative pulse detectors 226, 228 and fed back to a data recovery circuit 230. The data recovery circuit 230 includes an SR flip-flop that can combine positive and negative pulses to form a received data stream. The central processing module 196 then extracts the transmitted speed information from the data stream.

3. Automotive position and guidance system applications

FIG. 17 is a diagram of an automotive location and guidance system application of the concurrent display and data communication system of the present invention using LEDs in traffic lights, street lights, message signs, road signs, or similar devices. In many respects, the system is similar to the vehicle speed limiting system described above, except that the information sent by the concurrency component 180, 182, 184, or 186 is not vehicle speed information, but is information relating to the location of the automobile and its surrounding geographical and traffic conditions.

In this system, a car 188 moving over a defined area includes means 190 for detecting modulated visible light energy emitted by each of the traffic lights 182, street lights 180, sign 184 or road signs 186. A positioning system 240 on the vehicle, such as a stop reckoning system with a digital compass, detects the distance traveled and the direction of travel by the vehicle. The receiver 190 on the car 188 demodulates and processes the received signals from the concurrent light sources and then uses the received position information to calibrate the positioning system 240 within the car 188. The position, guidance and traffic information are displayed by the display device 242 and audio signals are also given via a loudspeaker. Display device 242 may include a graphical interface for displaying map information, location information, traffic data, traffic light status, and distances to various service locations, such as gas stations, hospitals, or parking lots, to name a few.

Fig. 17 shows an example of an in-vehicle visual and audio unit 242. Although other types of indicating devices may be used which show the car position on the street map by means of a horizontal or vertical line. On the right side of the display is an information area. In this area, traffic signals, directions, location and message information are displayed. For the audio unit, a speaker may output audio information to guide the driver. For example, referring to FIG. 17, an automobile is at the junction of the Bonham and Pokfula roads. The traffic light is green. To reach the nearest hospital, the driver must turn left and drive 1.5 km. The building is located nearby and the message sign outputs a message "road guide" to the driver. The audio unit tells the driver to pass the traffic lights and the location of the car.

FIG. 18 is a block diagram of inertial positioning module 240 in connection with the system application shown in FIG. 17. The module 240 includes an accelerometer 252, a gyroscope 250, an odometer 254, a digital compass 262, an a/D converter 260 coupled to the accelerometer 252 and the gyroscope 250, a control unit 256, and a serial interface unit 258. The location module 240 determines the distance traveled by the vehicle and the angle of the turn. Sensor data from the accelerometer 252, gyroscope 250, odometer 254 and digital compass 262 are transmitted to the central processing system 196 of the vehicle. The accumulated drift error displayed by the inertial sensor is corrected by the positioning information sent by the traffic light, the street lamp, the message display board or the road sign.

The location module may contain four different sensors, including an odometer 254, an accelerometer 252, a gyroscope 250, and a digital compass 262, although not all of these sensors are required. The odometer 254 measures the number of revolutions the wheel has rotated. The distance traveled by the vehicle is then calculated by counting the number of revolutions represented as electrical pulses. The accelerometer 252 measures the acceleration forces that the vehicle has. The distance covered by the vehicle is then calculated by integrating the acceleration and integrating the resulting velocity. The gyroscope 250 measures the angular velocity at which the vehicle is turning. The angle through which the vehicle is turned is then calculated by integrating the measured angular velocity. The digital compass 262 is used to measure the direction of the car relative to true north. The design of each sensor interface is similar. Each positioning sensor is connected to a controller unit 256 which controls the sensor and performs calculations. The sensor data is then transmitted to the central microprocessor 196 through the serial interface 258.

4. Portable travel information and location system applications

FIG. 19 is a diagram of a portable travel information system application of the concurrent display and data communication system of the present invention. The system is similar in many respects to that described above with respect to in-vehicle applications, except that the information sent by the concurrency components 180, 182, 184 and 186 within the application is received by a portable unit 290 carried by the traveler (or other mobile body), where the portable unit 290 can also send information back to the light sources 180, 182, 184 and 186. The concurrency component can include a receiver component 270 for receiving data transmissions from the portable unit 290. In this manner, a bi-directional concurrent display and data communication system is provided.

In the system shown in fig. 19, the visible light emitted by the Light Emitting Diodes (LEDs) on the traffic lights 182, street lights 180, message signs 184 or road signs 186 (or similar devices) in a defined area is modulated so that the visible signal carries location, local area maps, public transportation stations, major attractions/buildings in adjacent areas and/or guidance information or other types of information or data. The traffic light 182, street light 180, message display sign 184 or signpost 186 may also include means 270 for receiving a traveler request signal. The traveler or hiker has a portable information and location system 290 that includes means for receiving modulated information from concurrent display/data communication components (180, 182, 184, 186) and transmitting the information back to the receiver 270 associated with those components. The location, travel and directions information may be displayed by the display device 272 as part of the portable system 290, and the location, travel and directions information may also be represented as audio signals by the incorporated speaker 280. The display device 272 may include a map of location display 278 with crosshairs indicating the traveler, an information interface 274 for displaying an information selection menu to the traveler, a location interface 276 for displaying a location selection menu to the traveler, a selection button 282, and a scroll button 284 for moving through the interface menu. Other components may also be provided within the interface.

Fig. 20 is a block diagram of a preferred portable travel information and location unit 290. The unit 290 may include a visible light receiver module 298, a transmitter module 292, a central processing module 294, visible and audio units 272, 280, and a user input module 296. The receiver module 298 receives modulated visible light energy from the concurrent display/data communication components and demodulates it to obtain information. The information is then processed by a central processing module 294, which module 294 determines the content of the information displayed or presented, and how the information is to be displayed. The central processing module 294 includes a microprocessor system that controls the other modules and also performs data transfers. The traveler commands the portable module 290 using the user input module 296. The user input module may provide manual input such as a selection button 282 or a scroll key 284, or alternatively a language recognition module, so that the traveler can use voice commands to instruct the unit. Other types of input devices are also possible.

The input commands are communicated from the central processing module 294 to the transmitter module 292. The transmitter module 292 transmits the user request signal to the receiver unit 270 associated with the traffic light 182, the street light 180, the message sign 184, or the road sign 186. In this manner, an interactive travel and directions system is provided in which a traveler can select the content of information downloaded from a concurrent display/data communication system.

Fig. 19 shows an example of the operation of the portable travel information system. The location of the traveler or hiker is displayed in a cross-hair on the local street map at the user interface 272. Local street maps are downloaded from concurrent components (180, 182, 184, 186). These components may be connected to other components via a network 286 and/or provide requested information to the traveler's computer system.

To the right of the user interface are an information selection area 274 and a location information area 276. In these areas, the traveler may select the information content downloaded from the concurrent component. In this example, if 'restaurant' is selected, corresponding information about nearby restaurants is downloaded. The locations of these nearby restaurants are then displayed on a map and a pop-up menu within the information area also provides certain incoming restaurants. Other information that is transmitted includes hospital, police, shopping mall, commercial center, airline office, taxi station, subway station, or airport bus information, to name a few. The traveler may enter his destination into the portable module 290 before starting the trip. If the destination is contained within the module, information of the destination will be displayed on the local map. Further, an optimal route may be calculated and displayed on a map. A voice signal may be given through the system if the traveler is in the vicinity of the destination.

FIG. 21 is a schematic diagram of an exemplary user interface for the portable travel information and location unit 290 shown in FIG. 20. In the information area 274, the user can select information that the user wants to view, such as "hospital", "police", "restaurants", etc., assuming, for example, that the traveler is to find a restaurant that has dinner. He may approach nearby traffic lights, street lights, message signs or road signs coupled to the system. He can then select 'restaurant' within the information menu. A pop-up menu 274A will be displayed in the information area. From here he can select the type of restaurant he wants to go, e.g. a chinese restaurant. Another pop-up menu 274B then appears. From here, it can select the restaurant level of its consumption. Then, a list 274C of nearby restaurants that meet their needs is displayed. Finally, he can view the information of the restaurant in the list 274D. In the same manner, each information selection may include an additional set of pop-up menus within the information area to further refine the traveler's search for relevant information.

The preferred embodiments and several applications of the invention described above are given by way of example only and are not intended to limit the scope of the invention, which is defined by the claims. Other components and steps may be substituted for those shown. In addition, many other applications of a universal concurrent display and data communication system are possible and within the scope of the present invention.

Claims

1. A concurrent signaling and data communication system, comprising:

a data display and communication system;

a data receiving system; and

one or more LEDs coupled to the data display and communication system for emitting a visual display signal and a modulated data communication signal.

2. The system of claim 1, wherein the data display and communication system comprises:

a first computer;

a data transmitter circuit and one or more LEDs coupled to the first computer; and

a data communications computer program for generating a digital data signal for execution on a first computer.

3. The system of claim 2, wherein the data display and communication system further comprises a data display computer program running on the first computer for controlling the generation of the visual display signal.

4. The system of claim 2, wherein the data display and communication system further comprises:

a second computer; and

a data display computer program running on the second computer for controlling the generation of the visual display signal.

5. The system of claim 1, wherein the data receiving system receives a modulated data communication signal emitted by one or more LEDs.

6. The system of claim 5, wherein the data receiving system comprises:

a light detecting section;

a data receiver circuit coupled to the light detection element; and

a receiving computer system coupled to the data receiving circuit.

7. The system of claim 6, further comprising a lens for receiving the modulated data communication signal from the one or more LEDs and for focusing the modulated data communication signal to the light detection component.

8. The system of claim 6, wherein the light detection component is a photodetector.

9. The system of claim 1, wherein the one or more LEDs are configured as a two-dimensional dot matrix display.

10. The system of claim 6, further comprising a data communication computer program running on the receiving computer system for controlling the reception of the modulated data communication signal.

11. A system as recited in claim 2, wherein the data transmitter circuit is coupled to the first computer via a parallel interface.

12. The system of claim 9, wherein the dot matrix display produces visual display signals comprising character, word, image, graphic or embellishment patterns.

13. A system as claimed in claim 2, wherein the data transmitter circuit comprises a modulation circuit for generating a modulated digital data signal from a digital data signal generated by a data communications computer program running on the first computer.

14. The system of claim 13, wherein the data transmitter circuit applies the modulated digital data signal to the one or more LEDs.

15. The system of claim 14, wherein the modulated digital data signal emitted by the LED is at a high frequency so that the LED appears as constant illumination to the human eye.

16. The system of claim 6, wherein the data receiving circuit includes means for demodulating the modulated digital data signal.

17. The system of claim 2, wherein the first computer runs a non-multitasking operating system.

18. The system of claim 2, wherein the first computer runs a multitasking operating system.

19. The system of claim 1, wherein the modulated digital data signal is formatted into a plurality of data frames.

20. The system of claim 20, wherein each data frame comprises:

starting a frame synchronization byte;

a plurality of start bytes and data bytes; and

the frame sync byte is ended.

21. The system of claim 20, wherein each data frame further comprises an idle byte.

22. The system of claim 1, wherein the digital data signal is modulated using manchester encoding.

23. The system of claim 2, wherein the data transmitter circuit comprises:

a parallel port interface for receiving digital data signals from a first computer;

a parallel-to-serial converter for converting the digital data signal into a serial data stream; and

a modulation control circuit coupled to the parallel-to-serial converter for controlling a clock rate of the converter to produce a modulated digital data signal.

24. The system of claim 23, wherein the modulation control circuitry comprises:

a system oscillator; and

a baud rate prescaler coupled to the system oscillator for generating a selectable modulation frequency of the clocked parallel to serial converter.

25. The system of claim 23, wherein the data transmitter circuit further comprises a data latch coupled between the parallel port and the parallel-to-serial converter.

26. The system of claim 6, wherein the data receiver circuitry comprises:

a serial-to-parallel converter for converting the modulated digital data signal into a serial data stream;

a demodulation control circuit coupled to the serial-to-parallel converter for controlling a clock rate of the converter to recover the digital data signal; and

a parallel port interface for coupling the recovered digital data signal to a receiving computer system.

27. The system of claim 26, wherein the demodulation control circuit comprises:

a system oscillator; and

a baud rate prescaler coupled to the system oscillator for generating a selectable demodulation frequency of the clocked serial to parallel converter.

28. The system of claim 26, wherein the data receiver circuit further comprises a data latch coupled between the parallel port and the serial-to-parallel converter.

29. The system of claim 27, wherein the data receiver circuit further comprises a clock synchronization circuit for ensuring that the demodulation frequency matches the modulation frequency of the received modulated digital data signal.

30. The system of claim 2, wherein the data transmitter circuit comprises:

a serial input/output (SIO) circuit for converting a parallel digital data signal to a serial modulated digital data signal; and

a memory buffer coupled between the parallel port interface and the SIO circuit.

31. The system of claim 30, wherein the memory buffer is a dual port RAM.

32. A system as in claim 31, wherein the data transmitter circuit further comprises a pair of address generators for each port of the dual port RAM.

33. A system as recited in claim 30, wherein the data transmitter circuit further comprises a timing control circuit for controlling the modulation frequency of the SIO circuit.

34. The system of claim 6, wherein the data transmitter circuit comprises:

a serial input/output (SIO) circuit for converting a received modulated digital data signal into a demodulated parallel digital data signal;

a parallel port interface for coupling the demodulated digital data signals to a receiving computer system; and

35. The system of claim 34, wherein the memory buffer is a dual port RAM.

36. The system of claim 35, wherein the data receiver circuit further comprises a pair of address generators for each port of the dual port RAM.

37. The system of claim 34, wherein the data receiver circuit further comprises a timing control circuit for controlling a demodulation frequency of the SIO circuit.

38. A vehicle speed limiting system comprising:

a concurrent display and data communication section operating simultaneously as a visual display section and a data communication section, wherein the data transmitted by the concurrent display and data communication section is vehicle speed limit data; and

and an in-vehicle data processing receiver for receiving the transmitted vehicle speed limit data from the concurrent display and data communication section and processing the received data.

39. The system of claim 38, wherein the concurrent display and data communication means is a street light, a traffic light, a message sign or a road sign.

40. The system of claim 38, wherein the concurrent display and data communication component comprises one or more LEDs.

41. The system of claim 40, wherein the LED emits a modulated digital signal with vehicle speed limit data.

42. The system of claim 38, wherein the in-vehicle data processing receiver comprises:

a visible light receiver module for receiving vehicle speed limit data transmitted by the concurrent display and data communication component; and

and the central processing module is coupled to the visible light receiver module and is used for processing the vehicle speed limit data.

43. The system of claim 42, wherein the vehicle speed limit data comprises a modulated digital data signal, and wherein the visible light receiver module includes means for demodulating the modulated digital data signal to recover the vehicle speed limit data.

44. A system as in claim 42, wherein the in-vehicle data processing receiver further comprises a vehicle speed module for providing a current speed of the vehicle.

45. A system as claimed in claim 44, wherein the central processing module compares the transmitted speed limit data with the current speed of the vehicle and generates an alarm signal if the current speed of the vehicle is greater than the transmitted speed limit data.

46. A system according to claim 45, wherein the in-vehicle data processing receiver further comprises an alarm or display unit coupled to the alarm signal generated by the central processing module for alerting a driver of the vehicle that the current speed of the vehicle exceeds the transmitted speed limit data.

47. A system according to claim 45, wherein the in-vehicle data processing receiver further comprises a vehicle control unit for automatically adjusting the vehicle speed if the current speed of the vehicle exceeds the transmitted speed limit data.

48. The system of claim 42, wherein the visible light receiver module comprises:

a light detecting sensor; and

a data recovery circuit coupled to the sensor for demodulating the signal received by the light detecting sensor.

49. The system of claim 48, wherein the visible light receiver module further comprises a differential amplifier and a positive-negative pulse detector coupled between the light detection sensor and the data recovery circuit.

50. An automobile positioning and guidance system comprising:

a concurrent display and data communication component operating simultaneously as a visual display component and a data communication component, wherein data transmitted by the concurrent display and data communication component comprises location and guidance data; and

an in-vehicle data processing receiver includes a central processing unit, a visible light receiver module, and a positioning module for receiving transmitted location and guidance information from the concurrent display and data communication component and processing the received data.

51. The system of claim 50, wherein the location and guidance information comprises positioning information, traffic information, map information, road conditions, traffic signal status, or directions to nearby facilities.

52. The system of claim 50, wherein the in-vehicle data processing receiver further comprises a visual and audio display unit for displaying information transmitted by the concurrent display and data communication component.

53. The system of claim 52, wherein the visual and audio display unit provides a local street map representing the current location of the vehicle.

54. The system of claim 52, wherein the visual and audio display unit provides speakers for providing directions for the driver's audio.

55. The system of claim 52, wherein the visual and audio display unit provides a display of the current status of nearby traffic lights.

56. The system of claim 52, wherein the visual and audio display unit provides a display of directions to nearby facilities.

57. The system of claim 50, wherein the central processing module receives the position and location information transmitted by the concurrent display and data communication component and uses the information to calibrate the location module.

58. A system as claimed in claim 50, wherein the in-vehicle location module comprises one or more inertial sensors, such as an accelerometer, gyroscope, odometer or digital compass.

59. The system of claim 50, wherein the positioning module comprises an accelerometer, an analog-to-digital converter, a controller and a serial interface to the central processing module.

60. The system of claim 58, wherein the inertial sensor drift times out, and wherein the drift is corrected by the central processing module based on the position and guidance information sent by the concurrent display and data communication component.

61. A portable travel information and location system comprising:

concurrent display and data communication means operating simultaneously as visual display means and data communication means; and

a portable travel information system for receiving the transmitted data from the concurrent display and data communication component and displaying the data to a user of the portable travel information system.

62. The system of claim 61 wherein the concurrent display and data communication means comprises a receiver for receiving information transmitted by the portable travel information system.

63. The system of claim 61, further comprising a plurality of concurrent display and data communication components coupled to each other by a network.

64. The system of claim 61, wherein the concurrent display and data communication component comprises one or more LEDs for emitting modulated digital data signals.

65. The system of claim 64 wherein the portable travel information system includes a receiver for receiving the modulated digital data signal and means for demodulating the modulated signal to recover the digital data signal.

66. The system of claim 61, wherein the portable travel information system comprises:

a visible light receiver module;

a central processing unit;

a user input module;

a display unit;

an audio unit; and

a transmitter module.

67. The system of claim 61 wherein the portable travel information system includes a graphical user interface for displaying information to a user of the system.

68. The system of claim 66, wherein the display unit provides a graphical display of information received from the concurrent display and data communication component via the visible light receiver module.

69. The system of claim 67, wherein the graphical user interface includes a map representing a current location of a user of the system.

70. The system of claim 67, wherein the graphical user interface comprises a plurality of pop-up menus describing facilities in the vicinity of the system user location.