HK1040796B - Photo sensor array and method for manufacturing the same - Google Patents

Description

Photosensor array and method of manufacturing the same

The present application is based on and claims priority from prior Japanese patent application Nos. 2000-110718, filed 4-12-2000 and 2000-152828, filed 5-24-2000, both of which are incorporated herein by reference in their entirety.

Technical Field

The present invention relates to a photosensor array and a method of manufacturing the photosensor array, and particularly relates to a photosensor array and a method of manufacturing the photosensor array, which are constituted by arranging photoelectric conversion elements (photosensors) formed of thin film transistors in a two-dimensional form, each having a double gate structure in which a top gate electrode and a bottom gate electrode are provided above and below a common semiconductor layer.

Conventionally, as a two-dimensional image reading apparatus for reading a printed matter, a photo disc, a fine irregular form along a fingerprint, an apparatus having a photosensor array structure is provided, in which a photosensor array is constituted by arranging photoelectric conversion elements (photosensors) in a matrix-like arrangement. A solid-state imaging device such as a CCD (charge coupled device) or the like is generally used as the photosensor array.

As is well known, a CCD has a structure in which photosensors such as photodiodes, transistors, and the like are arranged in a matrix-like configuration, and the amount of electron-hole pairs (charge amount) generated corresponding to the amount of light applied to a light receiving portion of each photosensor is detected using a horizontal scanning circuit and a vertical scanning circuit to detect the applied light brightness.

In a photosensor system using such a CCD, since it is necessary to separately provide a selection transistor which sets each scanned photosensor in a selected state, there is a problem in that the size of the system itself becomes large as the number of pixels increases.

In the photosensor system applied to the above-described two-dimensional image reading apparatus, the pad portion is arranged around the array region in which the photosensors are arranged in a matrix-like arrangement. Some photosensors are connected through the disk portion to peripheral devices such as drivers that drive the photosensor array. Here, each of the photosensors having a TFT structure constituting the photosensor array has a structure in which a source electrode and a drain electrode and a gate electrode are provided with respect to a semiconductor layer provided on a glass substrate, for example. There is a problem in that since the sectional structure must have a laminated structure and the sectional structures fabricated at the array region and the disk portion are different and the respective fabrication processes are performed, the formation and patterning steps of the conductive layer and the insulating layer are significantly increased, resulting in an increase in fabrication cost and time.

Also, in the stacked structure of the photosensor array, there is a problem in that a difference between the conductive layer formed on the lower layer and the conductive layer formed on the upper layer is generated in a step for connecting a pad portion (the pad portion) of the peripheral circuit, with the result that the connection with the peripheral circuit may be damaged. Further, there is also a problem in that the conductive layer formed on the upper layer becomes more susceptible to the step generated by the lower conductive layer, and the risk of disconnection increases.

Disclosure of Invention

It is an object of the present invention to provide a photosensor array and a method of manufacturing a photosensor array that tends to improve the connection between the photosensor array and peripheral circuits and suppress disconnection of the conductive layer while reducing the manufacturing process.

A photosensor array according to a first aspect of the present invention includes:

a plurality of photoelectric conversion elements arranged apart from each other in a predetermined direction, each photoelectric conversion element including:

a semiconductor layer having an incident active region on which excitation light is incident;

source-drain electrodes provided at both ends of the semiconductor layer, respectively;

a first gate electrode provided below the semiconductor layer through the first gate insulating film; and

a second gate electrode provided over the semiconductor layer through a second gate insulating film;

a source terminal connected to a source of the photoelectric conversion element;

a drain terminal connected to a drain of the photoelectric conversion element;

a first gate terminal connected to a first gate of the photoelectric conversion element; and

a second gate terminal connected to a second gate of the photoelectric conversion element,

the second gate electrode provided in the photoelectric conversion element is composed of a first transparent electrode layer, and

at least one of the source terminal, the drain terminal, and the first gate terminal has a first transparent electrode layer. .

According to the first aspect of the present invention, any one of the source terminal, the drain terminal, the first gate terminal, and the second gate terminal has a stacked structure including a transparent electrode layer constituting the first gate or the second gate. Therefore, a good electrical connection state with the peripheral circuit can be achieved while reducing the sheet resistance that allows thick formation of each terminal structure and eliminating failure (failure) of the terminal configuration. In particular, when the transparent electrode layer is made of ITO, the connection with the peripheral circuit is improved as compared with the case of a metal terminal instead of ITO.

The uppermost layer of at least any one of the source terminal, the drain terminal, and the first gate terminal may be formed of a first transparent electrode layer. Therefore, each terminal can be formed in the laminated layer by using the same material and process as those of the electrode layer formed on the incident face of the excitation light with respect to the semiconductor layer.

Here, the photosensor array includes electrostatic discharge and contact sensing electrodes provided through an insulating film over the photoelectric conversion terminals. When at least any one of the source terminal, the drain terminal, the first gate terminal, and the second gate terminal is configured with the second transparent electrode layer configuring the electrostatic discharge and contact sensing electrode, it is possible to prevent an operation failure and an electrostatic breakdown of a circuit such as a driver which is in contact with an electrostatically charged finger. Thus, the driving of the photosensor array can be automatically started.

Also, the semiconductor layer may be enlarged or provided to serve as at least a lower layer of the source and drain electrodes, the source and drain terminals, and the source-drain wiring. Therefore, the laminated structure of each terminal portion can be made thick, and the arrangement failure of the terminals can be further suppressed, and the connection with the peripheral circuit can be further improved. In addition, steps generated on the conductive layer, such as an insulating layer provided on a layer higher than the semiconductor layer, a second gate electrode, and the like, can be reduced (insulated), so that deterioration in signal transmission performance and insulating performance can be suppressed.

Further, the plurality of photoelectric conversion elements having the above-described structure are connected via terminals to predetermined peripheral circuits such as the drain driver, the first gate driver, the second gate driver, and the like, so that a photosensor system having good insulation performance, signal transmission performance, and connection can be manufactured with a simple manufacturing process.

Also, the active region between the source and drain electrodes of the semiconductor layer on which the excitation light is incident may be configured to easily satisfy a predetermined arrangement ratio, so that the incident active region may be arbitrarily arranged to improve the deviation of the light sensing region. As a result, since the incident active region of the semiconductor layer can be set to be able to provide an optimum configuration ratio, a sufficient source-drain current is allowed to flow even when the incident light of the excitation light is very small. Good light sensitivity can be obtained.

With this photosensor array, the source electrodes of the semiconductor layers are connected to each other, the drain electrodes of the semiconductor layers are connected to each other, and the source electrode or the drain electrode can be formed over two adjacent semiconductor layers other than these semiconductor layers.

In addition, the semiconductor layers of the photoelectric conversion element may be arranged along the direction of the channel length of the semiconductor layers.

Further, when the photoelectric conversion elements are arranged in a triangular configuration, the distance between the photoelectric conversion elements adjacent to each other in two dimensions can be made more uniform. It is therefore possible to suppress deviation of optical information due to unevenness of light reception sensitivity, which differs according to the direction, when the same subject to be photographed is placed at different angles with respect to the plane of the photosensor array. The restriction on the angle at which the object is placed becomes small, so that a photosensor array having superiority in image reading performance can be realized.

A method of manufacturing a photosensor array according to a second embodiment of the present invention includes:

forming a first gate electrode on the insulating film and forming a first gate base pad connected to the first gate electrode on the gate terminal portion;

forming a first gate insulating film at least on the first gate electrode and the first gate terminal portion, followed by forming a semiconductor layer having a predetermined configuration over the first gate electrode, the semiconductor layer being for generating carriers with excitation light;

forming a first opening portion for exposing the first gate substrate pad to the first gate terminal portion;

forming source-drain electrodes provided at both ends of the semiconductor layer, respectively, a drain base pad connected to the drain electrode on the drain terminal portion, and a first gate terminal lower layer on the first gate portion via the first opening portion;

forming a second insulating film at least on the first gate terminal lower layer, the source-drain and drain terminal portions, followed by forming a second opening portion for exposing at least one of the first gate terminal lower layer and the drain substrate pad; and is

A second gate electrode having a predetermined configuration and a second gate substrate connected to the second gate electrode are formed, a second gate terminal portion is formed over the semiconductor layer, and at the same time, at least one of a first gate terminal upper layer connected to the first gate terminal lower layer and a drain terminal upper layer connected to the drain substrate pad is formed through the second opening portion.

According to this manufacturing method, since the electrode layer constituting any one of the first gate terminal and the drain terminal is laminated and formed using the same material and the same step as those of the conductive layer constituting the photoelectric conversion element of the photosensor array, each structure of the entire photosensor array can be constituted and processed in a common series of manufacturing processes. Efforts may therefore be made to reduce the manufacturing process and to reduce manufacturing costs and time. Meanwhile, an electrode layer constituting any one of the first gate terminal and the drain terminal may be made thick as desired and the sheet resistance of the terminal may be reduced.

In addition, on the protective insulating film, the electrostatic discharge and contact sensing electrode, the uppermost layer of the first gate terminal or the uppermost layer of the drain terminal, or the upper layer of the second gate terminal can be formed in the same process. This can prevent an operation failure and an electrostatic breakdown of the photoelectric conversion element due to the discharge of the object without increasing the manufacturing process. In addition, the connection with the peripheral circuit can be further improved by making the laminated structure of each terminal thick.

Further, in addition to the stacked structure constituting the drain terminal, the first gate terminal, and the second gate terminal, at least the conductive layer constituting the uppermost layer may be constituted by a transparent electrode layer. This makes it possible to form a lamination of each terminal by using the same material and the same process as those of the electrode layer formed on the incident face of the excitation light with respect to the semiconductor layer without increasing the manufacturing process.

Also, the semiconductor layer may be enlarged and provided on the lower layer of the source-drain, the source-drain terminal, and the source-drain arrangement. Therefore, the laminated structure of each terminal portion can be made thicker, the sheet resistance is reduced, the configuration failure of the terminal is suppressed, and the connection with the peripheral circuit can be further improved. In addition, steps generated on an insulating layer or a conductive layer provided on an upper layer higher than the semiconductor layer, such as the second gate electrode, can be reduced, so that a photosensor array in which deterioration of insulating properties and signal transmission properties can be suppressed can be provided with a simple manufacturing process.

Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate presently preferred embodiments of the invention and, together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.

Drawings

Fig. 1A and 1B show a cross-sectional view and a circuit diagram of a basic structure of a double gate type photosensor array applied to the present invention.

Fig. 2 is a schematic structural view showing a photosensor system equipped with a photosensor array formed by two-dimensionally arranging double gate type photosensors applied to the present invention.

Fig. 3 is a timing chart showing an example of a drive control method of the photosensor system.

Fig. 4 is a conceptual diagram illustrating a reset operation of the double-gate type photosensor.

Fig. 5 is a conceptual diagram illustrating a light accumulation operation of the double gate type photosensor.

Fig. 6 is a conceptual diagram illustrating a precharge operation of the dual gate type photosensor.

Fig. 7 is a conceptual diagram showing a selected state at the time of lighting of the double-gate photosensor.

Fig. 8 is a conceptual diagram showing a selected state at the dark light time of the double-gate photosensor.

Fig. 9 is a conceptual diagram showing an unselected state at the time of lighting of the double-gate type photosensor.

Fig. 10 is a conceptual diagram showing an unselected state at the dark light time of the double-gate type photosensor.

Fig. 11 is a graph showing the light response characteristics of the output voltage of the photosensor system in the selection mode.

Fig. 12 is a graph showing the optical response characteristics of the output voltage of the photosensor system in the unselected mode.

Fig. 13 is a sectional view showing an essential part of a reading apparatus for reading a two-dimensional image, in which a photosensor system equipped with a dual gate photosensor is provided.

Fig. 14 is a sectional view showing a part of one configuration example in the photosensor array according to the present invention.

Fig. 15 is a sectional view showing a part of another configuration example in the photosensor array according to the present invention.

Fig. 16A to 16C are sectional views for explaining first to third steps in a method of manufacturing a photosensor array having the structure shown in fig. 15.

Fig. 17A and 17B are sectional views for explaining the fourth step and the fifth step in the method of manufacturing the photosensor array having the structure shown in fig. 15.

Fig. 18A and 18B are sectional views for explaining the sixth step and the seventh step in the method of manufacturing the photosensor array having the structure shown in fig. 15.

Fig. 19A is a view showing an incident active region of a double gate type photosensor in which each device shown in fig. 14 is provided with a semiconductor layer constituting a photosensor portion.

Fig. 19B is a diagram showing an arrangement structure in a photosensor array in which the photosensors shown in fig. 19A are arranged in a matrix configuration.

Fig. 20 is a conceptual diagram showing the expansion of the light-sensing area in the structure shown in fig. 19A.

Fig. 21A is a view showing an incident active region of a double gate type photosensor in which each device shown in fig. 15 is provided with two semiconductor layers constituting a photosensor section.

Fig. 21B is a diagram showing an arrangement structure in a photosensor array in which the photosensors shown in fig. 21A are arranged in a matrix configuration.

Fig. 22 is a conceptual diagram showing the expansion of the light-sensing area in the structure shown in fig. 21A.

Fig. 23 is a sectional view showing a part of a photosensor array according to a second embodiment of the present invention.

Fig. 24 is a schematic structural view showing one example of a photosensor system equipped with the photosensor system shown in fig. 23.

Fig. 25 is a partial cross-sectional view showing whether or not reflected light is incident on the semiconductor layer of the photosensor.

Fig. 26 is a schematic circuit diagram showing electrostatic discharge and contact between the sensing electrode and the CMOS inverter when a finger is not allowed to touch therein.

Fig. 27 is a schematic circuit diagram showing electrostatic discharge and contact between the sensing electrode and the CMOS inverter when a finger is allowed to touch therein.

Fig. 28 is a circuit diagram showing a touch detector.

Fig. 29A is an output waveform diagram of the signal Pa, fig. 29B is an output waveform diagram of the signal Pb when the finger is not allowed to contact the electrostatic discharge and contact sensing electrode, fig. 29C is an output waveform diagram of the signal Pb when the finger is allowed to contact the electrostatic discharge and contact sensing electrode, and fig. 29D is an output waveform diagram of the signal Pc.

Fig. 30 is a circuit diagram showing the determination signal generator and the judgment circuit.

Fig. 31A is an output waveform diagram of the signal Ps, fig. 31B is an output waveform diagram of the signal Pa, fig. 31C is an output waveform diagram of the clock signal Pb, fig. 31D is an output waveform diagram of the signal Pb when the finger is not allowed to contact the electrostatic discharge and contact sensing electrode, and fig. 31E is an output waveform diagram of the signal Pe output to the counter.

Fig. 32A is an output waveform diagram of the signal Ps, fig. 32B is an output waveform diagram of the signal Pa, fig. 32C is an output waveform diagram of a clock signal, fig. 32D is an output waveform diagram of the signal Pb when a finger is not allowed to make contact with the electrostatic discharge and the touch sensing electrode, fig. 32E is an output waveform diagram of the signal Pc, and fig. 32F is an output waveform diagram of the signal Pd.

Fig. 33A is an output waveform diagram of the signal Ps, fig. 33B is an output waveform diagram of the signal Pa, fig. 33C is an output waveform diagram of a clock signal, fig. 33D is an output waveform diagram of the signal Pb when a finger is not allowed to make contact with the electrostatic discharge and the touch sensing electrode, and fig. 33E is an output waveform diagram of the signal Pc, and fig. 33F is an output waveform diagram of the signal Pd.

Fig. 34 is a sectional view showing a part of a photosensor array according to the third embodiment of the present invention.

Fig. 35A and 35B are sectional views for explaining a first step and a second step in a method of manufacturing a photosensor array of the structure shown in fig. 34.

Fig. 36A and 36B are sectional views for explaining a third step and a fourth step in the method of manufacturing the photosensor array of the structure shown in fig. 34.

Fig. 37A and 37B are sectional views for explaining a fifth step and a sixth step in the method of manufacturing the photosensor array of the structure shown in fig. 34.

Fig. 38 is a sectional view showing a part of a photosensor array according to the fourth embodiment of the present invention.

Fig. 39 is a schematic configuration diagram of a double gate type photosensor in which three semiconductor layers are provided, which constitute a photosensor section for each device.

Fig. 40 is a cross-sectional view showing a part of the photosensor of fig. 39.

Fig. 41 is a plan view of a photosensor array in which the double-gate type photosensors shown in fig. 40 are arranged in a matrix.

FIG. 42 shows a diagram of a photosensor array according to yet another embodiment of the invention.

Fig. 43 to 48 are diagrams showing different variations of electrostatic discharge and contact sensing electrodes.

Detailed Description

First, all of double-gate (double-gate) type photosensors for a photosensor array are explained.

Fig. 1 is a sectional view schematically showing the basic structure of a double gate type photosensor. As shown in fig. 1A, the double-gate type photosensor 10 includes a semiconductor layer (channel layer) 24 in which a pair of electrons and holes is generated when excitation light (here, visible light) is incident thereon; n + doped layers 26a and 26b, respectively provided on both sides of the semiconductor layer 24; a drain electrode 27a and a source electrode 27b, which are formed of chromium, aluminum, an aluminum alloy, or the like, on the doped layers 26a and 26b, and which do not transmit visible light; a top gate electrode 29 formed of a transparent conductive film such as ITO (indium-tin oxide) formed on the semiconductor layer 24, the electrode being transparent to visible light via one insulating film 25 and an upper (upper) gate insulating film 28; the bottom gate electrode 22 is formed of such a material as chromium, chromium alloy, aluminum alloy, and is opaque to visible light via a lower (bottom) gate insulating film 23 (lower part of the figure) under the semiconductor 24.

In fig. 1A, the top gate electrode 29, the top gate insulating film 28, the bottom gate insulating film 23, and the protective insulating film 30 on the top gate electrode 29 are all formed of a material having high transparency to visible light that excites the semiconductor layer 24. On the other hand, the bottom gate electrode 22 is formed of a material that is opaque to light, with the result that the bottom gate electrode 22 has only a structure that detects incident light above the drawing.

Therefore, the double-gate type photosensor 10 has a structure in which a double MOS transistor including an upper MOS transistor forming the semiconductor layer 24, the drain 27a, the source 27b, and the top gate electrode 29, and a lower MOS transistor forming the semiconductor layer 24, the drain 27a, the source 27b, and the top gate electrode 29 are combined and formed on the transparent substrate 21, and both the MOS transistors have the semiconductor layer 24 as the common semiconductor layer 24.

Such a double gate type photosensor 10 is generally represented by an equivalent circuit shown in fig. 1B. Here, TG denotes a top gate terminal, BG denotes a bottom gate terminal, S denotes a source terminal, and D denotes a drain terminal.

A photosensor system of a photosensor array constituted by the above-described double-gate type photosensors arranged two-dimensionally will be briefly described with reference to the drawings.

Fig. 2 is a schematic diagram of a structure of a photosensor system including a double-gate type photosensor.

As shown in fig. 2, the photosensor system generally includes: a photosensor array 100 in which a number of double gate type photosensors 10 of a matrix structure like n rows and m columns are arranged; a top gate row 101 and a bottom gate row 102, to which a top gate terminal TG (top gate 29) and a bottom gate terminal BG (bottom gate terminal 22) are connected, respectively, in the row direction; the drain line 103 connects the drain terminal D (drain electrode 27a) of the double-gate type photosensor 10 in the column direction; the source line 104 connects the source terminal S (source electrode 27b) in the column direction; a set of top gate pads 111 are arranged at the peripheral portion of the dual gate type photoelectric sensor 10 to be connected to the top gate row 101, and a set of bottom gate pads 121 are connected to the bottom gate set; a set of drain pads 131 connected to the drain row 103, a set of source pads 141 (number of pads greater than or equal to 1); the top gate driver 110 is connected to the top gate row 101 through a top gate disk group 111.

And a bottom gate driver 120 connected to the bottom gate row 102 through a bottom gate disk group 121.

A drain driver (output circuit section) 130 including a column switch 132 connected to the drain row 103 through a drain pad group 131, a precharge switch 133, and an amplifier 134; and

the light source 140 serves as a backlight.

Here, the top gate rows 101 are formed integrally with a transparent conductive film and the top gates 29, such as ITO or the like. Bottom gate rows 102, drain rows 103, and source rows 104 are integrally formed with bottom gates 22, drains 27a, and sources 27b from the same material that is opaque to the excitation light. Source row 104 is connected to ground through a group of source disks 141.

In fig. 2, symbols Φ tg and Φ bg denote control signals for generating reset pulses Φ T1, Φ T2, …, Φ Ti, …, Φ Tn, read pulses Φ B1, Φ B2, …, Φ Bi, …, Φ Bn, respectively. The symbol Φ pg denotes a precharge signal for controlling the time of applying the precharge voltage.

In this structure, the photo-sensing function is realized by applying a voltage to the top gate TG from the top gate driver 110 through the top gate row 101. A voltage is applied from the bottom gate driver 112 through the bottom gate row 102 to the bottom gates BG. By applying a voltage to the bottom gate BG a detection signal is entered via the drain line 103 into the drain driver 130, resulting in a selective read function, the signal through the output (Vout) being serial or parallel data.

Next, a method of driving the above-described photosensor system will be described with reference to the drawings.

Fig. 3 is a timing chart of a method of driving the above-described photosensor system. Fig. 4 to 10 show operation principle diagrams of the double gate type photoelectric sensor. Fig. 11 and 12 show the light response characteristics of the output voltage of the photosensor system. The explanation will be made with reference to the structure of the double gate type photosensor and photosensor system (fig. 1 and 2) roughly.

First, reset, as shown in fig. 3 and 4, a pulse voltage (reset pulse, for example, high level Vtg ═ 15V) Φ Ti is applied to the ith row top gate row 101, so that carriers (holes here) accumulated in the vicinity of the contact surface between the semiconductor layer 24 and the block insulating film 25 are released in the reset period reset.

Then, in the light condensing period, as shown in fig. 3 and 5, a low-level (e.g., Vtg ═ 15) bias voltage Φ Ti is applied to the top gate row 101 to terminate the reset operation, and the light condensing period is started by the carrier condensing operation. In the light collecting period Ta, since electron holes are generated in a region of the semiconductor layer 24, which is called a carrier generating region, where light enters, positive holes are collected in the vicinity of a contact surface with the semiconductor layer 24 of the bulk insulating film 25, which is called a channel region effect.

In the precharge operation, as shown in fig. 3 and 6, a predetermined voltage (precharge voltage) is applied to the drain row 103 based on the precharge signal Φ pg and along the light integration period Ta to allow the drains to remain charged (precharge period Tprch).

Then, in the read operation, as shown in fig. 3 and 7, after the precharge period T' prch, a high-level (e.g., Vbg ═ 10V) bias voltage (read select signal, hereinafter referred to as read pulse) Φ Bi is applied to the bottom gate row 102 to set the dual-gate type photosensor 10 to an on state (read period Tread).

Here, in the read period Tread, carriers (holes) operate in a direction of canceling out the voltage Vtg (+15V) applied to the term gate TG having the opposite polarity, thereby forming an n-channel with the bottom gate BG. Therefore, the drain line voltage VD of the drain line 103 shows a tendency to gradually decrease from the precharge voltage Vpg with time, as shown in fig. 11. That is, in the light integration period Ta, the light integration state is a black state, and in the case where carriers (positive holes) are not integrated in the channel region, as shown in fig. 8 and 11, the positive bias of the bottom gate BG is cancelled by applying a negative bias to the top gate TG, and thus, the dual gate type photosensor 10 is turned off. Then, the drain voltage (voltage VD of drain line 103) is held.

On the other hand, when the light condensing state is a bright state, as shown in fig. 7 and 11, carriers (positive holes) are trapped according to the amount of incident light, causing the carriers (holes) to operate at the top gate TG that cancels the negative bias. As a result, the positively biased double gate type photosensor 10 having the bottom gate BG is turned on due to the offset amount. Then, the voltage VD of the drain line 103 is lowered according to the on-resistance corresponding to the amount of incident light.

As a result, as shown in fig. 11, the trend of the variation of the voltage VD of the drain line 103 is extremely related to the amount of light received during the time from the point of terminating the reset operation by applying the reset pulse Φ Ti to the top gate TG to the application of the read pulse Φ Bi to the bottom gate BG. The voltage VD tends to decrease gradually if the accumulated carriers are few. On the other hand, if many carriers are accumulated, the voltage VD tends to decrease rapidly. As a result, the read cycle Tread starts, and the amount of light applied can be calculated by detecting the voltage VD of the drain line 103 after a predetermined time, and by detecting the time until a predetermined reference voltage is reached according to the predetermined reference voltage.

By setting a series of image reading operations to one cycle, the dual-gate type photosensor 10 can operate as a two-dimensional sensor system by allowing the i +1 th row dual-gate type photosensor to repeat the same process.

In the timing chart shown in fig. 3, after the precharge period Tprch, as shown in fig. 9 and 10, when the low level (for example, Vbg ═ 0V) state continues to be applied to the bottom gate row 102, the dual-gate type photosensor 10 maintains the off state. As shown in fig. 12, the precharge voltage Vpg is maintained for the voltage VD of the drain row 103. In this method, a selection function of selecting a read state of the dual gate type photosensor 10 is realized according to an application state of a voltage to the bottom gate row 102.

FIG. 13 is a cross-sectional view showing an apparatus for forming a read two-dimensional image using the photoelectric sensing system.

As shown in fig. 13, in an image reading device for reading a two-dimensional image such as a fingerprint or the like, light R1 applied from a backlight (surface light source) 140 is incident on the device, and the backlight 140 is provided on a glass substrate (insulating substrate) 21 at the lower end, on which a double gate type photosensor 10 is formed. In the device, except for the formation region of the double gate type photosensor 10, applied light R1 is allowed to pass through the transparent insulating substrate 21 and the insulating films 23, 28, and 30 to be applied to a subject (subject) on the protective insulating film 50.

The reflected light R2 based on the reflectance (light and dark information) determined by the image pattern (or emission or retraction pattern) of the subject 50 passes through the transparent insulating films 30, 28, 25 and the top gate electrode 29 so as to enter onto the semiconductor layer 24, resulting in carrier concentration corresponding to the image pattern of the subject 50, and the image pattern of the subject 50 can be read as light and dark information by a series of drive control methods.

Next, the photosensor array according to the present invention is explained by specific embodiments. The following examples are explained based on the following assumptions: the double-gate type photosensor is applied as a photoelectric conversion element (photosensor), and a voltage is applied to the first gate electrode using the top gate electrode. Therefore, a photoelectric sensing function is realized. A voltage is applied to the second gate electrode with the bottom gate electrode. Thus, a function of reading the accumulated electric power of the channel region is realized.

(first embodiment)

Fig. 14 is a sectional view showing a part of one structural example of a photosensor array according to the present invention. Here, the explanation is that: the photosensor array is formed by applying a double gate type photosensor having the same structure as that shown in fig. 1A. In addition, only one double gate type photosensor formed on the array region is shown due to lack of description in the drawing. Note that, with regard to the same structure as the above-described structure (fig. 1A), the description is simplified by attaching the same reference numerals.

As shown in fig. 14, the photosensor 100A in the configuration example roughly includes an array area Aa composed of photosensors arranged in a matrix-like configuration, and a disk area Ap electrically connected to peripheral circuits such as a driver and the like.

The array area Aa is a group of photosensors arranged on the insulating film 21 in a matrix-like structure (only one sensor is shown in fig. 14 due to inconvenience) similarly to the structure described in fig. 1A described above. The optical sensor includes: a semiconductor layer 24 formed of amorphous silicon or the like; doped layers 26a and 26b on both sides of the semiconductor layer, respectively; a drain electrode 27a and a source electrode 27b on the doped layers 26a and 26b, respectively; a bulk insulating film 25 on the semiconductor layer 24; an upper gate electrode 29 formed on the semiconductor layer 24 through an upper gate insulating film 28; and a lower gate electrode 22 formed under the semiconductor layer 24 through a lower gate insulating film 23.

Here, the bulk insulating film 25, the top gate insulating film 28, the bottom gate insulating film 23, and the protective insulating film 30 are formed of a transparent insulating film such as silicon nitride (SiN) or the like having light transmittance. In addition, the top gate electrodes 29 and the top gate lines 101 are formed of a conductive film such as ITO or the like having high transmittance with respect to the excitation light. On the other hand, at least the bottom gate electrodes 22 and the bottom gate lines 102 are made of chromium or the like which blocks the passage of excitation light.

In the pad area Ap, a predetermined downward-inclined bottom gate pad area Pb (bottom gate pad group 121 shown in fig. 2) is arranged, formed at the end of the bottom gate line 102 extending from the bottom gate electrode 22; a drain pad portion Pd (drain pad group 131 shown in fig. 2) formed at an end of the drain line 103 extending from the drain electrode 27 a; a top gate pad area Pt (top gate pad group 111 shown in fig. 2) is formed at the end of the top gate row 101 extending from the top gate electrode 2 g.

Here, the bottom pad region Pb structure is one in which the first bottom pad electrode layer 22b is composed of the same conductive material (e.g., chromium) as the drain electrode 27a and the source electrode 27b, and the second bottom pad electrode layer 22c is composed of the same conductive material (e.g., ITO) as the top gate electrode 29, laminated on the substrate 22a integrally formed with the bottom gate electrode 22 and the bottom gate line 102. The second bottom pad electrode layer 22c is exposed from the open end formed on the protective insulating film 30 to be electrically connected by, for example, a bump (outer end) Bb provided on the bottom gate driver 120 side.

The drain pad region Pd has a structure in which a first drain pad electrode layer 27y composed of the same conductive material (e.g., ITO) as the top gate electrode 29 is laminated on a substrate 27x formed integrally with the drain gate line 102, and the drain pad electrode layer 27y constituting the uppermost layer is exposed from an open end formed on the protective insulating film 30 to be electrically connected (to the switch 132) through a bump Bd provided on the drain driver 130 side.

The top gate pad region Pt is constituted such that the top gate electrodes 29a formed integrally with the top gate row 101 are directly exposed from the protective insulating film 30 to be electrically connected through the bumps Bt provided on the top gate driver 110 side.

That is, since the cross-sectional structure of the photosensor is a laminated structure of the photosensor array to which the double gate type photosensor is applied as described above, an open-port step (step) formed on the disk portion may be significant, and configuration failure of the conductive electrode (electrode layer on the disk portion) and contact failure of the bump provided on the driver side may occur.

In contrast, in the photosensor array according to the structural example, the pad portions (specifically, the bottom gate pad portion Pb and the drain pad portion Pd) formed on the pad portions are formed in a layered structure including a plurality of electrode layers. Therefore, the layered electrode layer is formed in a thick configuration, so that it is possible to suppress configuration failure while making it possible to improve the contact of the bump provided on the driver side.

Further, the photosensor array 100A has the second pad electrode layer 22C and the first drain electrode layer 27 y. Only either one of the two electrode layers may be provided in the photosensor array 100A. Then, the source pad group 141 may have the same structure as the substrate 27x, the first drain electrode layer 27y, and the pad region Ap. In addition, the source disk group 141 may be formed in the same layer structure as the substrate 27 x.

Fig. 15 is a sectional view showing a part of another configuration example in the photosensor array according to the first embodiment of the present invention. The case of a photosensor array constituted by double gate type photosensors each having two semiconductor layers constituting a photosensor array portion of each element will be explained. Incidentally, for the purpose of illustration, only a single double gate type photosensor formed on the array region is shown. Also, like elements (fig. 1A and 14) are denoted by like reference numerals, and explanations thereof are omitted.

As shown in fig. 15, the photosensor array 100B in the example structure constitutes an array area Aa and a disc area Ap in the same way as the structure shown in fig. 14. On the array region Aa, a plurality of photosensors (only one sensor is shown in fig. 15 for convenience) are arranged in a matrix-like structure on an insulating substrate 21, and the photosensors include two semiconductor layers 24a and 24b formed of amorphous silicon or the like, the layers being arranged in parallel to generate electron-hole pairs when visible light is incident.

Doped layers 26a, 26b, 26c and 26d are formed of n + silicon, these layers being at either end of each semiconductor layer 24a and 24b, respectively, with a single source 27b extending between doped layers 26b and 26c of semiconductor layers 24a and 24b, and an electrode formed between semiconductor layers 24a and 24 b.

Drain electrodes 27a and 27c are located opposite to the source electrode 27b, sandwiching each of the semiconductor layers 24a and 24b, and are formed on the doped layers 26a and 26d, where electrical connection of the electrodes 27a and 27c is not shown, a bulk insulating film 25a is provided on the semiconductor layer 24a, a bulk insulating film 25b is provided on the semiconductor layer 24b, a single top gate electrode 29 is formed on the semiconductor layers 24a and 24b via a top gate insulating film 28, and a single bottom gate electrode 22 is formed under the semiconductor layers 24a and 24b via a bottom gate insulating film 23. Incidentally, the disc area Ap has a disc area of the same layered structure as that shown in fig. 14.

That is, the double-gate type photosensors applied to the photosensor array 100B in the configuration example have the first and second double-gate type photosensors in parallel arrangement and parallel structure. The first double-gate type photosensor includes a first upper MOS transistor formed on an insulating substrate 21, having a semiconductor layer 24a, a drain electrode 27a, a source electrode 27b, a top gate insulating film 28, and a top gate electrode 29; and a first lower MOS transistor formed of a semiconductor layer 24a, a drain electrode 27a, a source electrode 27b, a bottom gate insulating film 23, and a bottom gate electrode 22, the semiconductor layer 24a serving as a common channel region. The second double-gate type photosensor includes a second upper MOS transistor formed of a semiconductor layer 24b, a source electrode 27b, a drain electrode 27c, a top gate insulating film 28, and a top gate electrode 29; and a second lower MOS transistor formed of the semiconductor layer 24b, the drain electrode 27c, the source electrode 27b, the bottom gate insulating film 23 and the bottom gate electrode 22, the semiconductor layer 24b being formed as a common channel region.

In the photosensor array 100B having such a structure, since the disk region can be formed in the layered structure, similarly to the above-described structural example, the failure in the arrangement of the electrode layers can be suppressed, and the contact with the driver can be improved.

The top gate electrode 29 and the bottom gate electrode 22 constitute first and second dual-gate type photosensors including common electrodes, respectively, and the drain electrodes 27a and 27c facing the common source electrode 27b are divided (branched) in this structure. Therefore, by applying the above-described drive control method, the double-gate type photosensor having two semiconductor layers, each device constituting a photosensor section, can operate in a manner similar to that of the double-gate type photosensor having one semiconductor layer.

A method of manufacturing the photosensor array having the above-described structure will be explained in detail with reference to the accompanying drawings.

Fig. 16a and 16b are sectional views for explaining a method of manufacturing a photosensor array having the structure shown in fig. 15. It is to be understood that the photosensor array manufactured with the structure shown in fig. 14 can be realized by almost the same method. Also, in the following explanation, the designations of the first to seventh steps are for convenience of explanation, and are not related to an actual manufacturing process.

First, in a first step, after a metal layer of chromium or the like having a thickness of 100nm (1000A) is formed on an insulating substrate 21 such as glass or the like by a sputtering method, vapor deposition or the like, the metal layer is selectively etched by a photolithography method or a Reactive Ion Etching (RIE) method to form a bottom gate electrode 22, a substrate 22a and a bottom gate line 102 having a predetermined structure.

Then, in a second step, as shown in fig. 16B, an insulating film 23 (hereinafter referred to as a bottom gate insulating film) formed of silicon nitride or the like, having a thickness of, for example, 250nm, an amorphous silicon film (hereinafter referred to as an a-Si film) 24p, having a thickness of, for example, 50nm, and an insulating film (hereinafter referred to as an SiN film) formed of silicon nitride, having a thickness of, for example, 100nm, are formed on the insulating film 21, which includes the bottom gate electrodes 21, the substrate 22a and the bottom gate lines 102.

Next, the block insulating films 25a and 25b are formed by selectively etching SiN on the bottom gate electrode by a photolithography method, a dry etching method, or the like, and they have a predetermined structure.

Next, in the entire region of the a-Si film 24P including a portion over the bulk insulating films 25a and 25b, an N-type silicon film 26P, which is made of, for example, N-type impurity ion amorphous silicon including, for example, phosphorus ions (P +) or the like, with a thickness of 25nm, is deposited on the entire region of the a-Si film 24P including a portion over the bulk insulating films 25a and 25b by a plasma CVD method or the like. Alternatively, the silicon film 26 may be formed such that after the formation of the internal amorphous silicon film, N-type impurity ions are doped into the amorphous silicon film by an ion implantation method and a thermal diffusion method.

Next, at a third step, as shown in fig. 16C, by selectively etching the a-Si film 24p and the N-type silicon film 26p by photolithography and dry etching, semiconductor layers (channel layers) 24a and 24b having a predetermined structure are formed under the bulk insulating films 25a and 25b, impurity doped layers 26a and 26b having a predetermined structure extending at both ends of the bulk insulating film 25a are formed at both ends of the bulk insulating film 24a, and impurity doped layers 26C and 26d having a predetermined structure extending at both ends of the bulk insulating film 25b are formed at both ends of the bulk insulating film 24 b.

Then, by etching the bottom gate insulating film 23 on the substrate 22a using a photolithography technique, a dry etching method, or the like, an opening portion 23a exposing the upper surface of the substrate 22a is formed.

In the fourth step, as shown in fig. 17A, a metal layer of chromium or the like having a thickness of 50nm is formed by a sputtering method or the like, on the entire region of the bottom gate insulating film 23 including a part on the semiconductor layers 25a and 25b, the bulk insulating films 25a and 25b, and the impurity doped layers 26a, 26b, 26c, and 26d, which are formed in the third step. The metal layer is selectively etched by a photolithography method or an RIE method to form drain electrodes 27a and 27c extending on the impurity doped layers 26a, 26b, sandwiching each of the semiconductor layers 24a and 24b with respect to the source electrode 27b, which are connected to a lead layer, not shown, arranged on the substrate 27x at a predetermined position, and forming drain lines 103 connecting the drain electrode 27a to the substrate 27 x. At this time, the first bottom pad electrode layer 22b connected to the substrate 22a is simultaneously formed through the opening portion 23a formed on the bottom gate insulating film 23.

In the fifth step, as shown in fig. 17B, an insulating film (hereinafter referred to as a top gate insulating film) 28 having a thickness of, for example, 150nm is formed on the entire region of the bottom gate insulating film 23 by a plasma CVD method or the like, including the drain electrodes 27a and 27c, the source electrode 27B, the substrate 27x and the drain line 103, the first bottom pad electrode layer 22B. Then, the top gate insulating film 28 on the first lower electrode layer 22b and the substrate 27x is etched, forming opening portions 28a and 28b that expose the first bottom pad electrode layer 22b and the substrate 27 x.

In the sixth step, as shown in fig. 18A, a transparent conductive layer such as ITO or the like with a thickness of, for example, 50nm is formed on the entire region of the top gate insulating film 28 by a sputtering method, an ion implantation method, or the like. The transparent conductive layer is selectively etched by a photolithography method, a wet etching method, or the like to form a common top gate electrode 29 formed on the following layers: semiconductor layers 24a and 24b, a substrate 29a arranged at predetermined positions, and a top gate row 101 connecting the top gate electrode 29 and the substrate 29 a. At this time, the second lower substrate electrode layer 22c connected to the first lower substrate electrode layer 22b through the opening portion 28a and the first drain pad electrode layer 27y connected to the substrate 27x through the opening portion 28b are formed.

In the seventh step, as shown in fig. 18B, an insulating film (hereinafter referred to as a protective insulating film) 30 made of silicon nitride having a thickness of, for example, 200 to 800nm is formed on the entire region of the top gate insulating film 28, including the top gate electrode 29, the substrate 29a, the top gate row 101, the second bottom gate electrode layer 22c, the first drain pad electrode layer 27y, and the etched substrate 29a to form openings 30a, 30B, and 30c exposing the upper surfaces of the second bottom gate electrode layer 22c, the first drain pad electrode layer 27y, and the substrate 29a, respectively.

Then, the photosensor array 100B manufactured in the above-described step is arranged on the pad area Ap as shown in fig. 15, and is electrically connected to the bottom gate driver 120, the drain pad driver 130, and the top gate driver 110 shown in fig. 2 through the bumps (outer ends) Bb, Bd, and Bt, respectively, to the second bottom pad electrode layer 22c, the first drain pad electrode layer 27y, and the substrate 29a (exposed in the openings 30a, 30B, and 30c and formed in the protective insulating film 30).

As a result, according to the method of manufacturing such a photosensor array, the electrode layer of each pad region arranged on the pad region is laminated and the same material is formed at the same step as the conductive layer of the double gate type photosensor arranged on the array region. Therefore, compared with the structure in which the array region and the disk region are formed in the respective steps, the manufacturing process (specifically, the molding step using the photolithography or etching technique) can be reduced (eight times in the present manufacturing method), and therefore, reduction in manufacturing cost and reduction in manufacturing time can be attempted. Meanwhile, forming the electrode layer of the pad section of a thick thickness can try to suppress structural failure and improve the contact with the peripheral circuit.

Here, the relationship between the structure of each of the structures shown in fig. 14 and 15, which constitutes the semiconductor layer in the double-gate type photosensor of the above-described photosensor array, in which excitation light is actually injected into the active region (carrier generation region), and the light receiving sensitivity for the double-gate type photosensor will be explained. Then, comparison and detection are performed.

Fig. 19A shows an incident active region of one double-gate type photosensor of the double-gate type photosensors, in which each device constitutes a semiconductor layer of the photosensor section shown in fig. 14. Fig. 19B shows an arrangement structure in the photosensor array. Fig. 20 is a schematic diagram showing a change in light reception sensitivity (distribution characteristic, hereinafter referred to as light detection region distribution) of the structure shown in fig. 19A. Also, fig. 21A shows an incident active region of a double gate type photosensor in which each device constitutes two semiconductor layers of the photosensor section shown in fig. 14. Fig. 21B shows an arrangement structure in the photosensor array. Fig. 22 is a schematic diagram showing the arrangement of the photo-sensing areas of the structure shown in fig. 21A. Here, the distributions of the light sensing region schematically shown in fig. 20 and 22 show that a predetermined light reception sensitivity can be obtained at the center of the semiconductor layer, but the distributions do not strictly show the distribution range of the light reception sensitivity.

As shown in fig. 19A, the planar structure of the double gate type photosensor 10A applied to the photosensor array 100B includes:

the lower and top gate rows 101, 102 are extended in the x direction (horizontal direction in the drawing) as a whole with respect to the bottom gate electrode 22 formed below the semiconductor layer 24 and the top gate electrode formed on the semiconductor layer 24.

Further, the drain line 103 and the source line 104 extend in the y direction (vertical direction in the drawing) as a whole with respect to the drain electrode 27a and the source electrode 27b which are formed on both ends of the semiconductor layer 24 and face each other.

In the double-gate type photosensor 10A having such a planar structure, the leakage current Ids according to the light amount has a relationship represented by the following mathematical expression:

Ids∝W/L …(1)

here, as shown in fig. 14 and 19A, symbols W and L denote a channel width and a channel length of the semiconductor layer 24, respectively. In the relationship expressed by the mathematical expression (1), the leakage current can be large to increase the voltage ratio between the bright light and the dark light, and therefore, the sensitivity of the double gate type photosensor 10A can be as large as desired, with W/L being desirably 3 or more, and more desirably 7 or more, to sufficiently judge the brightness and darkness due to the drift in the precharged leakage voltage.

On the other hand, if the double-gate type photosensor 10A is used as a photosensor that accumulates charges according to externally incident excitation light, it is clear that the light receiving sensitivity mainly depends on the area of the incident active region where the excitation light is incident on the portion of the semiconductor layer 24 exposed between the drain electrode 27a and the source electrode 27b, that is, the direction actually depends on the channel length L of the semiconductor layer and the channel width W of the semiconductor layer.

Here, since the drain electrode 27a and the source electrode 27b are opaque to visible light, the incident active region of the semiconductor layer 24, which generates carriers effective for leakage current, is a region sandwiched between the drain electrode 27a and the source electrode 27 b. The area is aligned (defined) with the distance K in the x direction and the channel width W in the y direction of the drain electrode 27a and the source electrode 27 b.

In this method, since the sensitivity of the photosensor depends on the channel, and the length K in the direction of W and the channel length, the transistor source-drain current value Ids depends on the ratio between the channel width W and the channel length L, and it is required in this method that the design value of W/L is as large as possible. However, when W/L is set to a large value, the planar structure of the double gate type photosensor 10A shown in fig. 14 and 19A becomes a rectangular structure in which the length W in the channel width direction (or the longitudinal direction of the semiconductor layer 24) is inevitably large and the length K in the channel length direction (or the dimension of the semiconductor layer 24 in the width direction) is small. Therefore, the distribution in the light sensing area having high light receiving sensitivity is deviated to the y direction with respect to the x direction.

In particular, since the incident active region of the semiconductor layer 24 is assumed to have a rectangular structure, the photoelectric sensing distribution on the semiconductor layer 24 inevitably becomes a vertically long region Ea (having a structure substantially similar to the incident active region of the semiconductor layer 24) extending in the longitudinal direction (vertical direction in the drawing, y direction) of the semiconductor layer 24. The region in which desired light sensitivity with respect to the horizontal direction (x direction) in the figure can be obtained has a characteristic that the region is narrow in the y direction.

As a result, as a result of the deviation of the photo-sensing areas in the x and y directions, bright and dark information (read image) from the subject is read out in a distorted state. Therefore, it is impossible to achieve both high light reception sensitivity and good image information reading operation with suppressed distortion.

Further, the planar structure of the photosensor array 100A constituting this double-gate type photosensor 10A is such that, for example, as shown in fig. 19B, it is considered that the double-gate type photosensor 10A is arranged in the x and y directions (row and column directions) perpendicular to each other as an equally spaced lattice (matrix) like structure having a predetermined Pitch (Pitch) Psp, and further, light energy from the surface side of the insulating substrate (glass substrate) 21 is applied to the main body through the inter-device region Rp in the latex. To add a sufficient amount of light to the body, it is necessary to ensure that the inter-device area Rp is as large as possible.

On the other hand, as shown in fig. 21A, the planar structure of the double-gate type photosensor 10B applied to the photosensor array 100A shown in fig. 15 is: wherein, with respect to the bottom gate electrode 22 and the top gate electrode 29, a bottom gate row 102 and a top gate row 101 extending in the x direction (horizontal direction in the drawing) are integrally formed. Then, the source electrodes 27b formed and extended between the semiconductor layers 24a and 24b are arranged in parallel with respect to the whole, and the source rows 104 extended in the y direction (vertical direction in the drawing) are formed. Further, the structure of the photoelectric sensor is as follows: facing the source electrode 27b, drain lines 103 extending in the y direction (vertical direction in the drawing) are formed integrally with respect to drain electrodes 27a and 27c formed on the other ends of the two semiconductor layers 24a and 24b, respectively.

In the double gate type photosensor 10B having such a planar structure, by allowing the width direction (longitudinal direction) to be located at an opposite position, the two semiconductor layers 24a and 24B are continuously arranged in parallel along the channel length direction. Thus, the semiconductor layer is aligned with the drain electrodes 27a and 27b and the source electrode 27 b. The length in the channel width direction of the incident active region in the semiconductor layers 24a and 24b aligned with the drain electrodes 27a and 27b and the source electrode 27b is denoted by W, and the length in the channel length direction is denoted by K1 and K2, respectively. The longitudinal length (length in the channel width direction) of the incident active region of the semiconductor layers 24a and 24b is set to W, and the width dimension of the incident active region is set to lengths K1 and K2. On the other hand, the light receiving sensitivity of the semiconductor layer 24a is assumed to be a rectangular structure substantially wide by W length K1, and the light receiving sensitivity of the semiconductor layer 24a is assumed to be a rectangular structure substantially wide by W length K2. As the double-gate type photoelectric sensor 10B, a region represented by two rectangular structures becomes an incident active region.

In this case, the structure (the composite structure of the rectangular region having the vertical length W and the horizontal length K1 and the rectangular region having the vertical length W and the horizontal length K2) as the incident active region in each of the semiconductor regions 24a and 24b becomes like a square structure, and a change in light reception sensitivity due to the incident angle of the excitation light to the semiconductor layers 24a and 24b can be corrected.

That is, the device operates in such a manner that the ratio (W/(K1+ K2)) of the length W in the channel width direction and the length in the channel length direction to (K1+ K2) tends to be more and more 1, and as shown in fig. 22, the incident sensitivity of light on the semiconductor layers 24a and 24B, respectively, from the angle in the x direction (arrow a; in detail, concentrated in the ± 45 ° region in the x direction, respectively) becomes equal to the incident sensitivity of light on the semiconductor layers 24a and 24B, respectively, from the y direction (arrow B; in detail, concentrated in the ± 45 ° region in the y direction, respectively). Therefore, the variation (directivity) of the light receiving sensitivity can be corrected, and since the distribution of the light sensing areas has substantially the same distribution in the x and y directions (a rectangle close to a square), the area E can be obtained.

Here, in the ratio (W/(K1+ K2)) of the length W in the channel width direction and the length sum (K1+ K2) in the channel length direction, the length sum (K1+ K2) that affects the light reception sensitivity of the dual-gate type photosensor 10B can be replaced by the sum Σ Ki of the lengths Ki of the incident active regions of the semiconductor layers in the number of semiconductor layers formed in one device.

The same applies to the structures shown in fig. 19A and 19B. In the structure shown in fig. 21A, it goes without saying that the directivities of incident light may be further aligned. Further, in addition to the conditions in fig. 21A and 22, when the regions surrounded by both sides defined at both end portions of the incident active region of the one set of semiconductor layers 24a and 24b in the y direction and both sides defined at both end portions of the incident active region of the one set of semiconductor layers 24a and 24b in the y direction (the boundary between the drain electrode 27a and the incident active region of the semiconductor layer 24a, the boundary between the drain electrode 27c and the incident active region of the semiconductor layer 24 b) tend to be square-shaped structures, the structures are desirable from the viewpoint of the balance of light receiving sensitivity.

In the double-gate type photosensor 10B shown in fig. 15 and 21A, the leakage current Ids based on the light amount generally has the following relationship.

Ids∝W/L1+W/L2 …(2)

Here, symbol W denotes the channel width of the semiconductor layers 24a and 24b, and symbols L1 and L2 denote the channel length of the semiconductor layers 24a and 24b, respectively. The channel length in the two semiconductor layers 24a and 24b is set to L1-L2-L. Based on the above mathematical expression (2), compared with the double gate type photoelectric sensor 10A shown in fig. 19A, since the source-drain current Ids can be theoretically doubled, the transistor characteristics are improved.

As a result, such a double-gate type photosensor 10B is arranged in a matrix-like structure as shown in fig. 21B to constitute a photosensor array 100B, resulting in uniform distribution of the photosensor areas, realizing a photosensor array of light receiving areas having good transistor characteristics, and a reading device for two-dimensional images, and suppressing distortion when reading two-dimensional images.

Further, in the above-described double-gate type photosensor 10B, the transistor characteristics are greatly improved, and even when light is rarely incident, reading operation for reading bright and dark information can be performed well. Therefore, the illuminance on the surface light source on the reading device can be reduced (suppressed), and the power consumption of the two-dimensional image reading device can be reduced. When the illuminance on the surface light source is set to a fixed level, a reading apparatus capable of greatly reducing the light condensing time is provided, and also the transistor characteristics are improved, which is excellent in reading a two-dimensional image.

Further, the surplus light relatively equal to the current in the case of the double gate type photosensor 10A is generated, greatly improving the transistor characteristics. Accordingly, the operation of the photosensor can be controlled by minimizing the difference between the maximum value and the minimum value of the driving voltage applied to the top gate electrode and the bottom gate electrode to suppress such on-current, and therefore, the variation in the dual gate type photosensor can be suppressed by reducing the driving voltage, and thus, the reliability and the life of the photosensor array can be maintained (prolonged).

In the double-gate type photosensors 10A and 10B shown in fig. 19A and 21A, each of the top-gate rows 101 for mutually connecting the top-gate electrodes 29 is divided into a plurality of rows (two rows in the embodiment), arranged mutually in a planar manner between adjacent double-gate type photosensors, and stretched in parallel arrangement over the row width and the row thickness in the y direction in an equal (uniform) relationship. That is, the double-gate type photoelectric sensor has the following structure: the top gate row 101 is arranged and formed to be substantially perpendicular to the row direction in a symmetrical relationship with respect to the bottom gate row 102 extending to substantially connect the central portions of the double gate type photosensors.

In this method, the top gate row 101 formed in the x direction actually as an axis separately from the bottom gate row 102 is a linear structure. Therefore, when light attenuated by the top gate line 101 is incident on the semiconductor layer 24: 24a, 24b, the symmetry of incidence in the y-direction can be uniform. Further, since the drain row 104 side has a substantially line-symmetric structure, when light attenuated by the top gate line 101 is incident on the semiconductor layer 24: 24a, 24b, the balance of incidence in the x-direction can be uniform.

As a result, since the top gate lines are divided, the light incidence balance (balance) becomes equal in both the vertical direction (y direction) and the horizontal direction (x direction), and the alignment balance of the sensing light can be advantageous. Further, substantially no overlap occurs in the vertical direction (y direction) between the top gate row 101 and the bottom gate row 102 arranged between the adjacent photosensors with each other, and therefore, no parasitic capacitance is generated between the top gate row 101 and the bottom gate row 102. Thus, signal delay and voltage drop can be suppressed.

(second embodiment)

A second embodiment of the photosensor array according to the present invention will be described below with reference to the accompanying drawings.

Fig. 23 is a sectional view showing a part of a photosensor array according to the second embodiment of the present invention. Fig. 24 is a schematic structure showing one example of a photosensor system provided with the photosensor array shown in fig. 23. Here, a case will be described in which the double gate type photosensor of the same structure as that shown in fig. 15 is used. For the purpose of explanation, a case where only a single double-gate type photosensor is formed on the array region is shown. The same structure as that of the above embodiment (fig. 15) is denoted by the same reference numeral and the description thereof is omitted.

The photosensor array 100C according to the second embodiment has a structure in which electrostatic discharge and contact sensing electrodes are formed on the protective insulating film 30 as the uppermost layer 30 in the photosensor array 100B shown in fig. 15, and each electrode layer constituting the uppermost layer is laminated on the disk portion in the same step as and using the same material as the electrostatic discharge and contact sensing electrodes.

Specifically, as shown in fig. 23, the photosensor array 100C according to the second embodiment includes an electrostatic discharge and contact sensing electrode 31 formed of a light-transmitting material such as ITO on an array region Aa of a protective insulating film 30 as the uppermost layer of the photosensor array 100B shown in fig. 15, and has a structure in which electrode layers 22d, 27z, and 29B made of the same conductive material (e.g., ITO) as the electrostatic discharge and contact sensing electrode 31 are respectively laminated in opening portions 30a, 30B, and 30C formed at a disk region Ap of the protective insulating film 30.

That is, at the bottom gate portion Pb, the third bottom pad electrode layer 22d is laminated so as to be connected to the second bottom pad electrode layer 22c exposed inside the disconnected portion formed in the protective insulating film 30. In the drain gate pad portion Pd, the second drain gate pad electrode layer 27z is laminated so as to be connected to the first drain gate pad electrode layer 27y exposed inside the disconnection portion formed in the protective insulating film 30. At the top gate pad portion Pt, a top gate pad electrode layer 29b is formed on the base pad 29 to be electrically connected thereto, the latter being exposed inside the disconnection portion formed in the protective insulating film 30.

The photosensor array 100B includes the second bottom pad electrode layer 22c and the first drain pad electrode layer 27 y. However, the photosensor array 100B may include any one of the above two layers. Although not shown, the source disc group 141 may be formed in a stacked three-layer structure similar to the base disc 27x, the first drain disc electrode 27y, and the second drain disc electrode layer 27z located at the drain disc portion Pd. Or the source disc group 141 may have a one-layer or two-layer structure including any one layer or two layers similar to the base disc 27x first drain disc electrode 27y and second drain disc electrode layer 27 z.

A method of manufacturing the photosensor array 100c having the above-described structure is such that a transparent conductive film (such as ITO or the like) having a thickness of 50nm over the entire area of the protective insulating film 30 after the sensor array 100b shown in fig. 15 is formed in the manufacturing process shown in fig. 16a to 18b by sputtering and wet etching methods in the 8 th step. Thus, the electrostatic discharge and contact sensing electrode 31 is formed on the array region Aa by selectively etching the transparent conductive layer by photolithography and ion implantation. In this step, the third bottom plate electrode layer 22d connected to the second bottom plate electrode layer 22c is formed through the cut-off portion 30a of the plate area Ap, the second drain plate electrode layer 27x connected to the first drain plate electrode layer 27y is formed through the cut-off portion 30b, and the upper plate electrode layer 29b connected to the base plate 29a is formed through the cut-off portion 30 c.

The photosensor array 100c has a three-layer structure including a third chassis layer 22d, a second drain pad electrode 27z, and a top pad electrode layer 29 z. The photosensor array 100c can have only one or two layers.

Although not shown, the source disc group 141 may be formed in a three-layer structure in the same manner as the base disc 27x, the first drain disc electrode layer 27y, and the second drain disc portion 27z of the drain disc portion Pd, or the source disc group 141 may include a one-layer structure of the base disc 27x, a two-layer structure of the base disc 27x and the first drain disc electrode layer 27y or the base disc 27x and the second drain disc electrode layer 27z, or a two-layer structure of the first drain disc electrode layer 27y and the second drain disc electrode layer 27 z.

The photosensor array 100C manufactured in the above-described steps is disposed in the pad area Ap as shown in fig. 23, and is connected to the bottom gate driver 120, the drain driver 130, and the top gate driver 110, which is completed by connecting the external terminals Bb, Bd, and Bt via the third bottom pad electrode layer 22d, the second drain pad electrode 27z, and the top pad electrode layer 29 b.

According to such a photosensor array 100c and a method of manufacturing the same, similar performance and effects to those of the first embodiment can be obtained. In addition, since the charges placed on the photosensor array are discharged by using the electrostatic discharge and the contact sensing electrode, power failure and operation failure of the dual gate type photosensor constituting the sensor array can be prevented.

As shown in fig. 24, the electrostatic discharge and contact sensing electrode 31 is formed on, for example, the entire surface of the array area Aa on which a finger is placed. When a signal delayed due to parasitic capacitance of a finger is read to connect with the contact detector 150, the static electricity is forced to be grounded to prevent the drivers 110, 120, 130, etc. from being disconnected from the contact of the finger charged with the static electricity when a driving start signal for outputting the photosensor array.

Here, as shown in fig. 25, when the finger FN charged with static electricity is connected to the electrostatic discharge and contact sensing electrode 31, in order to prevent disconnection due to the electrostatic top gate driver 110, the top gate driver 120, and the drain gate driver 130, the contact detector 150 transmits static electricity from thereto to the ground and outputs a connection confirmation signal Pd. The controller 160 outputs a signal φ h to the light source 140 to cause the light source 140 to begin emitting light. Thus, when the light source 140 emits light to the array area Aa, the controller 160 outputs control signals phitg, phibg, and Vpg for controlling the operations of the top gate driver 110, the bottom gate driver 120, and the drain gate driver 130, receives a voltage Vout, which is biased by a difference between emission (emission) and withdrawal (withdrawal) of a fingerprint of the finger FN according to the amount of light hv incident on the dual gate type photosensor, generates fingerprint image data of the finger FN and confirms whether the generated image data coincides with the registered image data.

An example of the operation of the present invention will be described below. The electrostatic discharge and contact sensing electrode 31 is represented as a corresponding circuit shown in fig. 26 in a state where the finger FN is not in contact with the electrostatic discharge and contact sensing electrode 31. Here, LN shows a resistance Rx and a floating capacitance Cx in which the capacitance between the electrostatic discharge and contact sensing electrode 31 and the P-channel MOS transistor (hereinafter simply referred to as P-transistor) 216, the capacitance of the P-transistor 216, and the capacitance of the resistance Rh1 are integrated. On the other hand, the relevant portion of the electrostatic discharge and contact sensing electrode 31 in the state where the finger FN is in contact with the electrostatic discharge and contact sensing electrode 31 is represented by a corresponding circuit shown in fig. 27. The finger FN of one person has a capacitance Cy and a resistance Ry within a predetermined range, and a resistance r is generated between the finger FN and the electrostatic discharge and contact sensing electrode 31. Resistor Rh1 is constructed in such a way that resistor Rh1 is conductive at several kilovolts but is not conductive if Vdd is sufficiently below the static.

Fig. 28 is a diagram showing a basic result of a photosensor system for use in the present invention. On the upper surface of the array region Aa, an electrostatic discharge and contact sensing electrode 31 is formed, and the electrostatic discharge and contact sensing electrode 31 is connected to the high voltage Vdd side.

The contact detector 150 includes a signal generator 213 for generating various signals; an inverter 217 including an N-channel MOS transistor (hereinafter referred to as an N transistor) 215, a P transistor 216, and a run resistor 214 between the transistors; a CMOS inverter 218; the determination signal generator 219; a judgment circuit 220; resistor Rh1 and resistor Rh 2.

The signal generator 213 outputs a square wave signal Pa having a predetermined period (e.g., 21Hz), a clock pulse P phi having a predetermined period (e.g., 1024 Hz). A square wave signal Pa is input to the gate of each of the N transistor 215 and the P transistor 216 to control the switching of each transistor. The source of the P-transistor 216 and the electrostatic discharge and contact sense electrode 31 are connected to the high voltage Vdd side. The output of the CMOS inverter 217 is then connected to the electrostatic discharge and contact sense electrode 31 via resistor Rh 2. The source side of the N transistor 21 is grounded. The resistor Rh2 has a structure in which the resistor Rh2 is conductive at several kilovolts (and similar to the case of the resistor Rh 1) but is not conductive if Vdd is sufficiently lower than the static electricity. The electrostatic charge of finger FN is thus transferred to ground via either of transistors 215 and 216. But the power supply voltage Vdd is supplied to the CMOS inverter 218 without passing through the electrostatic discharge and contact sensing electrode 31.

The output signal of the CMOS inverter 217 is inverted as an input signal to the other CMOS inverter 218. The output signal Pb of the inverter 21 is sent to the determination signal generator 219 from which the square wave signal 8a and the clock signal Pd are input. The detailed structure of the determination signal generator 219 will be described later. The determination signal generator 219 is configured to output a determination signal for determining whether a finger touches the sensing electrode 31 at a predetermined time. The determination signal Pc is sent to the determination circuit 220, wherein the output signal of the inverter 218 is input to the determination circuit 220 as the determination signal Pb. The determination circuit 220 detects at which binary logic level the determination signal Pb is at when the determination signal Pc is input to determine whether or not there is a finger touch, thereby outputting a touch confirmation signal Pd when it is determined that there is a finger touch. The contact confirmation signal Pd is sent to the controller 160 (fig. 24). Then, the controller 160 outputs control signals phih, phitg, phibg, and Vpg for driving the photosensor array when the contact confirmation signal Pd is at a high level.

Here, a sensing operation of the photosensor system contacted by the signal FN will be described. Initially, when the square wave signal Pa is output from the signal generator 213 at a high level, as shown in fig. 29a, when the finger is not in contact with the electrostatic discharge and contact sensing electrode 31, the output of the CMOS inverter 217 is an inverted signal of the square wave signal Pa. It is impossible to obtain an inversion signal completely opposite to the square wave signal Pa because the inversion signal is affected by the electrostatic discharge and the floating capacitance Cx between the touch sensing electrode 31 and the P transistor 216. Then, the timing of the threshold of the inverter 218 is delayed, and the output signal Pb of the inverter 218 is output to the square wave signal Pa with a delay time Tx relative to the floating capacitance component Cx under the influence of the floating capacitance component Cx as shown in fig. 29B.

On the contrary, when the finger FN is in contact with the electrostatic discharge and contact sensing electrode 31, the contact capacitance component Cy of the human body is formed. Since this contact capacitance component Cy is connected in parallel to the floating capacitance component Cx, the output signal of the inverter 218 is output to the square wave signal Pa with respect to the combined capacitance delay time (Tx + Ty) of the floating capacitance component Cx and the contact capacitance Cy, as shown in fig. 29C.

The delay time Tx corresponding to the floating capacitance component Cx is stored in advance. Then, as shown in fig. 29D, when the determination signal generator 219 is constituted in such a manner that the determination signal Pc is output after a short time after Tx, if the determination signal Pc has been raised in the determination circuit 220, it is possible to determine whether there is human body contact according to whether the determination signal Pb is at a high level or a low level.

For the above reason, the determination signal generator 219 and the determination circuit are configured as shown in fig. 30. That is, in the determination signal generator 219, the output terminal S is a test terminal for storing the floating capacitance Cx. When a clear key constituted by a key type switch, which is provided on a photosensor system, for example, is operated, a signal "1" is input. The signal Ps from the input terminal S is supplied to the NAND gate 221. The determination signal Pd is also input to the NAND gate 221. An output signal of a high level is taken from the NAND gate 221 to be input to the AND gate 222 when a signal from the input terminal is a low level. The AND gate 222 releases the rule when both the output signal of the NAND gate 221 AND the square wave signal Pa are at a high level, AND outputs the clock signal P to be input to the counter 223.

The counter 223 is reset at a high level of the square wave signal Pa to perform a counting operation of the output signal Pe (clock signal P Φ) of the AND gate 222. Further, an output signal of the NAND gate 221 is input as a write instruction signal to a clock input terminal of the memory 225 through the inverter 224. The output signal from NAND gate 221 is thus obtained and the contents of counter 223 are written to memory 225. Then, in normal use, the content n of the counter 223, which is sequentially counted along with the clock signal P Φ, and the content m, which has been preset in the memory 225, are supplied to the comparator 226 to compare the magnitudes of the two. Every time the contents of the counter 223 are counted, the comparator 226 detects whether the contents of the counter 223 and the memory 225 become n > m. The comparator 226 is then configured such that the determination signal Pc is output when the comparator detects that the relationship n > m is established.

The determination circuit 220 contains a flip-flop 227. The determination signal Pb is input to the setting input terminal of the flip-flop 227. Further, the determination signal Pc is input to the clock input terminal. Then, the operation signal Pd of the touch key 31 is taken out from the output terminal on the Q side of the flip-flop 227.

Next, a specific operation will be described. Initially, in use, the clear key is operated to determine the delay time Tx due to the floating capacitance Cx, as shown in fig. 29B. That is, as shown in fig. 31A, when the clear key is operated, the high-level signal Ps is sent to the NAND gate 221 of the determination signal generator 219 via the input terminal S. Due to this high level, the output signal of the NAND gate 221 becomes a high level until the determination signal Pb rises. When the square wave signal Pa becomes the high level, the counter 223 is simultaneously reset as shown in fig. 31B, and then the counter 223 is reset when the number of high levels of the clock signal shown in fig. 31C starts to be counted. After the square wave signal Pa becomes high level, when it is determined that the signal Ps has risen with the time delay Tx shown in fig. 31D, the output signal of the NAND gate 221 becomes low level. Then, the counting operation of the counter 223 is suspended, and the output signal of the inverter 224 becomes a high level. Whereby the contents of the counter 223 are written into the memory 225 at the rise time of the determination signal Pb. That is, as shown in fig. 31E, the counter 223 counts the number of high levels of the output signal Pe of the AND gate 222. Therefore, the content of the rising time counter 223 until the determination signal becomes "K". This value "K" is then written into the memory 225. Incidentally, the content "K" written in the memory 225 is a value corresponding to a delay time Tx which is a delay of the determination signal Pb with respect to the square wave signal Pa due to the influence of the floating capacitance component Cx. However, since the delay time Tx is a value related to the photosensor system, these measurements are not required when the data is input in advance.

The operation of detecting finger contact is explained below. Fig. 32A to 32F are output waveform diagrams of each signal when the human body is not in contact with the electrostatic discharge and contact sensing electrode 31. Here, as shown in fig. 32A, the signal Ps is set to a low level, and it is shown that the clear key is not operated. Then, in a state where the human body is not in contact with the electrostatic discharge and contact sensing electrode 31, the delay time Tx of the signal Pb with respect to the square wave signal Pa is determined to correspond to the sub floating capacitance component Cx. In this state, in the comparator 226, when the content of the counter 223 exceeds the content of the memory 225, that is, the (K +1) th clock signal P Φ counts up to the counter 223 so that the content of the counter 223 becomes "K + 1" with respect to the content "K" of the memory 225, the determination signal Pc is output as shown in fig. 32E.

When the determination signal Pc rises, as shown in fig. 32D, since the determination signal Pb has become a high level, a determination signal having a high level is input to the setting input terminal S of the flip-flop 227 so as to set the flip-flop 227. Whereby the contact confirmation signal Pd from the Q-side output terminal of the flip-flop 227 surely becomes low level even when the level of the flip-flop 227 is high level or low level. Then, when the controller 160 receives the contact confirmation signal Pd, it is output for a fixed period of time when the high level determination signal Pc is input. Accordingly, when the contact confirmation signal Pd is detected to be a low level, the driving signal is not supplied to the drivers 110, 120, and 130 and the light source 140.

Fig. 33A to 33F are output waveform diagrams in the case where the human body contacts the electrostatic discharge and the sensing electrode 31. When a finger or the like contacts the electrostatic discharge and the sensing electrode 31, a human body contacts the capacitance component Cy. Thus, the delay time of the drive signal Pb with respect to the square wave signal Pa corresponds to the floating capacitance component Cx and the contact capacitance component Cy, and thus becomes (Tx + Ty). As described previously, when the content of the counter 223 becomes "K + 1" with respect to the content "K" of the memory 225, the determination signal Pc is output from the comparator 226, as shown in fig. 33E. When the determination signal Pc rises, as shown in fig. 33D, the determination signal Pb is not at the high level but at the low level. Therefore, the flip-flop 227 is in a reset state so that the contact confirmation signal Pd of a high level is taken out from the Q side of the output terminal of the flip-flop 227 as shown in fig. 33F. Then, when the confirmation signal Pc of the high level is input, the controller 160 receives the output contact confirmation signal Pd for a fixed period of time. When the contact confirmation signal Pd is detected to be at a high level, a driving signal is supplied to the drivers 110, 120, 130 and the light source 140 so as to start driving of the photosensor array to confirm the fingerprint.

In this way, the delay time of the determination signal Pb with respect to the square wave signal due to the floating capacitance component, that is, with respect to the electrostatic discharge and the contact electrode, the delay time of the non-contact time is stored in advance by the switching operation of the clear key. It is then determined whether the determination signal is delayed from the delay amount to detect the contact of the finger. Thus, even if it is sufficient to change the floating capacitance, the floating capacitance at this time is sufficiently stored by the operation of the clear key immediately before the touch input. Since the capacitance of the human body is sufficiently Cy added to the stored floating capacitance component in the subsequent touch input, the switch detection operation can be surely performed without being affected by the floating capacitance component Cx.

(third embodiment)

A photosensor array according to a third embodiment of the present invention will be described below with reference to the accompanying drawings.

Fig. 34 is a sectional view showing a part of a photosensor array according to the third embodiment of the present invention. Here, it is to be noted that the double gate type photosensor having two semiconductor layers, of which the photosensor portion of each device is constituted by the semiconductor layers, operates in the same manner as the structure shown in fig. 15. In addition, for convenience of explanation, only one double-gate type photosensor formed over the array region is shown in the drawings. The same components as those of the above embodiment (fig. 15) are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in fig. 34, the photosensor array 100D in this structural example includes one array area Aa and one disc area Ap. In the array area Aa, a plurality of photosensors (only one is labeled in fig. 34 for the sake of convenience of explanation) are arranged in a matrix-like structure on the insulating substrate 21, and these sensors include: a semiconductor layer 24d made of an amorphous silicon or the like for generating electron-hole pairs when visible light is incident thereon; the bulk insulating films 25a and 25b are located on two regions, which constitute one channel region of the semiconductor layer 24 a; one doped layer 26f is located above the block insulating films 25a and 25 b; doped layers 26e and 26g opposite to the doped layer 26f by sandwiching each of the block insulating films 25a and 25b (channel region) are respectively located at the end portions of each of the block insulating films 25a and 25b and connected at one unshown portion; a source electrode 27b extending on the doped layer 26f, located between the bulk insulating films 25a and 25b and formed on the bulk insulating films 25a and 25 b; drain electrodes 27a and 27c opposed to the source electrode 27b by sandwiching each of the block insulating films 25a and 25b (channel regions) are formed over the doped layers 26e and 26g, and electrically connected to a portion not shown;

a top gate electrode 29 is formed on the bulk insulating films 25a and 25b (channel regions) via a common top gate insulating film 28; and a bottom gate electrode 22 is formed below the block insulating films 25a and 25b (channel regions) via a common bottom gate insulating film 23.

In the pad section Ap, a bottom gate pad section Pb formed on an end portion of a bottom gate line 102 extending from the bottom gate electrode 22, a drain pad section Pd formed on an end portion of a drain line 103 extending from the drain electrode 27a, and a top gate pad section Pt formed on an end portion of a top gate line 101 extending from the top gate electrode 29a are arranged at predetermined intervals, respectively. Among them, under the drain row 103 and the drain pad portion Pd, are a semiconductor layer 24e formed for extension and a doped layer 26h having the same structure, and the semiconductor layer 24f and the doped layer 26i may be located even in the vicinity of the bottom gate pad portion Pb.

Thus, the double gate type photosensor for the photosensor array 100D according to the third embodiment has a structure in which: the first and second double-gate type photosensors are connected and arranged in parallel on an insulating substrate 21. The first double-gate type photosensor includes a first upper MOS transistor composed of the semiconductor layer 24d, the drain 27a, the source 27b, the top gate insulating film 28, and the top gate 29, and a first lower MOS transistor composed of the semiconductor layer 24d, the drain 27a, the source 27b, the bottom gate insulating film 23, and the bottom gate 22, the semiconductor layer 24d located between the drain 27a and the source 27b being used as a common channel region. The second dual gate type photosensor includes a second upper MOS transistor composed of the semiconductor layer 24d, the source 27b, the drain 27c, the top gate insulating film 28 and the top gate 29, and a second lower MOS transistor composed of the semiconductor layer 24d, the source 27b, the drain 27c, the bottom gate insulating film 23 and the bottom gate 22, the semiconductor layer 24d between the source 27b and the drain 27c being used as one common channel region.

In the photosensor array 100D having such a structure, since the stacked structure of the pad portion (particularly, the drain pad portion) can be formed in a thicker structure than the above-described embodiment (shown in fig. 15), the structural failure can be further suppressed, and the contact with the driver-side bump can be further improved. In addition, the semiconductor layers 24d and 24f and the doped layers 26e and 26i are extended to form layers located under the drain row 103, the drain pad portion Pd, the semiconductor layer 24d, and the doped layer 26 e. Thus, the generation steps of the upper layer of the top gate insulating film 28 and the top gate electrode 29 can be reduced, and deterioration of the insulating performance and the signal transmission performance can be suppressed.

Although the photosensor array 100D has both the second chassis electrode layer 22c and the first drain chassis electrode layer 27y, the photosensor array 100D may have either one of the two layers. Although not shown, one set of source chips 141 may also have the same two-layer structure as the first drain layer 27y and the base 27x of the drain pad portion Pd. Alternatively, the source plate group 141 may have a single-layer structure composed of layers identical to the base plate 27 x.

Next, a method of manufacturing the photosensor array having the above-described structure will be described in detail.

Fig. 35 to 37 are sectional views showing each step in the method for manufacturing a photosensor array having the above-described structure. In the foregoing description, the designation of "first step" to "sixth step" is merely for convenience of description, and the designation is not related to the actual manufacturing process. Moreover, explanations about the same structure and manufacturing process as those of the above-described embodiment will be simplified.

In a first step, as shown in fig. 35A, after a chromium metal layer or the like having a thickness of, for example, 100nm (1000A) is formed on an insulating substrate 21 such as a glass substrate, this metal layer is selectively etched to form a bottom gate 22 having a predetermined structure, a base 22a, and a bottom gate row 102.

Next, a bottom gate insulating film 23 made of silicon nitride or the like and having a thickness of 250nm, an a-Si film 24p having a thickness of 50nm, and an SiN film having a thickness of 100nm are formed over the entire area of the insulating substrate 21.

Next, the bulk insulating films 25a and 25b having a predetermined structure are formed by selectively etching the SiN film located over one region composed of the a-Si film 24 p. Further, on this region on the a-Si film 24p including the bulk insulating films 25a and 25b, an n-type silicon film 26p, for example, 25nm in thickness is deposited, which forms amorphous silicon containing n-type impurity ions such as phosphorus ions. The n-type silicon film 26p can also be obtained by introducing n-type impurity ions into the amorphous silicon film by an ion implantation method or a thermal diffusion method after forming a pure amorphous silicon film.

Next, an opening portion 23a is formed by etching the bottom gate insulating film 23, the a-Si film 24p and the n-type silicon film 26p on the base 22a, in which the base 22a is exposed to the outside.

Next, in a second step, as shown in fig. 35B, a chromium metal layer or the like 27p having a thickness of 50nm is formed on the entire region of the doped layer 26 p. Here, the metal layer 27p is formed so as to be connected to the base 22a through an opening portion 23a formed on the bottom gate insulating film 23, the a-Si film 24p and the n-type silicon film 26 p.

Next, in a third step, as shown in fig. 36A, the metal layer 27p, the a-Si film 24p and the n-type silicon film 26p formed in the second step are selectively etched to form a source 27b protruding on the bulk insulating films 25a and 25b (channel regions), drain electrodes 27a and 27c which are joined to each other through an unillustrated electrical wiring layer, which sandwich the bulk insulating films 25a and 25b (channel regions) to protrude opposite to the source 27b, a substrate 27x arranged at a predetermined position, and a drain electrode wiring 103 for connecting the drain electrode 27a and the substrate 27 x. A first chassis electrode layer 22b having a predetermined structure is also formed on or in the vicinity of the opening portion 23 a.

At this time, while the conductive layers such as the drain electrodes 27a and 27c and the source electrode 27b are formed, in the lower layer of the conductive layer, the doping layers 26e, 26f and 26g and the semiconductor layer 24d are patterned to have the same structure. A semiconductor layer 24d including a region where the drain electrodes 27a and 27c and the source electrode 27b are formed and a region constituting a channel region is formed on the bottom gate electrode 22. On the lower layer of the drain row 103, a doped layer 26h and a semiconductor layer 24e having the same structure as the drain row 103 are formed. Under the substrate 27x, a doped layer 26i and a semiconductor layer 24f having the same structure as the substrate 27x are formed.

Next, at a fourth step, as shown in fig. 36B, after a top gate insulating film 28 made of silicon nitride or the like is formed to a thickness of, for example, 150nm over the entire region covering the drains 27a and 27c, the source 27B, the base 27x, the drain row 103, and the bottom gate insulating film 23 including the first bottom plate electrode 22B, opening portions 28a and 28B are formed by etching the top gate insulating film 28 on the first bottom plate electrode layer 22B and the base 27x, with the first bottom plate electrode layer 22B and the base 27x being exposed to the outside.

Next, at a fifth step, as shown in fig. 37A, after forming a transparent electrode layer such as ITO or the like having a thickness of, for example, 50nm over the entire region covering the top gate insulating film 28, a protruded top gate electrode 29 and the semiconductor layer 24 formed as described above, a base 29a arranged at a predetermined position and a top gate row 101 for connecting the top gate electrode 29 and the base 29a are formed. At this time, the second chassis electrode layer 22c connected to the first chassis electrode layer 22b through the opening portion 28a and the first drain pad electrode layer 27y connected to the base pad 27x through the opening portion 28b are simultaneously formed.

Next, at a sixth step, as shown in fig. 37B, for example, a protective insulating film 30 made of silicon nitride or the like is formed to a thickness of, for example, 200 to 400nm over the entire region covering the top gate 29, the base 29a, the top gate row 101, the second bottom plate electrode layer 22c, and the top gate insulating film 28 including the first drain plate electrode layer 27 y. Then, by etching the protective insulating film 30 on the second bottom plate electrode layer 22c, the first drain plate electrode layer 27y, and the base 29a, opening portions 30a, 30b, and 30c are formed, in which the second bottom plate electrode layer 22c, the first drain plate electrode layer 27y, and the base 29a are exposed, respectively.

Then, in the photosensor array 100D manufactured by the above-described process, as shown in fig. 34, the second chassis electrode layer 22c, the first drain pad electrode layer 27y, and the base pad 29a are bonded to the bumps (external terminals) Bb, Bd, and Bt of the bottom gate driver and the drain driver through the opening portions 30a, 30b, and 30c formed on the protective insulating film 30.

Thus, according to this method of manufacturing a photosensor, the array area and the disk area can be manufactured using the same material and the same process. In addition, the manufacturing process (particularly, the patterning step using the photolithography technique and the etching technique) is simplified (seven times in the present manufacturing process), thereby reducing the manufacturing cost and shortening the manufacturing time. Further, the electrode layer (particularly, the drain pad portion) in the pad portion is formed in a thicker thickness, so that it is possible to suppress structural damage and improve connection with the peripheral circuit having the bump. Further, since the semiconductor layer and the doped layer extend the lower layers of the drain line and the drain pad portion, the generation steps in the insulating layer located on the upper layer and the conductive layer can be reduced, thereby suppressing deterioration of the insulating property and the transmission property.

< fourth embodiment >

A photosensor array according to a fourth embodiment of the present invention will be described below with reference to the accompanying drawings.

Fig. 38 is a cross-sectional view showing a part of a photosensor array according to the fourth embodiment of the present invention. Here, the double-gate type photoelectric sensor has the same structure as that shown in fig. 34. For convenience of explanation, only one double-gate type photosensor formed over the array region is shown in the drawings. The same structure as that of the above-described embodiment (fig. 23, 34) is denoted by the same reference numerals, and the description thereof is simplified.

In the structure of the photosensor array 100D shown in fig. 34, the photosensor array 100E according to the fourth embodiment also has a structure such that, on the array region Aa of the protective insulating film 30 formed uppermost, an electrostatic discharge and contact sensing electrode 31 composed of a conductive film such as ITO having light transmission characteristics and a potential applied thereto and electrode layers (a third chassis electrode layer 22D, a second drain pad electrode layer 27z and a top pad electrode layer 29b) made of the same conductive material (for example, ITO) as the electrostatic discharge and sensing electrode 31 are stacked together so as to be connected to the second chassis electrode layer 22c, the first drain pad electrode layer 27y and the base pad 29a through opening portions 30a, 30b and 30c (see fig. 34) formed on the pad Ap of the protective insulating film 30.

The method of manufacturing the photosensor array having such a structure is such that: after the photosensor array structure shown in fig. 34 is formed by the manufacturing processes shown in fig. 35 to 37, a transparent conductive film, such as ITO or the like, having a thickness of, for example, 50nm is formed in the seventh step over the entire area of the protective insulating film 30; then forming an electrostatic discharge and induction electrode 31 on the array area Aa by selectively etching the transparent conductive layer; a third chassis electrode layer 22d connected to the second chassis electrode layer 22c through the opening portion 30a of the panel Ap, a second drain pad electrode layer 27z connected to the first drain pad electrode layer 27y through the opening portion 30b, and a chassis electrode layer 29b connected to the base 29a through the opening portion 30c are formed.

The photosensor array 100E has a third bottom plate electrode layer 22d, a second drain plate electrode layer 27z, and a top plate electrode layer 29 b. However, the photosensor array may have only one or both of the electrode layers. Although not shown in the drawing, the source disc group 141 may be a three-layer structure including a base disc 27x of the drain disc portion Pd, a first drain disc electrode layer 27y, and a second drain disc electrode layer 27 z. Alternatively, the source electrode pad group 141 may also be a single-layer structure composed of the base pad 27x, or a double-layer structure composed of the base pad 27x and the first drain pad electrode layer 27y, or a double-layer structure composed of the base pad 27x and the second drain pad electrode layer 27z, or a double-layer structure composed of the first drain pad electrode layer 27y and the second drain pad electrode layer 27 z.

As shown in fig. 38, the photosensor array 100E manufactured in the above-described steps is connected to the bottom gate driver 120, the drain driver 130, and the top gate driver 110 by bonding the bumps Bb, Bd, and Bt to each of the third chassis electrode layer 22d, the second drain pad electrode layer 27z, and the top pad electrode layer 29b arranged on the pad area Ap.

According to the structure of this photosensor array 100E and the method of manufacturing the array, the same effects and actions as those of the above-described embodiments can be obtained. In addition, since the electrostatic discharge and the contact sensing electrode discharge the electric charge charged on the object located in the photosensor array, the electrostatic breakdown and the malfunction of the double gate type photosensor forming the photosensor array are advantageously prevented.

In the fourth embodiment, a description has been given of a structure in which one electrostatic discharge and contact sensing electrode is formed on the protective insulating film of the array region. As shown in the above embodiment (fig. 24), the photosensor array can also be configured in such a manner: the electrostatic discharge and contact sensing electrodes are formed to be divided into a plurality to discharge and charge an object while controlling an operation of each driver according to a voltage variation caused by a short circuit between the electrostatic discharge and contact sensing electrodes.

Next, another structure of the photosensor array according to the present invention will be described with reference to the drawings.

Fig. 39 is a schematic diagram showing the structure of another double-gate type photosensor employing this structural example, in which each device has three semiconductor layers constituting one photosensor section. Fig. 41 is a plan view structural diagram showing a photosensor array in which double gate type photosensors are arranged in a matrix form. Here, the same structures as those of the above-described embodiment are denoted by the same reference numerals and the description thereof is simplified.

As shown in fig. 39 and 40, the double gate type photosensor employing this structural example includes: semiconductor layers 24a, 24b, and 24c arranged in parallel; a source electrode 27b formed over the semiconductor layers 24a and 24 c; a drain electrode 27c formed over the semiconductor layers 24a and 24c, a drain electrode 27a formed opposite to the source electrode 27b with the semiconductor layer 24a interposed therebetween; a source electrode 27d formed to oppose the drain electrode 27c with the semiconductor layer 24c interposed therebetween; a doped layer 26j interposed between the semiconductor layer 24a and the drain electrode 27 a; a doped layer 26k interposed between semiconductor layer 24a and source electrode 27 b; a doped layer 26m interposed between the semiconductor layer 24b and the source electrode 27 b; a doped layer 26n interposed between the semiconductor layer 24b and the drain electrode 27 c; a doped layer 26p interposed between the semiconductor layer 24c and the drain electrode 27 c; a doped layer 26q interposed between semiconductor layer 24c and source electrode 27 d; bulk insulating films 25a, 25b, and 25c formed on the upper layers of the semiconductor layers 24a, 24b, and 24 c; a top gate 29 formed opposite the semiconductor layers 24a, 24b and 24c by a bottom gate 28 on the semiconductor layers 24a, 24b and 24 c; a top gate electrode 22 formed opposite to the semiconductor layers 24a, 24b and 24c through a top gate insulating film 23 located under the semiconductor layers 24a, 24b and 24 c; wherein the structure is formed on an insulating substrate 21 such as a glass substrate. In this embodiment, since the material properties of these insulating films and conductive layers or the manufacturing methods thereof are the same as those in the above-described embodiment (fig. 15), the description thereof in the fourth embodiment is omitted.

In this way, this double-gate type photosensor 10F has a structure in which the first, second, and third double-gate type photosensors are connected to each other and arranged in parallel. The first double-gate type photosensor includes the semiconductor layer 24a, the drain electrode 27a, the source electrode 27b, the top gate insulating film 28, the bottom gate insulating film 23, the top gate electrode 29 and the bottom gate electrode 22, and the semiconductor layer 24a having a channel length L3 and a channel width W as one common channel region. The second dual gate type photosensor includes the semiconductor layer 24b, the source electrode 27b, the drain electrode 27c, the top gate insulating film 28, the bottom gate insulating film 23, the top gate electrode 29, the bottom gate electrode 22, the semiconductor layer 24b having a channel length L4 and a channel width W as one common channel region. The third double-gate type photosensor includes the semiconductor layer 24c, the drain electrode 27c, the source electrode 27d, the top gate insulating film 28, the bottom gate insulating film 23, the top gate electrode 29 and the bottom gate electrode 22, and the semiconductor layer 24c having a channel length L5 and a channel width W as one common channel region.

In particular, the top gate 29 and the bottom gate 22 constituting the first to third double gate type photosensors constitute one common electrode, and have a structure in which the drains 27a and 27c protrude from the common drain row 103 and the sources 27b and 27d protrude from the common source row 104. Therefore, with the above-described drive control method, three double-gate type photosensors connected and arranged to each other can be used as one double-gate type photosensor.

In the double gate type photosensor 10F, the leakage current Ids which varies with the amount of light passing therethrough is generally expressed by the following mathematical expression.

Ids∝W/L3+W/L4+W/L5 ……(3)

Here, in comparison with the double-gate type photoelectric sensor 10A shown in fig. 19A, the source-drain current can be theoretically increased by 3 times by setting the channel length L3-L4-L5-L according to the above equation (3). Therefore, transistor characteristics can be significantly improved.

In the double-gate type photosensor 10F having such a structure, since the semiconductor layers 24a, 24b, and 24c constituting the channel region are successively arranged in parallel in the extending direction of the channel lengths L3, L4, and L5 by allowing each width direction (longitudinal direction) to face each other, the length in the channel width direction of the incident active region in each of the semiconductor layers 24a, 24b, and 24c is represented by W, and the length in the channel length direction of each of the incident active regions is represented by K3, K4, and K5. For example, when K3 is set to K4 to K5, the photosensor can be regarded as a double gate type photosensor in which the length in the channel length direction is set to 3 times (3 × K).

Therefore, the distribution of the light sensing area of each of the semiconductor layers 24a, 24b, and 24c in the channel length direction (vertical direction in FIG. 41; direction y) is at most 3 times that of the double-gate type photosensor. Thus, the distribution range of the light-sensing area can be set to be square.

Therefore, by arranging the double-gate type photosensors 10F in a matrix shape to constitute the photosensor array 100F shown in fig. 41, a photosensor array having a light-receiving portion with a good transistor characteristic and a reading device for reading a two-dimensional image is realized, which further unifies the distribution of light-sensing areas and suppresses distortion occurring when reading a two-dimensional image.

In each of the embodiments, the double gate type photosensors 10A to 10F therein are shown to have a structure in which one to three semiconductor layers are successively arranged in parallel together. However, the present invention is not limited thereto. Therefore, the light receiving sensitivity and the distribution of the light sensing area can be arbitrarily set according to the number of semiconductor layers arranged in series.

In this case, as shown in fig. 21B or fig. 41, when the double-gate type photosensors 10B and 10F are arranged in a matrix shape to constitute photosensor arrays 100B and 100F and are applied to a reading apparatus for reading a two-dimensional image, since light is irradiated from the side of an insulating substrate (glass substrate) 21 to an object through regions Ra and Rb between devices inside a matrix grid, after the regions Ra and Rb between the devices are provided, the number of layers of a semiconductor layer (double-gate type photosensor) which is continuously arranged on a structure region of a light receiving portion needs to be arbitrarily provided in order to sufficiently secure the amount of light irradiated to the object.

Fig. 42 is a schematic view showing a structure of a photosensor array according to another embodiment of the present invention.

As shown in fig. 42, the photosensor array 100G according to the fourth embodiment has one double-gate type photosensor 10G having a structure similar to that of the double-gate type photosensor 10B shown in fig. 21A, and each of the double-gate type photosensors 10G has a so-called triangular arrangement structure in which each of the double-gate type photosensors 10G is arranged at a position of a vertex of an imaginary equilateral triangle continuously disposed on a two-dimensional plane, the equilateral triangle having a side of Psa (Psa: a pitch between the double-gate type photosensors 10A shown in fig. 19).

In this way, the double-gate type photosensors 10A are spaced apart by an equal distance Psp only in two mutually perpendicular directions x and y, as compared with the arrangement of the double-gate type photosensors 10A in the photosensor array 100A shown in fig. 19B. Thus, in the diagonal row direction with respect to the x and y directions in the matrix (appropriate angles other than 0 °, 90 °, 180 ° and 270 °, for example, in the directions of 45 ° and 60 °), the pitches of the dual gate type photosensors 10A in the x and y directions increase and do not coincide (for example, 2 times Psp at 45 °). Therefore, there is a problem that a uniform and highly accurate reading operation cannot be obtained for an object located in the diagonal row direction.

In contrast, in the photosensor array 100G according to one embodiment of the present invention, since the dual-gate type photosensors 10G constituting the light-receiving portions are arranged at the vertex positions of the equilateral triangles continuously arranged on the two-dimensional plane, the dual-gate type photosensors 10G are arranged at equal intervals in the x direction and also arranged at equal intervals in the diagonal row directions (60 °, 120 °, 240 °, and 300 °), so that the pitch between the light-receiving portions is equal to Psa.

Therefore, for the double-gate type photosensors adjacent to each other in the entire circumferential direction, all the double-gate type photosensors are arranged at equal intervals on a two-dimensional plane. Thus, when a two-dimensional image is placed in a diagonal direction with respect to the x and y directions, the two-dimensional image to be read can be read with high accuracy while suppressing distortion at the time of reading the image.

Further, since each of the double-gate type photosensors is arranged in a triangular manner, when the pitch in the x direction is set to the same Psa (Psp) as that of the photosensor in fig. 19B, the pitch Psb in the y direction is expressed by the following equation.

Psb＝Psa×sin 60° ...(4)

In this way, since the pitch Psb in the y direction is shorter than the pitch Psa in the x direction (Psb), the same number of double gate type photosensors 10G can be arranged on the planar area Mc smaller than the planar area Mp of the photosensor array 100A shown in fig. 19B in the y direction, thereby making it possible to reduce the size of the reading device for reading a two-dimensional image. That is, on the same planar area Mp as the photosensor array 100A shown in fig. 19B, the double-gate type photosensors 10G of 1/sin 60 ° (≒ 1.15.15 times) may be arranged, so that it is possible to increase the density.

Although the embodiment structure shown in fig. 21A is used as a double-gate type photosensor constituting each light receiving portion arranged in a triangular manner, it goes without saying that the embodiment structure shown in fig. 19A and 39 and double-gate type photosensors of other structures may also be used.

In the above-described photosensor array, emitted light of light R irradiated from the light source 140 on the glass substrate side of the photosensor array 100M onto an object 50a such as a finger is incident on each double-gate type photosensor 10M by conduction through one transparent insulating film on the region between the devices. This makes it possible to read the light and dark information of the object 50a with high accuracy and in a short time, while reducing the distortion occurring when reading is performed as described above.

Further, since the transistor characteristics in the photosensor array 100M can be greatly improved, the luminance of the light source can be relatively reduced, and the power consumption of the reading apparatus can be greatly reduced.

The electrostatic discharge and contact sensing electrode 31 has one piece of transparent film on the array area As, but may have two electrodes As shown in fig. 43. Here, as shown in fig. 24, the photosensor system includes a light source 140, a photosensor array 100, an electrostatic discharge and contact sensing electrode 31, a bottom gate driver 120, a top gate driver 110, a drain driver 130, and a controller 160. The photosensor system replaces the contact detector 150 with a contact detector 170.

The photosensor system includes a group of photosensor devices 10 arranged in a matrix on the area Aa for photographing a finger printed on the substrate 21, and is located above the light source 140.

The electrostatic discharge and contact sensing electrode 31 is an optically transparent electrode made of ITO (indium tin oxide) or the like and is formed on a photosensor device for eliminating static electricity charged on a finger (human body). Specifically, the electrostatic discharge and contact sensing electrode 31 is formed of two rectangular electrodes (electrodes 31a and 31b) separated by an elongated gap 231 passing near the center of the sensor area. This slit is arranged to pass between the photosensor devices 10. The width thereof is set so that no leak current caused by impurities or the like passes between the electrodes 31a and 31 b. As a result, all the photosensor devices 10 are covered with the electrodes 31a and 31b so as to obtain a uniform image without a moire pattern. Also, in a direction perpendicular to the longitudinal direction of the slit 231 among the surfaces of the two electrodes 31a and 31b, there is only one specific region separating the two electrodes 31a and 31 b. Thus, the electrostatic discharge and contact sensing electrode 31 has a very simple geometry compared to a comb structure. Therefore, the resistance of the electrostatic discharge and the touch sensing electrode 31 can be set very low. Thus, it is possible to effectively eliminate static electricity and prevent breakdown of the photosensor device charged with static electricity.

The contact detector 170 is connected to the electrostatic discharge and contact sensing electrode 31 to discharge static electricity and detect contact of a finger with the electrostatic discharge and contact sensing electrode 31, that is, to detect that the finger is placed on a predetermined photographing position. Specifically, the contact detector 170 is connected to the electrode 31a through the electric line L1, and is connected to the electrode 31b through the electric line L2. The contact detector 170 grounds the electrode 31b through the grounding of the electric line L2, so that the above static electricity is put into the ground through the electrode 31b and the electric line L2. Also, the contact detector 170 supplies a detection signal for detecting that the finger comes into contact with the electrostatic discharge and contact sensing electrode 31 to the electrode 31a through the line L1. When a finger is placed as shown in fig. 43, the electrodes 31a and 31b are electrically connected by the finger, so that the resistance value, the capacitance value, and the like between the electrodes 31a and 31b are changed. The contact detector 170 detects a change in impedance caused by an increased resistance value or capacitance value of the human body between the electrodes 31a and 31b through the electric lines L1 and L2 to detect that the finger has come into contact with the electrostatic discharge and contact sensing electrode 31. After the contact detector 170 detects that the finger is placed at a predetermined photographing position, a photographing start signal for designating start of fingerprint photographing is output to the light source 14 and the photosensor device 12.

In the case of photographing a fingerprint using the photosensor system configured in the above-described manner, the contact detector 170 supplies an alternating-current signal for detection to the electric line L1.

Then, a finger is placed on the electrostatic discharge and contact sensing electrode 31 to cross the slit 231 as shown in fig. 43.

When a finger is placed on the electrode 31 serving as an electrostatic discharge and touches the sensing electrode 31, the electrodes 31a and 31b are electrically connected by the finger. At this time, when static electricity is accumulated on the finger, the static electricity is discharged to the ground through the electrode 31b and the line L2. Then, the detection signal provided by the contact detector 170 leaves the human body through the finger, flows to the electrode 31b, and further flows to the current line L2.

The contact detector 170 detects a change in resistance or capacitance of a human body between the electrodes 31a and 31b including a finger, for example, a change in impedance caused by a change in the level of a detection signal flowing from the electric line L1 to the electric line L2, to detect that the finger has come into contact with the electrostatic discharge and contact sensing electrode 31. Then, the contact detector 170 outputs a photographing start signal to the controller 160.

As described above, the electrostatic discharge and contact sensing electrode is composed of the electrodes 31a and 31b having a simple geometry and extending over the entire sensor area. Thus, it is possible to set the electrostatic discharge and the resistance of the touch sensing electrode 31 to a small value. As a result, the photosensor device 12 can be sufficiently protected from static electricity on a finger (human body), and therefore the photosensor system has sufficiently high reliability. Further, using the electrostatic discharge and contact sensing electrode 31 composed of the two electrodes 31a and 31b spaced by the slit 231, it can be detected that the finger is placed on a predetermined photographing position.

As shown in fig. 44, the diode circuit 151 may be provided in the electric line L1 and/or the electric line L2. The diode circuit 151 is constituted by a pair of diodes connected in anti-parallel, and has one end connected to the electric line L1 or the electric line L2 and the other end grounded.

The diode circuit 151 constructed in the above manner has a non-linear rectification characteristic such that a sudden change in current occurs when the applied voltage exceeds a threshold value. Specifically, in the case where the voltage value Va across the diode circuit is smaller than the threshold voltage Vc (about 0.6V), the diode circuit 151 does not actually allow a current to pass therethrough. That is, when Va is smaller than the threshold voltage Vc, the resistance value of the diode circuit 151 is large. Conversely, in the case where the voltage Va is greater than the threshold voltage Vc, the diode circuit 151 allows a current to pass therethrough. That is, when the voltage Va is larger than the threshold voltage Vc, the resistance value of the diode circuit 151 is small.

For example, in the case where a finger charged with static electricity is in contact with the electrostatic discharge and contact sensing electrode 31, a high voltage (about 10(kV)) is applied to both ends of the diode circuit 151. At this time, static electricity cannot flow to the contact detector 170 but is discharged to the ground through the diode circuit 151 due to the characteristics of the diode circuit 151. As a result, static electricity flows to the contact detector, thereby preventing the contact detector 170 from being affected by the static electricity. On the other hand, when no static electricity is accumulated on the finger, or when the static electricity is discharged, the voltage applied to the diode circuit 151 is very small, and practically no current flows through the diode circuit 151. As a result, the contact detector 170 can read out the impedance change in the same manner as the first embodiment, and can detect that the finger has come into contact with the electrostatic discharge and contact sensing electrode 31.

As shown in fig. 45, the contact detector 150 shown in fig. 24 may be connected to one electrostatic discharge and contact sensing electrode 31. Also, as shown in fig. 46, the slit 231 may be curved. Alternatively, as shown in fig. 47, the electrode 31a covers the entire surface of the sensor region Aa, so that a finger can be accurately brought into contact with the electrode 31a when the electrode 31a is positioned on the photosensor device 12.

As shown in fig. 48, the diode circuit 151 may be configured by connecting two rows of diodes in reverse parallel, each row of diodes including a plurality of diodes connected in series. Further, a switching circuit for changing the number of diodes connected in series is provided so that the number of diodes located between the electrostatic discharge and contact sensing electrode 31 (electric lines L1, L2, and L3) and the ground point can be changed. However, the number of diodes between the electrostatic discharge and touch sensing electrode 31 and the ground should be synchronized across the two rows of diodes. When the threshold voltage Vc of the combined diodes is about 0.6(V), the threshold voltage of n diodes connected in series becomes about 0.6 × n (V). At this time, by changing the number of diodes connected in series, it will be possible to change the threshold voltage value as a reference value for determining whether or not to supply a current to the contact detector 170.

Other improvements and modifications will readily occur to those skilled in the art. Accordingly, the scope of the present invention is not limited to the specific illustrations and representative embodiments shown and described herein. Accordingly, various modifications are possible without departing from the spirit and scope of the invention as defined by the following claims.

Claims (15)

1. A photosensor array comprising:

a plurality of photoelectric conversion elements arranged apart from each other in a predetermined direction, each photoelectric conversion element including:

a semiconductor layer having an incident active region on which excitation light is incident;

a source electrode and a drain electrode provided at both ends of the semiconductor layer, respectively;

a first gate electrode provided below the semiconductor layer through the first gate insulating film; and

a second gate electrode provided over the semiconductor layer through a second gate insulating film;

a source terminal connected to a source of the photoelectric conversion element;

a drain terminal connected to a drain of the photoelectric conversion element;

a first gate terminal connected to a first gate of the photoelectric conversion element; and

a second gate terminal connected to a second gate of the photoelectric conversion element,

the second gate electrode provided in the photoelectric conversion element is composed of a first transparent electrode layer, and

at least one of the source terminal, the drain terminal, and the first gate terminal has a first transparent electrode layer.

2. The photosensor array according to claim 1, wherein an uppermost layer of at least any one of the source terminal, the drain terminal, and the first gate terminal is constituted by a first transparent electrode layer.

3. The photosensor array according to claim 1, wherein the photosensor array includes electrostatic discharge and contact sensing electrodes provided over the photoelectric conversion elements via insulating films, and

at least one of the source terminal, the drain terminal, the first gate terminal, and the second gate terminal is formed using a second transparent electrode layer that forms an electrostatic discharge and contact sensing electrode.

4. The photosensor array of claim 1, wherein the semiconductor layer extends under the source and drain electrodes, the wiring connecting the source and source terminals, and the wiring connecting the drain and drain terminals.

5. The photosensor array of claim 1, further comprising

A drain driver, a first gate driver, and a second gate driver, and wherein the photoelectric conversion element is connected with the drain driver, the first gate driver, and the second gate driver through the drain terminal, the first gate terminal, and the second gate terminal.

6. The photosensor array of claim 1, wherein the semiconductor layer has a plurality of incident active regions, and the regions are aligned in a direction parallel to the channel of the semiconductor layer.

7. The photosensor array of claim 1, wherein the source and drain are opaque with respect to the excitation light.

8. The photosensor array of claim 1, wherein the photoelectric conversion elements are arranged in a triangular configuration.

9. The photosensor array according to claim 1, wherein the semiconductor layer of each photoelectric conversion element is divided into a plurality of layer positions such that the source and drain electrodes are provided respectively at the layer positions, and the source electrodes are connected to each other and the drain electrodes are connected to each other.

10. The photosensor array according to claim 9, wherein the semiconductor layers of the photoelectric conversion elements are aligned in a channel direction parallel to the semiconductor layers.

11. A method of fabricating a photosensor array, comprising:

forming a first gate electrode and a first gate substrate pad connected to the first gate electrode on the insulating film;

forming a first gate insulating film on at least the first gate electrode and the first gate base pad, followed by forming a semiconductor layer having a predetermined configuration over the first gate electrode, the semiconductor layer being for generating carriers with the excitation light;

forming a first opening portion in the first gate insulating film for exposing the first gate base pad:

forming source-drain electrodes provided at both ends of the semiconductor layer, respectively, a drain substrate pad connected to the drain electrode, and a first gate terminal lower layer on the first gate substrate pad via the first opening portion;

forming a second insulating film on at least the first gate terminal lower layer, the source-drain and the drain substrate pad, followed by forming a second opening portion in the second insulating film for exposing at least one of the first gate terminal lower layer and the drain substrate pad; and is

A second gate electrode having a predetermined configuration and a second gate base pad connected to the second gate electrode are formed on the second insulating film, while at least one of a first gate terminal upper layer connected to the first gate terminal lower layer through the second opening portion and a drain terminal upper layer connected to the drain base pad is formed.

12. The method of manufacturing a photosensor array of claim 11, wherein at least the first gate terminal upper layer or the drain terminal upper layer is composed of the same transparent electrode layer as the second gate.

13. A method of manufacturing a photosensor array according to claim 11 comprising:

forming a protective insulating film on the second insulating film, followed by forming a third opening portion in the protective insulating film for exposing at least any one of the first gate terminal upper layer, the drain terminal upper layer and the second gate base pad; and is

An electrostatic discharge and contact sensing electrode having a predetermined configuration is formed on the protective insulating film, and at least one of a first gate terminal uppermost layer on the first gate terminal upper layer, a drain terminal uppermost layer on the drain terminal upper layer, and a second gate terminal upper layer on the second gate substrate pad is formed through a third opening portion.

14. The method of manufacturing a photosensor array of claim 13, wherein the uppermost layer of the first gate terminal or the uppermost layer of the drain terminal or the upper layer of the second gate terminal is composed of the same transparent electrode layer as the electrostatic discharge and contact sensing electrode.

15. The method of manufacturing a photosensor array of claim 11, where the semiconductor layer is provided and extended under the routing layer connecting at least the source and drain electrodes.