GB987858A - Improvements in or relating to electric signal synchronising equipment - Google Patents

Abstract

987,858. Multiplex pulse signalling. GENERAL ELECTRIC CO. Ltd. Oct. 10, 1962 [Oct. 11, 1961], No. 36500/61. Heading H4L. Relates to an arrangement for synchronizing the transmitter and receiver in a pulse signalling system, as described, a twelve-channel time division multiplex pulse code modulation system. At the transmitter sample amplitudes are coded using a seven digit binary code, an eighth digit being added at the beginning of each code group to provide synchronizing information, each group of eight digits forming a channel group. Thus twelve digits in each frame provide synchronizing information, the first eleven synchronizing digits being " 0's " and the twelfth a " 1." In addition, supervisory signals may be transmitted by using the first digit in each channel group every eighteenth frame. When this signalling information is to be transmitted the first digit of each channel group is made a " 0 " for the immediately preceding frame. At the receiver the incoming pulse signal is supplied via terminal 1 to an AND gate 21. A sinusoidal timing signal at the basic pulse repetition frequency (768 kc/s.) is derived from the incoming signal and supplied via a terminal 2 to a tapped delay line 3. One output of the delay line is supplied via an inverter 4 to a bistable circuit 5, and the other output is supplied via an inverter 19 providing waveform A, Fig. 2, to pulse generator 20 generating pulses B at a repetition frequency of 768 kc/s. The output from generator 20 is supplied to gate 21 which receives its other input from a gate 17 which is controlled by a frequency divider 10 to 15 to provide pulses C of 1À3 microseconds spaced by 10À4 microseconds so that each eighth pulse from generator 20 coincides with a pulse from gate 17. Waveform D represents the incoming signal showing a synchronizing pulse in channel 12, the remaining pulses being omitted for simplicity. Assuming correct synchronism the gate 21 will provide an output E comprising pulses of 0À3 microseconds duration spaced by 125 microseconds only when the synchronizing pulse is present, this signal being supplied to a gate 22. The gate 22 when synchronism is correct is inhibited by an input F from inverter 29 derived from the frequency divider 10 to 15 via gates 17 and 18. The tapped delay line 3 provides the necessary time correction to ensure this condition. The output pulse E from gate 21 is also supplied to a pulse generator 35 supplying a pulse of longer duration than the input pulse to inhibit a gate 33 so that the inverter circuit 30 cannot operate pulse generator 34 to supply a signal to gate 36 in coincidence with the waveform E. When supervisory signals are transmitted there are two frames without synchronizing information and during the first of these frames there will be no pulse supplied by the gate 21 so that signals can pass from the inverter 30 to operate the pulse generator 34. A long pulse will pass via gate 38 to inhibit gate 24 so that it will not pass any signal supplied during the next frame. During this next frame a pulse also will be supplied to the gate 36 so that any pulse passed by the gate 21 will pass the gate 36 to the terminal 37. These pulses constitute the supervisory signals. If the synchronizing is incorrect the gate 21 will open on other than the first pulse position and is likely to supply several pulses to the gate 22 during each frame and some or all of these pulses will be passed via inverter 23 to the gate 24. Assuming that gate 24 is receiving no inhibit pulse, pulses will be suppled to integrator 25 and gate 28. A reference signal from source 27 supplied to the detector 26 ensures that the detector 26 supplies a pulse to gate 28 when for example three pulses have been supplied to the integrator 25 during an interval equal to a few frames. Thus a further pulse supplied by the gate 24 will cause gate 28 to supply a pulse to a bi-stable circuit 8 to reverse its condition. This shifts the signal derived from the gate 9 and frequency divider 10 to 15 by one pulse position relative to the incoming signal and the process will be continued until synchronism is restored. Circuits 25, 26, 27 prevent loss of synchronism due to an occasional spurious pulse. Normally the gate 38 operates to block the gate 24 during the transmission of supervisory signals but if synchronism is lost it is necessary that the gate 24 should not be blocked. Therefore each time circuit 8 reverses its condition a pulse from differentiating circuit 39 or 40 is supplied via gate 41 to cause pulse generator 42 to supply a long pulse to inhibit the gate 38, the duration of the pulse being such as to give the equipment time to get back into synchronism.