GB977806A - A linear pulse width modulator - Google Patents

Abstract

977,806. Pulse modulation circuits; semi-conductor circuits. FERGUSON RADIO CORPORATION Ltd. June 5, 1963 [June 13, 1962], No. 22795/62. Headings H3T and H4L. [Also in Division G3] A pulse width modulator comprises a pulse generator 10, Fig. 1, having a capacitor which is charged (or discharged) by each of a succession of clock pulses and thereafter discharges (or charges) at a rate determined by the difference between the modulating voltage and a negative feedback voltage derived by smoothing the output pulses produced by the pulse generator 10 in a low-pass filter 18 and supplying the two voltages to a comparator 14. In one embodiment, Fig. 2, the pulse generator comprises a transistor VT1 and the output signal is supplied via an emitter-follower VT2, a diode D3 preventing reverse biasing of VT2. Narrow, positive-going clock pulses are supplied via capacitor C1 so that at each clock pulse capacitor C2 is charged from capacitor C1 via diode D2 causing transistor VT1 to cut off. At the end of a clock pulse diode D2 is reverse-biased and C1 recharges via diode D1. C2 is discharged slowly during each clock pulse period via transistor VT3 (the voltage comparator) until transistor VT1 conducts again, the discharge time of C2 being dependent on the voltage fed to the emitter via the low-pass filter 18 and the modulating potential applied to the base of the transistor. In a modification, Fig. 3, in which corresponding components have references as in Fig. 2 a transistor VT4 co-operates with transistor VT3 to form a long-tailed pair with a common resistor R6 returned to a potential -V2 more negative than the supply -V1, the modulating signal being applied to the base of VT3 as before. Diodes D4, D5, D6 limit bottoming in VT3 to reduce the effects of excess carrier storage and R5 allows VT3 to operate at a collector current well above its thermally dependent leakage component. Sinusoidal or square wave clock signals are supplied via an inverter-squarer VT5 in which D8, R6 and R7 limit saturation. VT5 is caused to be alternately conducting and non-conducting by the application of the clock signal and when it conducts D9 conducts so that capacitor C6 discharges and causes transistor VT6 to conduct. When VT6 conducts capacitor C1 charges capacitor C2 via D2 and transistor VT1 is reverse-biased. When transistor VT5 bottoms, current in C6 and VT6 ceases, C1 re-charges to -V1 volts through R10 and diode D1 and is discharged slowly by transistor VT3 defining the duration of the negative-going output pulse. When VT5 is driven " off " by the clock signal diode D9 disconnects C6 from the collector of transistor VT5. Capacitor C6 recharges to - V1 volts through diode D10 and resistor R9. The system may be used for data transmission and recording and also may be used for D.C. voltage regulators or controllers (see Division G3). Specification 790,941 is referred to.