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GB911051A - A circuit arrangement for checking the validity of binary numbers - Google Patents

A circuit arrangement for checking the validity of binary numbers

Info

Publication number
GB911051A
GB911051A GB7829/61A GB782961A GB911051A GB 911051 A GB911051 A GB 911051A GB 7829/61 A GB7829/61 A GB 7829/61A GB 782961 A GB782961 A GB 782961A GB 911051 A GB911051 A GB 911051A
Authority
GB
United Kingdom
Prior art keywords
binary
digit
code
stored
combination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB7829/61A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympia Werke AG
Original Assignee
Olympia Werke AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympia Werke AG filed Critical Olympia Werke AG
Publication of GB911051A publication Critical patent/GB911051A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0763Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Storage Device Security (AREA)

Abstract

911,051. Digital electric calculating apparatus. OLYMPIA WERKE A.G. March 3, 1961 [April 11, 1960], No. 7829/61. Class 106 (1). In an arrangement for checking whether a combination of binary digits represents a coded digit in a binary excess code, sections of the digit positions which have combinations of binary digits occurring only in numbers in the code, are checked. As described, for an excess twenty-seven code, in which a decimal digit n is represented as the binary number n+27, the representation for the digits 0-9 are shown in Fig. 2, the section comprising the first four code positions being characterized by the combination 0111 for digits 1-4 and 1000 for digits 5-8. A number to be checked is stored in a six-plate register comprising bi-stable stages FF 1 -FF 6 , the " 0 " and " 1 " outputs from the stages being applied to " and " gates U 1 -U 4 . The gate U 1 produces an output if 011011, representing decimal zero, is stored, the gates U 2 , U 3 producing outputs if the combination 0111 and 1000 respectively are stored in flip-flops FF 1 - FF 4 and the gate U 4 producing an output if 100100, representing decimal nine is stored. The outputs of the gates U 1 -U 4 are connected via an inverter I 1 , to a further " and " gate U 5 supplied with synchronizing pulses at P. The arrangement is such that when a binary digit combination to be tested is stored in the stages FF 1 -FF 6 , the application of a synchronizing pulse at P causes an output at A if and only if the binary digit combination does not represent a decimal digit 0-9 in the excess twenty-seven code.
GB7829/61A 1960-04-11 1961-03-03 A circuit arrangement for checking the validity of binary numbers Expired GB911051A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DEO7341A DE1115490B (en) 1960-04-11 1960-04-11 Procedure and arrangement for checking the validity of information presented in a binary excess key

Publications (1)

Publication Number Publication Date
GB911051A true GB911051A (en) 1962-11-21

Family

ID=7351121

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7829/61A Expired GB911051A (en) 1960-04-11 1961-03-03 A circuit arrangement for checking the validity of binary numbers

Country Status (4)

Country Link
US (1) US3091391A (en)
CH (1) CH387988A (en)
DE (1) DE1115490B (en)
GB (1) GB911051A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745605A (en) * 1986-08-19 1988-05-17 Amadahl Corporation Control word error detection and classification

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL197751A (en) * 1954-06-04
US2857100A (en) * 1957-03-05 1958-10-21 Sperry Rand Corp Error detection system

Also Published As

Publication number Publication date
US3091391A (en) 1963-05-28
CH387988A (en) 1965-02-15
DE1115490B (en) 1961-10-19

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