GB840711A - Improvements in or relating to electric relay arrangements - Google Patents

Abstract

840,711. Protective cut-out arrangements. ADAMSON, C., and WEDEPOHL, L. M. Aug. 7, 1956 [May 6, 1955; Dec. 1, 1955], Nos. 13153/55 and 34392/55. Class 38 (5). A directional or distance relay arrangement operative in accordance with a phase comparison of two A.C. quantities dependent upon the current and the voltage in a main electric circuit C, comprises a transistor network including two transistors to which the two A.C. quantities are respectively applied, means for energizing the two transistors from a unidirectional supply in parallel with one another whereby with zero energization from the two A.C. quantities the two transistors would both be in the same state, and means responsive to a change of state of both transistors for controlling the operation of a relay device G. In the directional relay arrangement of Fig. 1, the emitters A<SP>2</SP>, A<SP>5</SP> of the two transistors are connected to a positive bus-bar B and the collectors A<SP>3</SP>, A<SP>6</SP> are connected to a negative bus-bar B<SP>2</SP>. As the emitters are given a small positive bias by a battery B<SP>4</SP> with respect to the bases A<SP>1</SP>, A<SP>4</SP> of the transistors, both transistors conduct with zero energization from the A.C. quantities. The current quantity is derived from a current transformer C<SP>2</SP> and a phase-shifting impedance D connected between the bus-bar B and the base A<SP>4</SP> of the second transductor, the A.C. potential applied to the base causing the second transistor to be cut-off for nearly the whole of the positive half-cycle of the current wave. The voltage quantity is derived from a voltage transformer C<SP>3</SP> and a phase-shifting transformer E whose secondary winding is loaded by a capacitance E<SP>1</SP> and resistance E<SP>2</SP>, the output of the transformer E being applied to the base of an auxiliary transistor E<SP>3</SP> which behaves as a switch and conducts when its base is negative relative to its emitter. Thus a load transformer E<SP>5</SP> produces a short pulse only when the potential of the base of the transistor E<SP>3</SP> changes sign, the resulting pulses being applied to the base A<SP>1</SP> of the first transistor which ceases to conduct only when a positive pulse is applied. When the phase relationship of the two A.C. quantities is such that the relay arrangement is to be operated, the positive pulses are applied to the first transistor during the periods in which the positive half-cycles are applied to the second transistor, so that for the duration of each pulse both transistors are non-conducting with the result that a further transistor F becomes conducting and charges a capacitor F<SP>1</SP>. This capacitor slowly discharges between the pulses and causes a transistor G<SP>1</SP> to conduct to energize the relay G. In the modified arrangement of Fig. 4 (not shown) the two transistors are non- conducting with zero energization by the A.C. quantities and are both conducting to produce relay operation if negative pulses occur during the negative half-cycles. The A.C. quantity applied to the second transistor may be a vectorial combination of the current and voltage so that the relay arrangement may function as a distance relay with a mho, offset mho or ohm characteristic, Fig. 5 (not shown). In Fig. 7 (not shown) the two A.C. quantities are directly applied to the two transistors of the network and the phase comparison is effected by measuring the length of time in each cycle during which the two quantities have the chosen polarity. Other arrangements include the use of a polarized relay connected between two auxiliary transistors, Fig. 8 (not shown), the use of transistor integrating circuits and level detectors between the transistor network and relay device, Fig. 9 (not shown), and the use of a thyratron as the relay device, Figs. 10 ... 12 (not shown). Figs. 13-15 (not shown) illustrate how several of the above arrangements are made insensitive to D.C. components in the main circuit by duplicating the transistor network, one network functioning on the positive halfcycles and the other on the negative half-cycles. Various input circuits to give the relay arrangement the desired characteristic are shown and compensation may be provided to remove the error introduced by the use of a bias voltage.