GB2635791A - Dimmer circuit improvement - Google Patents

Abstract

A control circuit 100 and a method for generating a control signal 11 for controlling a switch 60, the switch for controlling current applied to a load 50 from a source of mains power, in which the control circuit comprises a processor 10 for outputting the control signal and for receiving a connection from a neutral terminal of the mains power source, such that the control signal is generated in accordance with the frequency of the mains power. In particular, a virtual load zero crossing signal is generated and used as the control signal for controlling the switch, the virtual load zero crossing signal having its phase locked with the frequency of the mains power. This arrangement provides a more robust system that is less susceptible to missing mains zero crossing signals and transient signals on the mains power lines.

Description

DIMMER CIRCUIT IMPROVEMENT

TECHNICAL FIELD

[0001] The present application relates to dimming of electrical loads. PRIORITY [0002] This application claims priority from Australian Provisional Patent Application Number 2023901383 entitled "Dimmer Circuit Improvement" and filed on 8 May 2023. The entire content of this application is hereby incorporated by reference.

BACKGROUND

[0003] Dimmer circuits are used to control the power provided to an electrical load such as a light or electric motor from a power source such as mains or supply power. Such circuits often use a technique referred to as phase controlled dimming. This allows power provided to the load to be controlled by varying the amount of time that a switch connecting the load to the power source is conducting during a given cycle.

[0004] For example, if voltage provided by the power source can be represented by a sine wave, then maximum power is provided to the load if the switch connecting the load to the power source is on at all times. In this way, the total energy of the power source is transferred to the load. If the switch is turned off for a portion of each cycle (both positive and negative), then a proportional amount of the sine wave is effectively isolated from the load, thus reducing the average energy provided to the load. For example, if the switch is turned on and off half way through each cycle, then only half of the power will be transferred to the load. This technique will be well understood by the person skilled in the art. In leading edge dimmer topologies for controlling inductive loads, it is generally necessary to allow the prevailing half-cycle load current to fall to near-zero levels, before returning the switch to the off-state, in order to avoid excessive inductive voltage spiking levels, which can cause damage to the electrical components of the dimmer circuit and the load. Turning off the switch while there is any appreciable level of current causes a sudden rise in the voltage appearing across the load.

[0005] As will be understood, the greater the rate of change in current i through the load, the greater the voltage spike occurring. It follows then that the greater the current at the time of turning off the switch, which causes the current to fall to zero in a very short space of time, the greater the rate of change of current and therefore the greater the voltage spike induced. Accordingly then, it is desirable to turn off the switch when the magnitude of current is nearly zero.

[0006] One approach to this is to detect when the load current is crossing the "zero point", that, is turning from one polarity to the other. This is known as "load zero crossing". At the zero point, the load current is zero, or at least small. In these applications, a zero crossing detector is placed in series with the load which is connected to the mains power supply to provide zero-crossing information to the dimmer controller of the dimmer circuit.

[0007] This approach however, still suffers from a number of disadvantages, including instability when the load has a high impedance. This creates instability in the control system of the dimmer causing the light (when the load is a light for example) to shimmer or flicker rather than changing smoothly.

[0008] Furthermore, there is a limitation on the dimming range able to be achieved by the dimmer.

SIJMNIARY

[0009] According to a first aspect, there is provided a control circuit for generating a control signal for controlling a switch, the switch for controlling current applied to a load from a source of mains power, the control circuit comprising a processor for outputting the control signal and for receiving a connection from a neutral terminal of the mains power, wherein the processor is configured to generate the control signal in accordance with the frequency of the mains power.

[0010] In some embodiments, the control circuit generates a virtual load zero crossing signal as the control signal for controlling the switch, the virtual load zero crossing signal having its phase locked with the frequency of the mains power.

[0011] In some embodiments, the control circuit comprises a Phase Locked Loop (PLL) for generating the virtual zero crossing signal.

[0012] In some embodiments, an input of the PLL is electrically connected to the neutral line of the mains power.

[0013] According to another aspect, there is provided a method of controlling a switch for controlling current applied to a load from a source of mains power, wherein the switch is controlled in accordance with the frequency of the mains power.

[0014] In some embodiments, a mains zero crossing signal is obtained from the mains power obtained from a neutral terminal of the main power.

[0015] In some embodiments, a virtual load zero crossing signal is obtained from the mains zero crossing signal.

[0016] In some embodiments the virtual load zero crossing signal is applied to the input of a Phase Locked Loop (PLL) to provide the control signal for controlling the switch.

[0017] According to another aspect, there is provided a machine readable medium containing instructions to cause a machine to carry out the method of the other aspect.

BRIEF DESCRIPTION OF DRAWINGS

[0018] Embodiments of the various aspects described herein will be detailed with reference to the accompanying drawings in which: [0019] Figure 1 -shows a generalised system block diagram of a control circuit according to one aspect; [0020] Figure 2 -shows a block diagram of a generalised embodiment of the control circuit of Figure 1; [0021] Figure 3 -shows a general flow diagram of the conversion of the mains zero crossing signal derived from the mains frequency into a virtual load zero crossing signal; [0022] Figure 4A -shows an illustration of how the mains voltage from the neutral terminal is converted into a square wave digital output signal which provides a mains zero crossing MZC digital level signal; [0023] Figure 4B -shows how the MZC digital level signal obtained from Figure 4A is processed to provide the MZC signal; [0024] Figure 4C -shows an example of the MZC signal; [0025] Figure 4D -shows the MZC signal of Figure 4C input to the PLL of the controller to output the stable virtual zero crossing; [0026] Figure 4E -shows a synthesized virtual zero crossing signal; [0027] Figure 5A -shows an example circuit diagram of the power supply and mains zero crossing blocks of Figure 2; [0028] Figure 5B -shows an example circuit diagram of the processor of Figure 2; [0029] Figure SC -shows an example circuit diagram of the Mosfet driver of Figure 2; [0030] Figure 5D -shows an example circuit diagram of the switch of Figure 2; [0031] Figure 6 -shows example waveforms of various parts of the circuit of Figures 5A to SD; [0032] Figure 7A -shows a first step of a method according to one aspect; [0033] Figure 7B -shows another step of the method; [0034] Figure 7C -shows another step of the method; [0035] Figure 7D -shows another step of the method; and [0036] Figure 8 -shows a flowchart of the method steps of Figures 7A -7D carried out together.

DESCRIPTION OF EMBODIMENTS

[0037] Various embodiments will now be described in detail in accordance with the accompanying drawings.

[0038] Figure 1 shows a generalised system block diagram of a control circuit 100, such as a dimmer circuit, for controlling the current applied to a load 50 as shown in Figure I. It will be appreciated that Figure I shows the control circuit 100 in an exemplary arrangement connected to the load 50 and to the mains power. These elements do not form part of the control circuit itself.

[0039] The control circuit 100 comprises a switch 60 for controlling the load current applied to the load 50. The switch 60 is controlled in accordance with a control signal 1 I generated by a processor 10 within the control circuit I 00.

[0040] As can be seen in Figure 1, the load current is applied to the load via the active terminal of the mains power (or supply power), and the switch 60 is connected to the load in series with the load current so as to be able to switch the load current in and out as will be understood by the person skilled in the art. ).

[0041] It will be understood that, in some countries, the mains, or supply power, is provided as an alternating current (AC) electrical signal of about 240V (for example between about 220V and 260V) and about 50Hz frequency. In other countries, mains or supply power is provided as an AC signal of between about 100V and 130V. Some systems use a frequency of about 50Hz while others use a frequency of about 60Hz.

[0042] In this aspect, the neutral terminal of the mains power is connected to an input of the control circuit, and is electrically input to the microprocessor 10. From this mains power signal, the control circuit is able to derive the frequency of the mains power signal as will be described in more detail below. According to this aspect, the control signal I l is generated in accordance with the frequency of the mains power circuit. In this aspect, the control signal is not generated in accordance with the load current zero crossing obtained from a detection of the load current, as in traditional arrangements.

[0043] Accordingly then, there is provided a control circuit 100 for generating a control signal 11 for controlling a switch 60, the switch for controlling current applied to a load 50 from a source of mains power, the control circuit 100 comprising a processor 10 for outputting the control signal 11 and for receiving a connection from a neutral terminal of the mains power, wherein the processor is configured to generate the control signal 11 in accordance with the frequency of the mains power.

[0044] Figure 2 shows a block diagram of a generalised embodiment of the control circuit of Figure 1. In this arrangement, control circuit 100 comprises a power supply 8, which derives power from the mains power to provide power to the various components of the control circuit. Also provided is a zero crossing detector 9 which receives as an input, the mains power signal from the neutral terminal, and provides its output to the controller or processor 10. Controller 10 generates and outputs control signal 11 which in this arrangement is used to control MOSFET DRIVER 7 for driving MOSFETS 61, 62, which provide the switch 60. Switch 60 of control circuit 100 is seen connected in series with load 50 to control the load current from the active terminal applied to the load 50 from the mains power source.

[0045] Figure 3 shows a general flow diagram of the conversion of the mains zero crossing signal derived from the mains frequency into a virtual load zero crossing signal, which in one form, provides the control signal 11 that controls the switch 60.

[0046] In this aspect, the mains zero crossing signal is provided by the zero crossing block 9 (see Figure 9) and input to the processor 10. The processor is configured to provide a Phase Locked Loop (PLL) which comprises a phase comparator 6a, low pass filter 6b, loop gain 6c and oscillator 6d.

[0047] In this arrangement, the input zero crossing signal provided by the zero crossing block 9 is processed through the PLL to provide the output signal 11 as a virtual load zero crossing. The output signal 11 is also re-input into the PLL so as to effectively lock the phase of the virtual load zero crossing signal to the frequency of the mains power. The function and operation of a PLL will be understood by the person skilled in the art and will not be detailed herein.

[0048] Accordingly, in this aspect, the control signal I I is provided as a virtual load zero crossing signal and negates the need to obtain a direct measurement of the load zero crossing signal as required in traditional arrangements.

[0049] Figures 4A to 4E illustrate in more detail an example of how the mains power signal is converted to a mains zero crossing signal (MZC) for use as an input to the PLL 6 and then to a virtual load zero crossing signal.

[0050] In Figure 4A, the mains voltage from the Active-Neutral terminal is converted into a square wave digital output signal which provides a mains zero crossing MZC digital level signal. In some embodiments, a comparator can be utilized to transform the negative half cycle of the AC mains sinusoidal wave into a square wave. The threshold voltage for the comparator is, in some embodiments, set to 30V, and when the AC mains voltage surpasses this level, the output of the comparator goes high. Conversely, when the AC mains voltage drops below 30V, the output of the comparator goes low. By employing this method, the zero crossing of the AC mains can be accurately detected. Other methods of converting the negative half cycle of the AC mains sinusoidal wave into a square wave may be used as will be understood by the person skilled in the art.

[0051] In Figure 4B, the MZC digital level signal obtained from Figure 4A is processed to provide the MZC signal that is input into the controller 10. This signal is shown in Figure 4C.

[0052] It will be noted that the signal shown below the Mains Zero Crossing MZC Digital Level signal in Figure 4B is the hardware zero crossing signal and is merely provided here to illustrate the "Delta Phase" (see pseudocode below) and the conduction time (see further below). It will be understood that this hardware zero crossing signal is not used for dimming in this application. Rather, the stable virtual load zero crossing signal derived for MZC is used for the dimming. The hardware ZC is unstable and can be susceptible to load impedance and inrush current. As previously stated, according to one aspect described herein, the virtual zero crossing signal is used instead of the hardware zero crossing signal.

[0053] In Figure 4C, the previously obtained MZC generates pulses for every half mains cycle, which occurs every 20ms. To perform dimming operations, phase cutting must occur in both the positive and negative half cycles. To accomplish this, the MZC obtained from the hardware in Figure 4A is input into a frequency doubler, which serves as the reference for the conduction time (e.g. l Oms for a 50Hz mains signal) in the future. Again, it will be appreciated that this signal is not phase-aligned to the Load zero crossing and is also susceptible to missing MZC and transients on the line.

[0054] Figure 4D shows the MZC signal of Figure 4C input to the PLL 6 of the controller 11 as previously described with reference to Figure 3, to output the stable virtual zero crossing which is synchronised with the actual load zero crossing. This is provided as the control signal I1 for controlling the switch 60.

[0055] The signal depicted in Figure 4E synthesizes the virtual zero crossing, which effectively replaces the problematic hardware load zero crossing. This output is synchronized with the mains frequency and is not affected by missing mains cycles. The MCU utilizes this timing parameter to regulate the final switch for dimming purposes.

[0056] Figures 5A to 5D show actual circuit diagrams of one example embodiment for providing the power supply 8 and mains zero crossing module 9 (Figure 5A), the controller 10 (Figure 5B), the MOSFETT Driver 7 (Figure 5C) and the switch 60 (Figure 5D). The operation of these circuits will be understood by the person skilled in the art given these circuit schematics and need not be explained herein.

[0057] It will also be appreciated that these circuits are examples only and that any other suitable arrangement can be used, including via components that can be purchased on shelf to perform these functions, as will be understood by the person skilled in the art.

[0058] The following is an example of pseudocode that provides for the operation of the controller 11 to effect the method of the various aspects of the present application: initialize main_timer to zero initialize MZC 10 to capture main_timer count on rising edge initialize VZC to capture main_timer count on rising edge //Virtual zero crossing capture initialize DELTA_PHASE to HW phase difference between MZC -ZC time initialize phase_error to DELTA_PHASE initialize phase_error_LPF to DELTA_PHASE initialize COND_MAX to 10ms //for 50Hz mains if (MZC interrupt) { set mzc_ref to main_timer if (VZC compare_interrupt){ set vzc_ref to main_timer l'S?.:Ie the Ieekd:v dse deede-e.

if (MZC polarity is positive) { set VZC compare register to trigger interrupt at (mzc_ref + DELTA_PHASE + phase_error_LPF) set phase_error equal to (mzc_ref -vzc_ref -DELTA_PHASE) }else{ set VZC compare register to trigger interrupt at (mzc_ref + COND_MAX + DELTA_PHASE + phase_error_LPF) set phase_error equal to (mzc_ref + COND_MAX -vzc_ref -DELTA_PHASE) g:ee l.s -:.se: end s ryi,:c.

set phase_error_LPF to (low_pass_filter(phase_error)* LOOP_GAIN) set VZC_active to true if (conduction time interrupt) { if (TE_MODE) turn off MOSFET if (LE_MODE) turn on MOSFET DELIA PHI>, rjr\l/3.. CC,S:C hr/r: CUNLUVEAX, loop (mcu is active) { if (VZC_active is true) { if (TE_MODE) { turn on MOSFET SET main_timer to trigger interrupt at main_timer + conduction time if (LE_MODE) turn off MOSFET SET main_timer to trigger interrupt at main_timer + (COND_MAX -conduction time) set VZC_active to false [0059] It will be appreciated that this is only one example and any other suitable code could be used to effect the required operation.

[0060] Several advantages are provided by the aspects described herein. One advantage provides a much more stable control circuit or dimmer circuit 100 that is tolerant to missing a mains zero crossing that might occur when there is a large in-rush current or surge in the AC mains network.

[0061] Figure 6 shows some waveforms measured at various points in the dimmer circuit. In particular, Figure 6 illustrates what can happen on a typical AC mains signal. For example, the MZC pulse train could have a missing cycle due to interference. The pink trace (MZC) shows, a cycle that is missing. The blue trace(Load Zero crossing) shows, a traditional dimming method that experiences a glitch and stops working.

[0062] In another advantage, the stability in general of the dimmer is enhanced due to the very stable reference provided by the virtual load zero crossing locked to the frequency of the mains power signal and is not susceptible to minor variations in the load zero crossing as exhibited in traditional systems.

[0063] In another advantage, because there is no requirement for a load current zero crossing detector and associated components, the resulting design of the present application requires fewer parts. This provides potential cost savings and also allows the dimmer circuit to be smaller.

[0064] In yet another advantage, because no circuitry (traditionally required for a load current zero crossing detector) in series with the load is present to share current with the load, the load is able to be dimmed across the full conduction range.

[0065] As shown in Figure 7A, according to another aspect, there is also provided a method of controlling a switch for controlling current applied to a load from a source of mains power, wherein in step 801, the switch is controlled in accordance with the frequency of the mains power.

[0066] In some aspects, as shown in Figure 7B, in step 802, the mains zero crossing signal is obtained from the mains power obtained from a neutral terminal of the main power.

[0067] In some aspects, as shown in Figure 7C, in step 803, a virtual load zero crossing signal is obtained from the mains zero crossing signal.

[0068] In some aspects, as shown in Figure 7D, in step 804, the virtual load zero crossing signal is applied to the input of a Phase Locked Loop (PIT.) to provide the control signal for controlling the switch.

[0069] Figure 8 shows a flow chart of the method 800, of controlling a switch for controlling current applied to a load from a source of mains power, comprising, in step 801, controlling the switch in accordance with the frequency of the mains power, then in step 802, obtaining a mains zero crossing signal from the mains power obtained from a neutral terminal of the mains power, then in step 803, obtaining a virtual load zero crossing from the mains zero crossing signal, and then in step 804, applying the virtual load zero crossing signal to the input of a Phase Locked Loop (PLL) to provide the control signal for controlling the switch.

[0070] Those of skill in the art would understand that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0071] Information, signals, bits, symbols, and chips may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0072] Those of skill in the art would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software or instructions, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope as claimed.

[0073] For example, the Phase Locked Loop described herein may be implemented in software on the controller 10 or may be provided by a separate processor or may be provided by discrete hardware components to provide the desired function, or a combination or partial combination of any of these.

[0074] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. For a hardware implementation, processing may be implemented within one or more application specific integrated circuits (AS1Cs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof Software modules, also known as computer programs, computer codes, or instructions, may contain a number a number of source code or object code segments or instructions, and may reside in any computer readable medium such as a RAM memory, flash memory, ROM memory, EPROM memory, registers, hard disk, a removable disk, a CDROM, a DVD-ROM, a Blu-ray disc, or any other form of computer readable medium. In some aspects the computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media).

[0075] In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer readable media. In another aspect, the computer readable medium may be integral to the processor. The processor and the computer readable medium may reside in an ASIC or related device. The software codes may be stored in a memory unit and the processor may be configured to execute them. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

[0076] In a broad aspect then, there is provided a computer readable medium containing instructions to cause the computer to perform the steps of any one or more of the methods described herein.

[0077] Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by computing device. For example, such a device can be coupled to a sewer to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a computing device can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

[0078] In one form there is provided a computer program product for performing the method or operations presented herein. For example, such a computer program product may comprise a computer (or processor) readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For certain aspects, the computer program product may include packaging material.

[0079] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified or required, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[0080] Any Input/Output Interface used may comprise a network interface and/or communications module for communicating with an equivalent communications module in another device using a predefined communications protocol (e.g. Bluetooth, Zigbee, IEEE 802.15, IEEE 802.11, TCP/IP, UDP, etc). A graphical processing unit (GPU) may also be included. Any display apparatus may comprise a flat screen display (e.g. LCD, LED, plasma, touch screen, etc), a projector, CRT, etc. The computing device may comprise a single CPU (core) or multiple CPU's (multiple core), or multiple processors. The computing device may use a parallel processor, a vector processor, or be a distributed computing device. The memory is operatively coupled to the processor(s) and may comprise RAM and ROM components, and may be provided within or external to the device. The memory may be used to store the operating system and additional software modules or instructions. The processor(s) may be configured to load and executed the software modules or instructions stored in the memory.

[0081] Although some specific embodiments of the various aspects have been demonstrated in detail with examples, it should be understood by a person skilled in the art that the above examples are only intended to be illustrative but not to limit the scope. It should be understood by a person skilled in the art that the above embodiments can be modified without departing from the scope and spirit of the various aspects described. The scope of the present invention is defined by the attached claims.

[0082] Throughout the specification and the claims that follow, unless the context requires otherwise, the words "comprise" and "include" and variations such as "comprising" and "including" will be understood to imply the inclusion of a stated integer or group of integers, but not the exclusion of any other integer or group of integers.

[0083] The reference to any prior art in this specification is not, and should not be taken as, an acknowledgement of any form of suggestion that such prior art forms part of the common general knowledge.

Claims (9)

1. CLAIMS1. A control circuit for generating a control signal for controlling a switch, the switch for controlling current applied to a load from a source of mains power, the control circuit comprising a processor for outputting the control signal and for receiving a connection from a neutral terminal of the mains power, wherein the processor is configured to generate the control signal in accordance with the frequency of the mains power.
2. 2. A control circuit as claimed in claim 1 wherein the control circuit generates a virtual load zero crossing signal as the control signal for controlling the switch, the virtual load zero crossing signal having its phase locked with the frequency of the mains power.
3. 3. A control circuit as claimed in claim 2 comprising a Phase Locked Loop (PLL) for generating the virtual zero crossing signal.
4. 4. A control circuit as claimed in claim 3 wherein an input of the PLL is electrically connected to the neutral line of the mains power.
5. 5. A method of controlling a switch for controlling current applied to a load from a source of mains power, wherein the switch is controlled in accordance with the frequency of the mains power.
6. 6. A method as claimed in claim 5 wherein a mains zero crossing signal is obtained from the mains power obtained from a neutral terminal of the mains power.
7. 7. A method as claimed in claim 6 wherein a virtual load zero cross ng signal s obtained from the mains zero crossing signal.
8. 8. A method as claimed in claim 7 wherein the virtual load zero crossing signal is applied to the input of a Phase Locked Loop (PLL) to provide the control signal for controlling the switch.
9. 9. A machine readable medium containing instructions to cause a machine to carry out the method of any one of claims 5 to 8.