GB2632325A - Apparatus and method - Google Patents

Abstract

A method of packaging semiconductor die, the method comprising: placing the first of a set of semiconductor die at the respective first of a set of placements; and providing a first package, having a first structure, comprising ink jetting (i.e. binder jet printing, powder bed and inkjet printing and/or drop-on-powder printing) comprising: providing a first layer of a first powder comprising a first material (e.g. copper powder); forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation. Also disclosed is a packaged semiconductor die produced by this method. The first ink formulation may oxidise the first material upon contact and/or heating. The second ink formulation may reduce the first material upon contact and/or heating.

Description

APPARATUS AND METHOD

Field

The present invention relates to a method of packaging semiconductor die using ink jetting and a packaged semiconductor die manufactured using ink jetting.

Background to the invention

Electronic device manufacturers are constantly striving to increase the performance of their products, while decreasing their cost of manufacture. The family of electronic devices also contains semiconductor devices. A cost intensive area in the manufacture of semiconductor devices is packaging the semiconductor chips. As those skilled in the art are aware, integrated circuits are most often fabricated in wafers, which are then singulated (also known as diced) to produce semiconductor chips, which are also known as semiconductor die or die. Dies range from LED lighting to power semiconductor devices to central processing units. There are three commonly used plural forms: dice, dies, and die.

In the case of power electronic semiconductors, each semiconductor die provides a maximum amount of current which it can switch and conduct for a given semiconductor junction temperature without damage. Semiconductor die are often electrically connected (also known as coupled) in parallel to provide a larger overall current rating. Semiconductor die are also electrically connected in different configurations to provide different functionalities.

Conventionally, one or more semiconductor die are placed in a package to protect them from environmental and physical stresses. Packaging semiconductor die increases the cost and complexity of manufacturing semiconductor devices because the packaging designs do not only provide protection, but also permit transmission of electrical signals to and from the semiconductor chips and, in particular, removal of heat generated by the semiconductor die.

Each package design requires extensive development and testing and often results in the need for a specific production line for each configuration, which reduces the agility and flexibility of production while increasing cost.

In the case of power semiconductor die, for example, the circuit parasitics (inductance, capacitance and/or resistance) greatly affect the overall efficiency of the system. These parasitics may be reduced through careful package design; however, there are limits to this reduction when using conventional manufacturing methods such as busbars. In an ideal situation, high energy connectors would be closely coupled to reduce inductance, for example.

The rate at which losses in the form of heat energy can be removed from the power semiconductor die becomes a limiting factor to the overall power rating of the package. Conventional methods result in high levels of thermal resistance between the semiconductor die and the cooling medium, such as a circulating fluid which is cooled external to the package.

Hence, there is a need to improve packaging of semiconductor die.

Summary of the Invention

A first aspect provides a method of packaging semiconductor die, the method comprising: placing a first set of semiconductor die, including a first semiconductor die, at a respective first set of placements, including a first placement; and providing a first package, having a first structure, for the first set of semiconductor die comprising additive manufacturing, for example ink jetting, and/or hybrid manufacturing.

A second aspect provides a computer comprising a processor and a memory configured to implement, at least in part, a method according to the first aspect, a computer program comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the first aspect or a non-transient computer-readable storage medium comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the first aspect.

A third aspect provides a packaged semiconductor die comprising: a first set of semiconductor die, including a first semiconductor die, placed at a respective first set of placements, including a first placement; and a first package, having a first structure, for the first set of semiconductor die, wherein the first package is provided, at least in part, by additive manufacturing, for example ink jetting, and/or hybrid manufacturing.

A fourth aspect provides a method of ink jetting, the method comprising: providing a first layer of a first powder comprising a first material; forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation.

A fifth aspect provides a computer comprising a processor and a memory configured to implement, at least in part, a method according to the fourth aspect, a computer program comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the fourth aspect or a non-transient computer-readable storage medium comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the fourth aspect.

A sixth aspect provides an article manufactured at least in part by ink jetting, the article comprising: a first layer of a bound first powder comprising a first material; wherein the first layer comprises: a first part having a first electrical conductivity formed by selectively jetting the first layer using a first ink formulation; and a second part having a second electrical conductivity formed by selectively jetting the first layer using a second ink formulation.

A seventh aspect provides a method of packaging semiconductor die, the method comprising: placing a first set of semiconductor die, including a first semiconductor die, at a respective first set of placements, including a first placement; and providing a first package, having a first structure, for the first set of semiconductor die comprising ink jetting comprising: providing a first layer of a first powder comprising a first material; forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation.

An eighth aspect provides a computer comprising a processor and a memory configured to implement, at least in part, a method according to the seventh aspect, a computer program comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the seventh aspect or a non-transient computer-readable storage medium comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the seventh aspect.

A ninth aspect provides a packaged semiconductor die comprising: a first set of semiconductor die, including a first semiconductor die, placed at a respective first set of placements, including a first placement; and a first package, having a first structure, for the first set of semiconductor die, wherein the first package is provided, at least in part, by ink jetting wherein the first package comprises: a first layer of a bound first powder comprising a first material; wherein the first layer comprises: a first part having a first electrical conductivity formed by selectively jetting the first layer using a first ink formulation; and a second part having a second electrical conductivity formed by selectively jetting the first layer using a second ink formulation.

A tenth aspect provides an apparatus configured to implement the method according to the first aspect, the fourth aspect and/or the seventh aspect, to provide a packaged semiconductor die according to the third aspect and/or the ninth aspect and/or to provide an article according to the sixth aspect.

Definitions is A semiconductor device, also known as a module, contains at least one electronic or electrical component, for example. An electronic or electrical component may be a semiconductor chip (also known as a semiconductor die), a power semiconductor die, a passive component or a sensor, for example. A semiconductor chip may be for example a control IC, a monitor IC, a sensor IC, a microprocessor or a power semiconductordie, for example. A power semiconductor die may be any topology and technology for example MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate BipolarTransistors), JFETs (Junction Gate Field Effect Transistors) topologies and Si, SiC, SiGe, GaAs, GaN technologies, for example. A passive component may be a resistor, an inductor, a delay line, an antenna, or a capacitor, for example.

Additive manufacture (AM), also known as three-dimensional (3D) printing, is the process of joining materials to make 3D objects, also known as articles, from 3D model data.

Ink jetting is an additive manufacturing process in which a printhead selectively deposits a liquid binding agent (also known as an ink, a binder or an ink formulation) onto a thin layer of powder particles, to build (for example manufacture) parts or articles and tooling, for example.

A half-bridge is a DC-to-AC step-down converter. It is a "two-quadrant converter' because the load current can flow in both directions. This is a critical feature when driving an inductive load with an AC waveform.

In a totem pole configuration, all power devices are connected in series with their anti-parallel diodes all in the same direction.

A bidirectional switch controls current flow in both directions by, for example, employing two power devices connected in series with the anti-parallel diodes of each device in opposite directions.

A three-level inverter phase can switch between three voltages levels. The most common topologies are the Diode Clamped Inverter and the T-Type inverter.

Electrical parasitics include AC loop inductance, which causes voltage overshoot during and immediately after a switching event, and local output capacitance, in which energy is lost during a switch transition in order to charge and discharge this capacitance. More generally, in electrical networks such as electronic modules, a parasitic element is a circuit element (resistance, inductance and/or capacitance) that is possessed by an electrical component or electrical but which it is not desirable for it to have for its intended purpose.

Detailed Description of the Invention

According to the present invention there is provided a method, as set forth in the appended claims. Also provided is an article, for example a packaged semiconductor die. Other features of the invention will be apparent from the dependent claims, and the description that follows.

Method of packaging semiconductor die The first aspect provides a method of packaging semiconductor die, the method comprising: placing a first set of semiconductor die, including a first semiconductor die, at a respective first set of placements, including a first placement; and providing a first package, having a first structure, for the first set of semiconductor die comprising additive manufacturing, for example ink jetting, and/or hybrid manufacturing.

In this way, the first set of semiconductor die is packaged by additive manufacturing, at least in part, the first package, thereby protecting the first set of semiconductor die from environmental and/or physical stresses. Since the first package is provided, at least in part, by additive manufacturing, the first structure of the first package may be specific (i.e. custom, tailored, individual), for example to reduced parasitics and/or improve removal of heat, thereby enhancing efficiency in use. In this way, agility and/orflexibility of production of the packaged semiconductor die is improved, since the same production line may be used for producing packaged semiconductor die having different structures.

Packaging The method is of packaging semiconductor die, thereby providing a packaged semiconductor die. Conventional packaged semiconductor die are known. In contrast to conventional packaged semiconductor die, each packaged semiconductor die provided by the method according to the first aspect may comprise different sets of semiconductor die, optionally at different respective placements, and/or different packages having respectively different structures while produced using the same production line, comprising an additive manufacturing apparatus, for example a binder jet apparatus.

Placing The method comprises placing the first set of semiconductor die, including the first semiconductor die, at the respective first set of placements, including the first placement.

In one example, the first semiconductor die comprises and/or is a control IC, a monitor IC, a sensor IC, a microprocessor, a CPU, a power semiconductor die, for example of any topology such as a MOSFET, an IGBT and/or a JFET and/or any technology such as Si, SiC, SiGe, GaAs and/or GaN. In one example, the first set of semiconductor die includes a second semiconductor die, for example wherein the second semiconductor die is as described with respect to the first semiconductor die, for example wherein the first semiconductor die and the second semiconductor die have the same topology and/or technology or wherein the first semiconductor die and the second semiconductor die have mutually different topology and/or technology.

In one example, the first set of semiconductor die includes N semiconductor die, wherein N is a natural number greater than or equal to 2, for example 2, 3, 4, 5, 6, 7, 8, 9, 10 or more. The N semiconductor die maybe as described with respect to the first semiconductor die or the second semiconductor die.

It should be understood that the first semiconductor die is placed (i.e. physically positioned or located) at the first placement (i.e position or location). It should be understood that the respective first set of placements of the first set of semiconductor die are mutually relative and may be defined absolutely, for example in two or three dimensions with respect to a predetermined reference, or relatively, for example in two or three dimensions with respect to the first of semiconductor die, for example a datum thereof.

In one example, the step of placing the first set of semiconductor die, including the first semiconductor die, at the respective first set of placements, including the first placement, precedes the step of providing, at least in part, the first package, having the first structure, for the first set of semiconductor die comprising additive manufacturing. In this way, the first set of semiconductor die is placed and the first package is subsequently provided thereupon and/or therearound. In one example, the step of placing the first semiconductor die at the respective first placement precedes this step of providing the first package, having a first structure, for the first set of semiconductor die comprising additive manufacturing. In this way, the first semiconductor die is placed and the first package is subsequently provided, at least in part, thereupon and/or therearound. Subsequently, a second semiconductor die may be placed at a respective second placement and the step of providing the first package continued.

In one example, the step of placing the first set of semiconductor die, including the first semiconductor die, at the respective first set of placements, including the first placement, proceeds the step of providing, at least in part, the first package, having the first structure, for the first set of semiconductor die comprising additive manufacturing. In this way, the first package is provided, at least in part, and subsequently, the first set of semiconductor die is placed thereupon and/or therein, whereupon the step of providing, at least in part, the first package may be continued. In one example, the step of placing the first semiconductor die at the respective first placement precedes this step of providing the first package, having a first structure, for the first set of semiconductor die comprising additive manufacturing. In this way, the first semiconductor die is placed and the first package is subsequently provided, at least in part, thereupon and/or therearound. Subsequently, a second semiconductor die may be placed at a respective second placement and the step of providing the first package continued.

More generally, the first set of semiconductor die may be placed before, during and/or after providing the first package. In this way, the first set of semiconductor die may be placed mutually relatively in three dimensions at different stages of the additive manufacturing, thereby packaging the first set of semiconductor die in three dimensional placements and/or topologies that may not be achieved conventionally. For example, four semiconductor die maybe packaged in the same respective placements in two different packages but interconnected in two different topologies.

In one example, placing the first set of semiconductor die, including the first semiconductor die, comprises placing the first set of semiconductor die, including the first semiconductor die, on a substrate; and wherein providing the first package for the first set of semiconductor die comprising the additive manufacturing comprises providing the first package for the first set of semiconductor die comprising the additive manufacturing on the substrate. In this way, a substrate is provided for the first set of semiconductor die.

In one example, the respective first set of placements, including the first placement, are mutually coplanar. In this way, the first set of semiconductor die are mutually coplanar i.e. placed on the same plane.

In one example, the respective first set of placements, including the first placement, are mutually parallel. In this way, the first of semiconductor die are placed on mutually parallel planes.

In one example, the respective first set of placements, including the first placement, are mutually non-coplanar, for example placed on mutually parallel planes and/or transverse, for example orthogonal, thereto. In this way, novel topologies may be provided in three dimensions.

In one example, the method comprises: placing a second set of semiconductor die, including a first semiconductor die, at the respective first set of placements, including the first placement; and providing a second package, having a second structure, for the second set of semiconductor die comprising additive manufacturing, for example ink jetting, and/or hybrid manufacturing; wherein the first structure and the second structure are mutually different.

In this way, different structures (for example having different interconnects) are provided for the first and second package, which have the same semiconductor die placements.

In one example, placing the first set of semiconductor die, including the first semiconductor die, at the respective first set of placements, including the first placement, is performed during the additive manufacturing and/or the hybrid manufacturing, for example by the additive manufacturing apparatus, which may additionally and/or alternatively place other electronic or electrical components. For example, the additive manufacturing apparatus may include a separate "pick and place" function on the same xy gantry, or a separate gantry for this placement.

Packaging The method comprises providing the first package, having the first structure, for the first set of semiconductor die.

Generally, a semiconductor package (also known as a package) is a metal, plastic, glass, or ceramic casing containing one or more discrete semiconductor die. The package provides a means for connecting the semiconductor die to the external environment, such as a printed circuit board, via leads such as lands, balls, or pins; and protection against threats such as mechanical impact, chemical contamination, and light exposure. Additionally, the package helps dissipate heat produced by the device, with or without the aid of a heat spreader.

In one example, the first structure comprises a first set of electrical couplings (also known as interconnects), including a first electrical coupling, wherein the first electrical coupling is electrically coupled to the first semiconductor die. It should be understood that the first set of electrical couplings is provided by additive manufacturing, as described herein. In this way, the first semiconductor die may be electrically coupled to a second semiconductor die included in the set thereof via the first electrical coupling. Additionally and/or alternatively, in this way, the first semiconductor die may be electrically coupleable to an external component via the first electrical coupling. In one example, the first set of semiconductor die includes N semiconductor die, wherein N is a natural number greater than or equal to 1, for example 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or more, including the first semiconductor die, and the first structure comprises the first set of electrical couplings includes C electrical couplings, wherein C is a natural number greater than or equal to 1, for example 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or more, including a first electrical coupling, wherein the first electrical coupling is electrically coupled to the first semiconductor die and optionally, wherein the C electrical couplings mutually electrically couple semiconductor die. In one example, the first electrical coupling is provided by a first layer or a part thereof, for example only by a first layer or a part thereof, within the first structure, for example by patterning the first layer, for example only the first layer or a part thereof, during the additive manufacturing.

In this way, the first electrical coupling may be provided within a layer (i.e. in plane) of the additively manufactured first structure. In one example, the first electrical coupling is provided by two or more adjacent layers or parts thereof, for example by patterning the two or more adjacent layers or parts thereof during the additive manufacturing. In this way, the first electrical coupling may be provided through two or more adjacent layers (i.e. through thickness) of the additively manufactured first structure. In one example, the first electrical coupling is provided by a first layer or a part thereof within the first structure, for example by patterning the first layer, during the additive manufacturing and by two or more adjacent layers or parts thereof, for example by patterning the two or more adjacent layers or parts thereof during the additive manufacturing. In this way, the first electrical coupling may be provided partly within a layer (i.e. in plane) and partly through two or more adjacent layers (i.e. through thickness). In this way, the first electrical coupling may be routed in three dimensions around other electrical couplings, electrical isolators, thermal couplings and/or semiconductor die, for example. Such routing is generally not possible via conventional packaging processes.

In one example, the first structure comprises a first set of electrical isolators, including a first electrical isolator, wherein the first electrical isolator is disposed to electrically isolate a part of the first semiconductor die and/or an electrical coupling. It should be understood that the first set of electrical isolators is provided by additive manufacturing, as described herein. In this way, semiconductor die and/or electrical couplings may be mutually electrically isolated, for example.

In one example, the first structure comprises the first set of electrical isolators includes I electrical isolators, wherein I is a natural number greater than or equal to 1, for example 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or more, including a first electrical isolator, wherein the first electrical isolator is disposed to electrically isolate a part of the first semiconductor die and/or an electrical coupling. In one example, the first electrical isolator is provided by a first layer or a part thereof, for example only by a first layer or a part thereof, within the first structure, for example by patterning the first layer, for example only the first layer or a part thereof, during the additive manufacturing. In this way, the first electrical isolator may be provided within a layer (i.e. in plane) of the additively manufactured first structure. In one example, the first electrical isolator is provided by two or more adjacent layers or parts thereof, for example by patteming the two or more adjacent layers or parts thereof during the additive manufacturing. In this way, the first electrical isolator may be provided through two or more adjacent layers (i.e. through thickness) of the additively manufactured first structure. In one example, the first electrical isolator is provided by a first layer or a part thereof within the first structure, for example by patterning the first layer, during the additive manufacturing and by two or more adjacent layers or parts thereof, for example by patterning the two or more adjacent layers or parts thereof during the additive manufacturing. In this way, the first electrical isolator may be provided partly within a layer (i.e. in plane) and partly through two or more adjacent layers (i.e. through thickness). In this way, the first electrical isolator may be routed in three dimensions around other electrical isolators, electrical couplings, thermal isolators and/or semiconductor die, for example. Such routing is generally not possible via conventional packaging processes.

In one example, the first structure comprises a first set of thermal couplings, including a first thermal coupling, wherein the first thermal coupling is thermally coupled to the first semiconductor die. In this way, removal of heat may be improved.

In one example, the first thermal coupling comprises and/or is a passageway (a conduit, a channel or a pipe), for example for circulation of a coolant fluid therethrough.

In one example, the first thermal coupling is provided by the first electrical coupling or the first electrical isolator. In one example, the first thermal coupling is not provided by the first electrical coupling and/or the first electrical isolator. For example, the first thermal coupling may have a different material composition (e.g. lower thermal resistance) and/or the first thermal coupling may be either electrically conductive or electrically insulative. For example, the first thermal coupling may comprise a tube created in the other structures to take either an electrically conductive liquid (e.g. water) within the insulator part or a non-conductive liquid (e.g. dielectric oil) for either conductor or insulator parts.

In one example, the first structure comprises a first set of passive components, including a first passive component. In this way, parasitics may be reduced. In one example, the first passive component comprises and/or is a resistor, an inductor, a delay line, an antenna or a capacitor.

In one example, the first package comprises a first set of electrical or electronic components, including a first electrical or electronic component, for example inserted therein, such as a current sensor embedded in, or adjoining, the first set of electrical couplings.

In one example, the first structure comprises a section which provides a calibratable function of equivalent to a passive electronic or electrical component. In one example, the first structure comprises a section which provides a calibratable function of equivalent to a passive electronic or electrical component.

In one example, the section comprises and/or is a second section of the first electrical coupling or the first electrical isolator which provides a calibratable function of passive electronic component for example, resistance, inductance, capacitance, electromagnetic coupling (transformer for example).

In one example, the method provides inline measurement of electrical conduction and/or electrical insulation (i.e. electrical resistance) for realtime feedback control of the additive manufacturing apparatus, for example in order to meet design targets.

In one example, the first set of electrical couplings and the first set of electrical isolators provide mutually parallel conductors, for example which form insulated multistrand electrical wire or cable. Alternatively, they may produce structures like braided, low inductance, wire or Litz wire.

Additive manufacturing ink jetting Providing the first package, having the first structure, for the first set of semiconductor die comprises additive manufacturing, for example ink jetting, and/or hybrid manufacturing, for example layer manufacturing.

Additive manufacturing (AM), popularly known as three-dimensional (3D) printing, generally refers to processes used to create articles or objects from layers of material sequentially formed under computer control. Additive manufacturing provides creation of articles having complex shapes, geometries or structures, including internal voids, that may not readily be formed according to conventional subtractive manufacturing processes, such as machining, or conventional casting or moulding processes. Materials suitable for additive manufacturing include metals, ceramics, glasses and polymers. ISO/ASTM52900-15 defines seven categories of additive manufacturing processes, including ink jetting in which a liquid bonding agent (also known as an ink formulation) is selectively deposited to join powder materials.

Hybrid manufacturing includes Additive/Subtractive Hybrid Manufacturing (ASHM), which involves additive and subtractive manufacturing. Hybrid manufacturing also includes layer manufacturing, used to create articles or objects from layers, such as previously formed layers, which are sequentially stacked, thereby providing the benefits of additive manufacturing.

The inventors have determined that additive manufacturing and/or hybrid manufacturing may be used to provide a specific structure of the package, for example to reduce parasitics and/or improve removal of heat while providing interconnects, for example for individual packages and/or limited batches, such as using the same production line. Additionally and/or alternatively, additive manufacturing and/or hybrid manufacturing may be used to interconnect the semiconductor die in topologies, for example in three dimensions, but may not be realisable using conventional processes.

In one example, the ink jetting comprises: providing a first layer of a first powder comprising a first material (i.e. a first powder); forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and wherein the first part is disposed to electrically couple to the first semiconductor die and/or electrically isolate the first semiconductor die.

In this way, the first part provides an electrical coupling or an electrical isolator, as described herein, depending on the first ink formulation, for example as described with respect to the fourth aspect.

In one example, providing the first package for the first set of semiconductor die comprises additive manufacturing the placed first set of semiconductor die. In this way, the semiconductor die are provided, at least in part by additive manufacturing i.e. in situ.

In one example, the additive manufacturing comprises providing a void in the first layer and depositing materials and/or fluid therein. In this way, the materials and/or fluid are inserted during at least one pause in the additive manufacture process, for example whereby additional materials are poured into a surface orifice and thus into a void created when the powder is removed.

Computer, computer program, non-transient computer-readable storage medium The second aspect provides a computer comprising a processor and a memory configured to implement, at least in part, a method according to the first aspect, a computer program comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the first aspect or a non-transient computer-readable storage medium comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the first aspect.

Packaged semiconductor die The third aspect provides a packaged semiconductor die comprising: a first set of semiconductor die, including a first semiconductor die, placed at a respective first set of placements, including a first placement; and a first package, having a first structure, for the first set of semiconductor die, wherein the first package is provided, at least in part, by additive manufacturing, for example ink jetting, and/or hybrid manufacturing.

In one example, the first structure comprises a first set of electrical isolators, including a first electrical isolator, wherein the first electrical isolator is disposed to electrically isolate a part of the first semiconductor die.

In one example, the first structure comprises a first set of thermal couplings, including a first thermal coupling, wherein the first thermal coupling is thermally coupled to the first semiconductor die.

Method of ink jetting The fourth aspect provides a method of ink jetting, the method comprising: providing a first layer of a first powder comprising a first material; forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation.

In this way, the electrical conductivity of the bonded powder comprising the first material is determined by which ink formulation is used for binding the powder. Hence, the first part, having the first electrical conductivity, is formed by jetting the first powder comprising the first material with the first ink formulation while the second part, having the second electrical conductivity, is formed by jetting the first powder comprising the first material (i.e. the same material) with the second ink formulation. In this way, different parts of the first layer may have different electrical conductivities according to which ink formulation and/or dosing thereof is used for the selective jetting. For example, the first part may be an electrical coupling such as an interconnect while the second part may be an electrical isolator, for example surrounding the first part and thereby electrically isolating the electrical coupling from other electrical couplings, for example. In this way, electrical couplings and/or electrical isolators may be provided by the ink jetting in one or more layers (i.e. in 2D or 3D) of the same material, thereby providing relatively complex routes in 2D or 3D. It should be understood that the method according to the fourth aspect may be more generally applied to multilayer ink jetting.

Ink jetting The method is of ink jetting (also known as binder jet 3D printing, powder bed and inkjet printing and drop-on-powder printing. Suitable apparatuses for ink jetting are known. Ink jetting is an additive manufacturing process in which a printhead selectively deposits a liquid binding agent (also known as a binder or an ink formulation) onto a thin layer of powder particles, to build (for example manufacture) parts or articles and tooling, for example. By repeating the steps of providing a thin layer of powder particles and selectively depositing liquid binding agent thereupon, 3D parts or articles may be manufactured.

First layer The method comprises providing the first layer of the first powder comprising the first material. Methods of providing layers for ink jetting are known. The first powder comprises the first material. In one example, the first powder consist essentially of the first material or consist of the first material. It should be understood that the first part and the second part are both formed from the first powder comprising the first material of the first layer i.e. from the same material notwithstanding that different ink formulations are used for the first part and the second part.

In one example, the method comprises: providing a second layer on the first layer; selectively jetting the second layer using the first ink formulation; and/or selectively jetting the second layer using the second ink formulation.

First part The method comprises forming the first part having the first electrical conductivity comprising selectively jetting the first layer using the first ink formulation. It should be understood that the first part is formed in the first layer. It should be understood that the first ink formulation binds the first powder of the first layer to form the part and determines the electrical conductivity thereof.

In one example, the first ink formulation oxidises the first material, for example upon contacting and/or heating. In this way, the first material may be oxidised to provide an electrical insulator, for example. In one example, selectively jetting the first layer using the first ink formulation comprises oxidising the first material, for example thereby providing an oxide of the first material. In one example, forming the first part having the first electrical conductivity comprises heating the first layer, for example after forming the first part and/or the second part and/or before providing a second layer (i.e. interlayer heating). More generally, in one example, the first ink formulation causes or renders the first material to become an electrical insulator and/or electrically insulates the first material, for example upon contacting and/or heating.

In one example, the first part comprises and/or is an electrical isolator for an electrical 15 component.

In one example, the first electrical conductivity is relatively lower than the second electrical conductivity, for example by one, two, three, four, five, six or more orders of magnitude.

In one example, the first ink formulation comprises and/or is a resistive ink, for example comprising an electrical insulator such as an oxide. For example, a resistive ink may comprise A1203 nano particles (generally as small as possible to aid sintering of resistive layer at Cu sintering temperatures) suspended in liquid. Could contain yttrium butoxide or some other oxide forming butoxide. Jetting would be in humidity-controlled environment. After jetting first layer, water vapour is brought into the chamber to convert yttrium butoxide to yttria to bind to the A1203 particles and Cu.

Other resistive inks include: * YSZ ink -Ink based on decomposition and oxidation of Yttrium and Zirconium containing solution. Ratio of Y to Zr can be easily controlled during formulation to tailor electrical properties.

100% ZrO2 resistivity around 3.1 x10^12 4.cm, 100% Y203 resistivity around 2.8 x10^6 acm. Resistivity values between the two extremes can be selected during the formulation stage. Ink formulation could be adapted to contain Yttria and Zirconia nanoparticles in the chosen ratios and printed onto either a mix of Yttria and Zirconia microparticles or onto Yttria stabilised zirconia microparticles in a powder bed.

* As described in Synthesis of Preceramic Precursor Based on Organic Aluminum Salts for Stereolithographic 3D Printing of Corundum Ceramics INORGANIC MATERIALS: APPLIED RESEARCH Vol. 12 No. 5 2021 Second part The method comprises forming the second part having the second electrical conductivity comprising selectively jetting the first layer using a second ink formulation. It should be understood that the second part is formed in the first layer. It should be understood that the second ink formulation binds the first powder of the first layer to form the second part and determines the electrical conductivity thereof In one example, the second ink formulation reduces the first material, for example upon contacting and/or heating. In this way, the first material may be reduced to provide an electrical conductor, for example. In one example, selectively jetting the first layer using the second ink formulation comprises reducing the first material, for example thereby providing a reduced form of the first material. In one example, forming the second part having the second electrical conductivity comprises heating the first layer, for example after forming the first part and/or the second part and/or before providing a second layer (i.e. interlayer heating). More generally, in one example, the second ink formulation causes or renders the first material to become an electrical conductor and/or electrically coats the first material, for example upon contacting and/or heating.

In one example, the second part comprises and/or is an electrical coupling for an electrical component.

In one example, the second ink formulation comprises and/or is a conductive ink, for example comprising an electrical conductor such as a metal. For example, a copper conductive ink may 25 comprise: * Cu formate tetrahydrate (CuFT) * Octylamine * Aminomethylpropanol (AMP) * Isopropyl alcohol (IPA) Cu particles (CuMPs, CuNPs) Other conductive inks include: * graphene-based inks * silver inks such as described in Gioia Furia, Fanny Tricot, Didier Chaussy, Philippe Madn, Andrea Graziano, et al.. Use of a 6-axis robot and ink piezo-jetting to print conductive paths on 3D objects. Printed circuit geometry, and conductivity predictive model. CIRP Journal of Manufacturing Science and Technology, 2021, 35, pp.855-863. 10.1016/j.cirpj.2021.09.012. hal03440231 * aluminium inks First part and second part In one example, the first part and the second part mutually partially overlap and/or the first part and the second part are mutually adjacent.

In one example, the first part and the second part mutually partially overlap. In this way, the region of mutual overlap may have a third electrical conductivity, for example between the first electrical conductivity and the second electrical conductivity. In this way, an electrical conductivity gradient may be provided between the first part and the second part.

In one example, the first part and the second part are mutually adjacent. In this way, the first part may be an electrical coupling such as an interconnect while the second part may be an electrical isolator, for example surrounding the first part and thereby electrically isolating the electrical coupling from other electrical couplings, for example between the first part and the second part.

In one example, the first part and the second part define an electrical conductivity gradient or a part thereof. For example, a plurality of different ink formulations may be used to define a relatively shallow electrical conductivity gradient. For example, two different ink formulations may be used to define an electrical conductivity step.

In one example, the method comprises electrically isolating the second part using the first part, for example by surrounding the second part on one or more sides.

Ink formulations In one example, the method comprises preparing the first ink formulation and/or the second ink formulation.

In one example, the method comprises selectively jetting the first layer using a third ink formulation.

Computer, computer program, non-transient computer-readable storage medium A fifth aspect provides a computer comprising a processor and a memory configured to implement, at least in part, a method according to the fourth aspect, a computer program comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the fourth aspect or a non-transient computer-readable storage medium comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the fourth aspect.

Article The sixth aspect provides an article manufactured at least in part by ink jetting, the article comprising: a first layer of a bound first powder comprising a first material; wherein the first layer comprises: a first part having a first electrical conductivity formed by selectively jetting the first layer using a first ink formulation; and a second part having a second electrical conductivity formed by selectively jetting the first layer using a second ink formulation.

In one example, the first part comprises oxidised first material or reduced first material.

In one example, the first part and the second part mutually partially overlap and/or wherein the first part and the second part are mutually adjacent.

In one example, the first part and the second part define an electrical conductivity gradient.

Method of packaging semiconductor die comprising ink jetting The seventh aspect provides a method of packaging semiconductor die, the method comprising: placing a first set of semiconductor die, including a first semiconductor die, at a respective first set of placements, including a first placement; and providing a first package, having a first structure, for the first set of semiconductor die comprising ink jetting comprising: providing a first layer of a first powder comprising a first material; forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation.

That is, the method according to the seventh aspect provides a method of packaging semiconductor die according to the first aspect, wherein providing the first package is according to the fourth aspect, thereby synergistically providing the advantages of both the first aspect and the fourth aspect.

The method may include any steps as described with respect to the first aspect and/or the fourth aspect mutatis mutandis.

Computer, computer program, non-transient computer-readable storage medium The eighth aspect provides a computer comprising a processor and a memory configured to implement, at least in part, a method according to the seventh aspect, a computer program comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the seventh aspect or a non-transient computer-readable storage medium comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to the seventh aspect.

Ink jet packaged semiconductor die The ninth aspect provides a packaged semiconductor die comprising: a first set of semiconductor die, including a first semiconductor die, placed at a respective first set of placements, including a first placement; and a first package, having a first structure, for the first set of semiconductor die, wherein the first package is provided, at least in part, by ink jetting wherein the first package comprises: a first layer of a bound first powder comprising a first material; wherein the first layer comprises: a first part having a first electrical conductivity formed by selectively jetting the first layer using a first ink formulation; and a second part having a second electrical conductivity formed by selectively jetting the first layer using a second ink formulation.

That is, the packaged semiconductor die according to the ninth aspect provides a packaged semiconductor die according to the third aspect, wherein the first package is manufactured according to the sixth aspect, thereby synergistically providing the advantages of both the third aspect and the sixth aspect.

The method may include any features as described with respect to the third aspect and/or the sixth aspect mutatis mutandis.

Apparatus The tenth aspect provides an apparatus configured to implement the method according to the first aspect, the fourth aspect and/or the seventh aspect, to provide a packaged semiconductor die according to the third aspect and/or the ninth aspect and/or to provide an article according to the sixth aspect.

Definitions Throughout this specification, the term "comprising" or "comprises" means including the component(s) specified but not to the exclusion of the presence of other components. The term "consisting essentially of or "consists essentially of means including the components specified but excluding other components except for materials present as impurities, unavoidable materials present as a result of processes used to provide the components, and components added for a purpose other than achieving the technical effect of the invention, such as colourants, and the like.

The term "consisting of or "consists of means including the components specified but excluding other components.

Whenever appropriate, depending upon the context, the use of the term "comprises" or "comprising" may also be taken to include the meaning "consists essentially of or "consisting essentially of', and also may also be taken to include the meaning "consists of or "consisting of'.

The optional features set out herein may be used either individually or in combination with each other where appropriate and particularly in the combinations as set out in the accompanying claims. The optional features for each aspect or exemplary embodiment of the invention, as set out herein are also applicable to all other aspects or exemplary embodiments of the invention, where appropriate. In other words, the skilled person reading this specification should consider the optional features for each aspect or exemplary embodiment of the invention as interchangeable and combinable between different aspects and exemplary embodiments.

Brief description of the drawings

For a better understanding of the invention, and to show how exemplary embodiments of the same may be brought into effect, reference will be made, by way of example only, to the accompanying diagrammatic Figures, in which: Figure 1A schematically depicts a single power semiconductor die as an electrical symbol; and Figure 1B schematically depicts the single power semiconductor die as a mechanical representation (plan view); Figures 2A to 2F schematically depict six example electrical configurations based on four die within the same package, noting that other electrical configurations are possible with the same die placements; Figure 3A schematically depicts the four die of Figure 2A in more detail, connected in parallel to provide a single switch element; Figure 3B schematically depicts the four die according to an exemplary embodiment, as a mechanical representation (plan view); and Figures 3C and 3D schematically depict the four die of Figure 3B, as alternative exemplary embodiments; Figure 4A schematically depicts the half bridge configuration of Figure 2B in more detail, with each switch implemented using two die; Figure 4B schematically depicts the half bridge configuration according to an exemplary embodiment, as a mechanical representation (plan view); and Figures 4C, 4D and 4E schematically depict the half bridge configuration of Figure 4B, as alternative exemplary embodiments; Figure 5A schematically depicts the pair of half bridge configurations of Figure 2C in more detail, with each switch implemented using one die; Figure 5B schematically depicts the pair of half bridge configurations according to an exemplary embodiment, as a mechanical representation (plan view); and Figures 5C and 5D schematically depict the half bridge configuration of Figure 5B, as alternative exemplary embodiments; Figure 6A schematically depicts the four die in a totem pole configuration of Figure 2D in more detail, and also how the external connection of two additional diodes may provide a three-level inverter phase overall; Figure 6B schematically depicts the four die in the totem pole configuration according to an exemplary embodiment, as a mechanical representation (plan view); and Figure 6C schematically depicts the half bridge configuration of Figure 6B, as alternative exemplary embodiments; Figure 7A schematically depicts the four die as a bidirectional switch of Figure 2E in more detail, connected to a half bridge to provide a T-Type three-level inverter phase; Figure 7B schematically depicts the four die as the bidirectional switch according to an exemplary embodiment, as a mechanical representation (plan view); and Figure 7C schematically depicts the two four as the bidirectional switch of Figure 7B, as alternative exemplary embodiments; Figure 8A schematically depicts the pair of two die as a bidirectional switch with a common output of Figure 2F in more detail; Figure 8B schematically depicts the pair of two die according to an exemplary embodiment, as a mechanical representation (plan view); and Figure 8C schematically depicts the pair of two die, as alternative exemplary embodiments; Figure 9 schematically depicts a method according to an exemplary embodiment, particularly an additive manufacturing process, in this example a binder jet method; Figure 10 schematically depicts the incorporation of insulators, fully encapsulating (apart from external connections) in this example; Figure 11 schematically depicts the incorporation of coolant fluid channels within the structure, cooling bus bars and insulation in this example Figure 12 schematically depicts the primary current loops within a T-type topology under the three main switching states; Figure 13 schematically depicts how the 3D routing of the positive and negative dc conductors close to the mid voltage conductor and mid voltage bidirectional switch can be used to reduce the parasitic inductance; Figure 14A schematically depicts a method according to an exemplary embodiment; and Figure 14B schematically depicts a method according to an exemplary embodiment; Figure 15 schematically depicts a method according to an exemplary embodiment; Figure 16 schematically depicts a method according to an exemplary embodiment; and Figure 17 schematically depicts a method according to an exemplary embodiment.

Detailed Description of the Drawings

General In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.

As used herein, the terms "coupled" and/or "electrically coupled" are not meant to mean that the elements must be directly coupled together; intervening elements may be provided between the "coupled" or "electrically coupled" elements.

Semiconductors Devices containing one or more semiconductor die are described below. The semiconductor die may be of different types, may be manufactured by different technologies and may include for example integrated electrical, electro-optical or electro-mechanical circuits and/or passives. The semiconductor die may, for example, be configured as power semiconductor die, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), power bipolar transistors or power diodes. Furthermore, the semiconductor device may include control circuits, microprocessors or microelectromechanical components.

Semiconductor die having a vertical structure may be involved, that is to say that the semiconductor die may be fabricated in such a way that electric currents can flow in a direction perpendicular to the main faces of the semiconductor die. A semiconductor die having a vertical structure may have contact elements on its two main faces, that is, on its top side and bottom side. Power semiconductor die may have a vertical structure. By way of example, the source electrode and gate electrode of a power MOSFET may be situated on one main face, while the drain electrode of the power MOSFET is arranged on the other main face. Other topologies may be used with the present invention.

Furthermore, the devices described below may include integrated circuits to control the integrated circuits of other semiconductor die, for example the integrated circuits of power semiconductor die. The semiconductor die need not be manufactured from specific semiconductor material, for example Si, SiC, SiGe, GaAs, GaN, and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example insulators, plastics or metals.

The semiconductor die may be placed on carriers. The carriers may be of any shape, size or material. According to one embodiment, the carriers may be electrically conductive. They may be fabricated from metals or metal alloys, for example, copper, copper alloys, iron nickel, aluminum, aluminum alloys, or other appropriate materials. The carriers may be metal plates or metal foils. The carriers may be unstructured or structured and may be, for example, a leadframe or a part of a leadframe. Furthermore, the carriers may be plated with an electrically conductive material, for example copper, silver, iron nickel or nickel phosphorus. According to one embodiment, the carriers may be electrically insulating and may, for example, be made of a polymer material, for example a prepreg material.

Moreover, the carriers may be embodied as a PCB (printed circuit board) or a DCB (direct copper bonded), which includes a ceramic carrier, for example made of A1203, AN, BN or TiN, and copper coatings on both sides.

The devices described below include external contact elements, which may be of any shape, size and material. The external contact elements may be accessible from outside the device and may thus allow electrical contact to be made with the semiconductor die from outside the device. Furthermore, the external contact elements may be thermally conductive and may serve as heat sinks for dissipating the heat generated by the semiconductor die. The external contact elements may be composed of any desired electrically conductive material. The external contact elements may include external contact pads. Solder material may be deposited on the external contact pads.

The diagrams contained in this patent focus on the power conductors and not the control signal paths. Those skilled in the art will be able to adapt the methods contained within this patent to provide control signal, thermal measurement and other signal connections required to support a range of power semiconductor devices and semiconductor chips.

The diagrams extend the power conductor to the nearest edge of the package to provide for external connection. The external connection method is not shown, but those skilled in the art will be able to adapt the method to support many methods of external connection including the production of a single package containing a number of similar or different instances of the configurations shown in this patent. The connectors may be extended to other edges or the top or bottom faces of the package.

The present invention produces a semiconductor package incorporating a plurality of power semiconductor die where the die placements may be kept common, and the surrounding structures are different in order to provide a number of package function configurations. The package structures include conductors, insulators, heat paths, external connections and supports. Variants of the die placement will be explained in connection with the embodiments described in this patent, flat and stacked, however, other common die placements are possible using the present invention.

The structural designs are optimised for circuit parasitics by closely coupling the high energy conductors involved in the switch energy paths and thus reduce the systems ac loop inductance.

The structural designs and manufacturing method are optimised for reduction in thermal resistance between the die and the cooling medium while providing protection from environmental and physical stresses.

Examples of configurations Figure 1A schematically depicts a single power semiconductor die as an electrical symbol; and Figure 1B schematically depicts the single power semiconductor die as a mechanical representation (plan view).

Figure 1, comprising Figures 1A and 1 B, schematically illustrates a single power semiconductor die as an electrical symbol 100 (Figure 1A) and a mechanical representation 103 (Figure 1B).

102 denotes the switching element of the device and 101 the anti-parallel diode. The switching device 102 might take the form of a MOSFET or an IGBT or any other switching semiconductor. It may use any technology, for example, Si, SiC, GaN. The diode 101 function might be provided as a separate element on the same die substrate or be intrinsic in the device design or be on a separate substrate. Those skilled in the art will know how to adapt the examples given in this patent in order to support all types and technologies of power device and diode connection method.

Within the mechanical representation 103 (Figure 1B), the source is shown as 104 and the drain as 105 in the case of a MOSFET. Those skilled in the art will know how to adapt the schematically illustrations to support other power semiconductor devices and semiconductor chips.

Figures 2A to 2F schematically depict six example electrical configurations based on four die within the same package, noting that other electrical configurations are possible with the same die placements.

Figure 2, comprising Figures 2A to 2F, schematically illustrates six example electrical configurations based on four die within the same package. Those skilled in the art will appreciate how to extend the number of die to increase the power rating of the overall device. Those skilled in the art will be able to develop alternative common die placements. Those skilled in the art will be able to develop alternative power device configurations based on principles from this invention.

Figure 2A illustrates four die connected in parallel 200 to provide a single switch element. Figure 2B schematically illustrates a half bridge configuration 201 with each switch implemented using two die. Figure 2C schematically illustrates a pair of half bridge configurations 202 with each switch implemented using one die. Figure 2D schematically illustrates four die in a totem pole configuration 203 and also how the external connection of two additional diodes would provide a three-level inverter phase overall. Figure 2E schematically illustrates two die as a bidirectional switch 204 connected to a half bridge would provide a T-Type three-level inverter phase. Figure 2F schematically illustrates a pair of two die as a bidirectional switch 205 with a common output. Each of these example electrical configurations will be described in detail in turn.

Those skilled in the art will know how to adapt the schematically illustrations to accommodate different numbers of die. The structural principals described herein may be adapted to a single die within semiconductor device 200 up to an unlimited number of die. Semiconductor devices 201, 202 and 205 require at least 2 die. Semiconductor device 203 requires at least 4 die.

Semiconductor device 204 requires at least 4 die total if the bidirectional switch is being provided using two die, and 3 die total if the bidirectional switch is being provided using one die of a bidirectional format.

Figure 3A schematically depicts the four die of Figure 2A in more detail, connected in parallel to provide a single switch element; Figure 3B schematically depicts the four die according to an exemplary embodiment, as a mechanical representation (plan view); and Figures 3C and 3D schematically depict the four die of Figure 3B, as alternative exemplary embodiments.

Figure 3, comprising Figures 3A to 3D, schematically illustrates four die connected in parallel to provide a single switch element. The example shown uses four die, 303, 304, 305 and 306.

Figure 3B shows a plan view (from the top) of a common flat die structure 300 where the die are not stacked using a first variant of the common die positions. Figure 3C shows a plan view (from the top) of an alternative embedment of a common flat die structure 313 where the DC power planes have been extended to increase coupling and reduce parasitic inductance. Figure 3D shows a side view stacked variant 312 which has the second variant of the die positions. The common die positions have been optimised so that the die positions do not require changing in order to support alternative package configurations.

As shown in Figure 3A, each die 303, 304, 305 and 306 is connected in parallel with each die drain connected to the upper conductor 310 and each die source connected to the lower conductor 311. In standard operation, the gate control signal of each die would trigger conduction at the same time so that the combined configuration acts as a single switch. Those skilled in the art will appreciate that individual control of each die is also possible for example during low current switching or in reaction to one of the die overheating or failing.

As shown in Figure 3B, each die 303, 304, 305 and 306 is connected to the appropriate conduction in the simplest fashion, being two separate flat conducting layers, 301 and 302.

These layers are extended in Figure 3C in order to increase coupling and reduce parasitic inductance. Those skilled in the art will be able to adapt this method to include other signals such as the gate control signals.

As shown in Figure 3D, the conductors, 308 and 309, bend around the die. The locations of the die are in a second variant of a common position, as will be seen in further figures. The bending of the conductors has been optimised so that the die positions do not require changing in order to support alternative package function configurations.

Figure 4A schematically depicts the half bridge configuration of Figure 2B in more detail, with each switch implemented using two die; Figure 4B schematically depicts the half bridge configuration according to an exemplary embodiment, as a mechanical representation (plan view); and Figures 4C, 4D and 4E schematically depict the half bridge configuration of Figure 4B, as altemative exemplary embodiments.

Figure 4, comprising Figures 4A to 4E, schematically illustrates a half bridge configuration with each switch implemented using two die. The example shown uses four die 303, 304, 305, 306. The electrical circuit 201 is shown in Figure 4A. Die 303 and 306 are in parallel and form the upper switch. Die 305 and 306 are in parallel and form the lower switch.

Figure 4B shows a plan view from the top of a common flat die structure 401 where the die are not stacked using the first variant of the common die positions. Figure 4D shows a plan view from the top of an alternative embedment of a common flat die structure 403 where the DC power planes have been extended to increase coupling and reduce parasitic inductance. Figure 4E shows a side view stacked variant 404 which has the second variant of the die positions.

Figure 4C shows a third variant 402 of the common die positions where the die are stacked and the sources of the die in the lower level of the stack are close and can be bonded to the drains of the die in the upper level of the stack.

Within electrical circuit 201, each die 303 and 306 is connected in parallel with each die drain connected to the upper conductor 310 and each die source connected to the mid conductor 400. Each die 304 and 305 is connected in parallel with each die drain connected to the mid conductor 400 and each die source connected to the lower conductor 311.

Within die structure 401, each die 303, 304, 305 and 306 is connected to the appropriate conduction in the simplest fashion, being three separate flat conducting layers: upper conductor 405, mid conductor 406 and lower conductor 407.

These layers are extended in die structure 403 in orderto increase coupling and reduce parasitic inductance: upper conductor 414, mid conductor 415 and lower conductor 416.

In die structure 404, the die are stacked in the second variant of the common die position. The upper conductor 411, the mid conductor 412 and the lower conductor 413 are not required to bend and thus may be made of simple flat layers.

In die structure 402, the upper conductor 408, the mid conductor 409 and the lower conductor 410 are not required to bend and thus may be made of simple flat layers. The source of die 303 may be in direct contact with the drain of die 304, or they may be pre-bonded before placement, or they may be bonded in situ. This is similar in the case of die 306 and 305.

Figure 5 schematically illustrates a pair of half bridge configurations with each switch implemented using one die. The example shown uses four die. The electrical circuit is shown in 202. 303 and 306 are in parallel and form the upper switch. 305 and 306 are in parallel and form the lower switch.

Figure 5A schematically depicts the pair of half bridge configurations of Figure 2C in more detail, with each switch implemented using one die; Figure 5B schematically depicts the pair of half bridge configurations according to an exemplary embodiment, as a mechanical representation (plan view); and Figures 5C and 5D schematically depict the half bridge configuration of Figure 5B, as alternative exemplary embodiments.

Figure 5B shows a plan view from the top of a common flat die structure 503 where the die are not stacked using the first variant of the common die positions. Figure 5D shows a plan view from the top of an alternative embedment of a common flat die structure 505 where the DC power planes have been extended to increase coupling and reduce parasitic inductance. Figure 5C shows a side view stacked variant 504 which has the second variant of the die positions. Those skilled in the art will see how this configuration may be adapted to also use a structure similar to that shown in in Figure 4C.

Within die structure 202 of Figure 5A, each die 303 and 306 is connected with each die drain connected to the upper conductor 310 and each die source connected to a different mid conductor: mid conductor 500 in the case of die 303 and mid conductor 501 in the case of die 306. Each die 304 and 305 is connected with each die source connected to the lower conductor 311 and each die drain connected to a different mid conductor: mid conductor 500 in the case of die 304 and mid conductor 501 in the case of die 305.

Within die structure 503, each die 303, 304, 305 and 306 is connected to the appropriate conduction in the simplest fashion, being four separate flat conducting layers: upper conductor 504, mid conductors 505 and 506 and lower conductor 507.

These layers are extended in die structure 505 in order to increase coupling and reduce parasitic inductance: upper conductor 512, mid conductors 513 and 514 and lower conductor 515.

In die structure 504, the die are stacked in the second variant of the common die position. The upper conductor 508, the mid conductors 509 and 510 and the lower conductor 511 are not required to bend and thus may be made of simple flat layers.

Figure 6A schematically depicts the four die in a totem pole configuration of Figure 2D in more detail, and also how the external connection of two additional diodes may provide a three-level inverter phase overall; Figure 6B schematically depicts the four die in the totem pole configuration according to an exemplary embodiment, as a mechanical representation (plan view); and Figure 6C schematically depicts the totem pole configuration of Figure 6B, as alternative exemplary embodiments.

Figure 6, comprising Figures 6A to 6C, schematically illustrates four die in a totem pole configuration and also how the external connection of two additional diodes 601 and 602 would provide a three-level inverter phase overall. When used as a three-level inverter phase, the upper DC supply would be on conductor 310, the mid voltage on conductor 603 and the lower DC supply on conductor 311. Die 303 is the upper switch and is connected between the upper internal connector 604 and the upper DC supply would be on conductor 310. Die 304 is the upper mid switch and is connected between the phase output conductor 605 and the upper internal connector 604. Die 305 is the lower mid switch and is connected between the lower internal connector 606 and the phase output conductor, 605. Die 306 is the lower switch and is connected between the lower DC supply on conductor, 311, and the lower internal connector 606.

Figure 6B shows a plan view from the top of a common flat die structure 608 where the die are not stacked using the first variant of the common die positions. Figure 6C shows a side view stacked variant 609 which has the second variant of the die positions. Those skilled in the art will see how this configuration may be adapted to also use a structure similar to that shown in die structure 402 of Figure 4C.

Within die structure 608, each die 303, 304, 305 and 306 is connected to the appropriate conduction in the simplest fashion, being four separate flat conducting layers: upper dc conductor 610, internal conductors 613 and 611, lower dc conductor 614 and phase output conductor 612.

Within die structure 609, the die are stacked in the second variant of the common die position: upper dc conductor 615, internal conductors 618 and 616, lower dc conductor 614 and phase output conductor 617.

Figure 7A schematically depicts the four die as a bidirectional switch of Figure 2E in more detail, connected to a half bridge to provide a T-Type three-level inverter phase; Figure 7B schematically depicts the T-Type three-level inverter phase according to an exemplary embodiment, as a mechanical representation (plan view); and Figure 7C schematically depicts T-Type three-level inverter phase of Figure 7B, as alternative exemplary embodiments.

Figure 7, comprising Figures 7A to 7C, schematically illustrates two die as a bidirectional switch die 303 and 304 connected to a half bridge die 306 and 305 to provide a T-Type three-level inverter phase.

In die structure 204, when used as a T-Type three-level inverter phase, the upper DC supply is on conductor 310, the mid voltage on conductor 703 and the lower DC supply on conductor 311.

Die 303 and 304 have drains connected to connector 704 to form a bidirectional switch.

Alternatively, both sources could be connected via 704 instead of both drains. Alternatively, each die 303 and 304 could be connected in parallel to the mid voltage supply, 703, through diodes in a parallel T configuration. Those skilled in the art would be able to make this modification to the structure. In the current example, die 303 has source connected to the mid voltage supply, 703 and die 304 has source connected to the output phase conductor, 705.

Die 306 and 305 form a half-bridge between the upper DC supply conductor 310 and the lower DC supply conductor 311, with the output phase conductor 705.

Figure 7B shows a plan view from the top of a common flat die structure 700 where the die are not stacked using the first variant of the common die positions. Figure 7C shows a side view stacked variant 701 which has the second variant of the die positions. Those skilled in the art will see how this configuration may be adapted to also use a structure similar to that shown in die structure 402 of Figure 4C.

Within die structure 700, each die 303, 304, 305 and 306 is connected to the appropriate conduction in the simplest fashion, being four separate flat conducting layers: upper dc conductor 707, internal conductor 708 to form a bidirectional switch and lower dc conductor 711, phase output conductor 710 and mid voltage conductor 709.

Within die structure 701, the die are stacked in the second variant of the common die position, comprising upper dc conductor 712, internal conductor 714 to form a bidirectional switch, lower dc conductor 716, phase output conductor 715 and mid voltage conductor 713.

Figure 8A schematically depicts the pair of two die as a bidirectional switch with a common output of Figure 2F in more detail; Figure 8B schematically depicts the pair of two die according to an exemplary embodiment, as a mechanical representation (plan view); and Figure 8C schematically depicts the pair of two die, as alternative exemplary embodiments.

Figure 8, comprising Figures 8A to 8C, schematically illustrates a pair of two die as a bidirectional switch with a common output.

Die 303 and 304 have drains connected to connector 804 to form a bidirectional switch.

Alternatively, both sources could be connected instead. Those skilled in the art would be able to make this modification to the structure. In this example, die 303 has source connected to conductor 803 and die 304 has source connected to conductor 805. Die 305 and 306 provide a second bidirectional switch, die 305 has source connected to the conductor 806 and die 306 has source connected to the conductor 805. In this example, die 304 and 306 are connected to a common conductor 805. Alternatively, die 304 and 306 may not share a common conductor.

Figure 8B shows a plan view from the top of a common flat die structure 802 where the die are not stacked using the first variant of the common die positions. Figure 8C shows a side view stacked variant 801 which has the second variant of the die positions. Those skilled in the art will see how this configuration may be adapted to also use a structure similar to that shown in die structure 402 of Figure 4C.

Within die structure 802, each die 303, 304, 305 and 306 is connected to the appropriate conduction in the simplest fashion, being four separate flat conducting layers: die 304 between conductors 810 and 809; die 303 between conductor 809 to form a bidirectional switch with die 304 and conductor 808; die 305 between conductors 811 and 812; and die 306 between conductor 812 to form a bidirectional switch with die 305 and conductor 808.

Within die structure 801, the die are stacked in the second variant of the common die position: die 304 between conductor 813 and 814; die 303 between conductor 814 to form a bidirectional switch with die 304 and conductor 817; die 305 between conductors 815 and 816; and die 306 between conductor 816 to form a bidirectional switch with die 305 and conductor 817.

Those skilled in the art will see how other topologies can be created adapting these methods.

Those skilled in the art will see how the structure may contain any form of electrical or electronic component and how either power conductors, signal conductors or both can be provided in the same structure. The use of a common die location simplifies the design of the signal connections and placement of other components.

Production using additive manufacturing.

Figure 9 schematically illustrates an additive manufacturing process, in this example an ink jetting method. Ink jetting is an Additive Manufacturing process in which a binding liquid is selectively deposited to join powder material together to form a 3D part. An ink jetting procedure generally consist of the following steps, however, those skilled in the art will appreciate that other procedures exist: 1. The powder material is spread over the build platform 907 using a roller 903.

2. The print head 902 moves on an XY bar 901 and deposits the binder adhesive on top of the powder 906 where required.

3. The build platform 907 is lowered by the model's layer thickness 908.

4. Another layer of powder 906 is spread overthe previous layer. The object is formed where the powder is bound to the liquid.

5. The unbound powder 906 remains in position surrounding the object 904.

6. The process is repeated until the entire object 904 has been made.

7. Un-dosed powder is removed.

8. The part is sintered.

In one embodiment, two inks are used. The use of these two inks in the creation of a structure may control that structure's conductive or insulative properties.

As an example, and those skilled in the art will be able to produce other examples, the powder may be copper with D10 of 20 pm and D90 of 70 pm for reasons of making the powder spreadable.

To create a conductive structure, a first ink is used as a binder, for example, copper formate tetrahydrate and includes stabilisers, for example, octylamine aminomethyl propanol AMP. For the highest level of conductively the ink saturates the powder, for example, two passes with 12 pl (picolitre) drops with a dots per inch (dpi) of 360.

To create an insulator structure, a highly alkaline second ink solution is used which provides oxygen, for example, A1203 nanoparticles (preferably as small as possible to aid sintering of resistive layer at Cu sintering temperatures) suspended in liquid and/or yttrium butoxide and/or some other oxide forming butoxide. Oxidisation either takes place immediate or during subsequent heating steps. For the highest level of insulation, the ink saturates the powder, for example, two passes with a 12 pl drops with a dots per inch of 360.

Software may be used to calculate the necessary dosage based on chemical analysis and processors or from experimental data.

To create a cooling channel, or a void, the powder is not dosed and thus becomes a support structure during printing. The un-dosed powder is then removed before sintering, for example, via an air jet.

Additional material or fluid layers for example dielectrics, phase change materials or plastics, can be printed or sprayed as an additional ink. Alternatively, fluid may be inserted during pause in the additive manufacture as was described for the case of the power semiconductor die. Alternatively, the dielectric could be poured into a surface orifice and thus into a void created when the un-dosed powder was removed. The orifice would then be filled.

The die may be placed using the same xy bar as the ink jetting heads 902. In this case the Z axis may be controlled by the build plate height 908. This may be controlled via software. Additive manufacture could be used to create a section of the part before inserting one or more components on the last layer before, or after, that layer is sintered or consolidated. Components could be inserted on a green or brown part then build continues. The components insertion could be in a different machine or a function of the additive manufacture machine.

Alternatively, a subassembly of component(s) (with structure below) is placed into additive manufacture build area before powder bed placed to surround and above. This subassembly could be manufactured using a range or manufacturing techniques.

Alternatively, the additive manufacture may build on top of component(s).

Incorporating thermal features Figure 10 schematically illustrates the incorporation of insulators (1004), fully encapsulating (except external connection areas) in this example.

Drawing 1000 shows an insulating structure, 1004, which is in contact with the conductor structures, 1001, 1002 and 1003, and also the semiconductor die, 303, 304, 305, and 306. In the embodiment illustrated in drawing, the conductors, 1001, 1002 and 1003 emerge from the insulative structure.

Those skilled in the art will see how other structures could be formed using this method and that the insulator structure may connect with the conductive structures only in certain areas. Multiple insulator structures may be present in the same part.

The conductive structures and insulative structures may be manufactured as the same part or be separate parts brought together. Each structure may be manufactured using methods including additive manufacturing and subtractive manufacturing. Additive manufacturing may include those listed before or the build-up of a stack of individual layers (laminations) for example a printed circuit board or a series of deposited material layers.

The insulating structure, 1004, serves to protect the die and other items contained within it from environmental and physical stresses.

Figure 11 schematically illustrates the incorporation of coolant fluid channels (1101) within the structure, cooling electrical conductors (1001, 1002 and 1003) and insulation structure (1004) in this example.

Drawing 1100 shows an example fluid coolant circuit, 1101, with an inlet, 1102, and outlet, 1103. The coolant circuit, 1101, passes through the insulation structure, 1004, before passing within the electrical conductors, 1001. Those skilled in the art will appreciate that the fluid channel could alternatively adjoin the conductor, particularly where the fluid is conductive.

The fluid coolant circuit, 1101, passes through the insulation structure, 1004, near the semiconductor die, 304. Alternatively, the fluid could come in direct contact with the die using an adaptive structure.

Drawing 1100 shows an example where the fluid coolant circuit, 1101, passes through all of the structures within the part. Those skilled in the art will be able to adapt this approach to other structural and electrical designs where the fluid coolant circuit flows through or adjoins, or both, some or all the structures.

Figure 12 schematically depicts the primary current loops within a T-type topology under the three main switching states. Diagram element numbers are by reference to Figure 7A.

Loopl is when the bidirectional switch (made of two switches 304 and 303 and conductor 704 in the diagram) connected to the mid-voltage 703 (between the two capacitors) and the upper switch (306) are switching.

Loop 2 is when the bidirectional switch (made of two switches in the diagram) connected to the mid-voltage 703 (between the two capacitors) and the lower switch (305) are switching.

Loop 3 is during switching of the upper or lower switches, which are connected to the positive (310) and negative (311) dc supplies.

Figure 13 schematically depicts how the 3D routing of the positive and negative dc conductors close to the mid-voltage conductor and bidirectional switch can be used to reduce the parasitic inductance. Diagram element numbers are by reference to Figure 7A.

T-type configurations are extremely difficult to design using conventional technologies as there are multiple parallel plains which require careful routing to reduce the parasitic ac inductance during the three main switching events. However, the methods described herein enable the parasitic ac inductance to be reduced via the provided packaging.

The positive (310) and negative (311) dc conductors close (i.e. proximal) to the mid-voltage conductor (703) and mid voltage bidirectional switch (304, 704, 303) can be used to reduce the parasitic inductance of all three loops described in Figure 12.

Figure 14A schematically depicts a method according to an exemplary embodiment; and Figure 14B schematically depicts a method according to an exemplary embodiment.

In more detail, Figure 14A schematically depicts a method of packaging semiconductor die, particularly the half bridge configuration of Figure 2B and similar to the half bridge configuration of Figure 4D, showing layers A to I. Layer C is under the die and contains the three conductors (one of which connects to two die) ready for the die to be placed.

Layer D has the die placed (onto the conductive areas) and a layer of powder placed and then inked (where needed). The die is surrounded (up to it upper face) by insulator. The two horizontal bars are parts of the conductors. The remainder is un-dosed powder.

Layer E has powder spread which is dosed to produce conductors attached to the top fact of the die. The remaining layer area is either dosed insulator or un-dosed powder.

In more detail, Figure 14B schematically depicts a method of packaging semiconductor die, particularly the T-Type three-level inverter phase configuration of Figure 2E and similar to the T-type three-level inverter phase configuration of Figure 7B, showing layers A to F. Layer C is under the die and contains the three conductors (one of which connects to two die) ready for the die to be placed.

Layer D has the die placed (onto the conductive areas) and a layer of powder placed and then inked (where needed). The die is surrounded (up to it upper face) by insulator. The horizontal bar is part of the conductor. The remainder is un-dosed powder.

Layer E has powder spread which is dosed to produce conductors attached to the top fact of the die. The remaining layer area is either dosed insulator or un-dosed powder.

Figure 15 schematically depicts a method according to an exemplary embodiment.

The method is of packaging semiconductor die, the method comprising: placing a first set of semiconductor die, including a first semiconductor die, at a respective first set of placements, including a first placement (S1501); and providing a first package, having a first structure, for the first set of semiconductor die comprising additive manufacturing, for example ink jetting, and/or hybrid manufacturing (61502).

Figure 16 schematically depicts a method according to an exemplary embodiment.

The method is of ink jetting, the method comprising: providing a first layer of a first powder comprising a first material (S1601); forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation (S1602); and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation (S1603) Figure 17 schematically depicts a method according to an exemplary embodiment.

The method is of packaging semiconductor die, the method comprising: placing a first set of semiconductor die, including a first semiconductor die, at a respective first set of placements, including a first placement (S1701); and providing a first package, having a first structure, for the first set of semiconductor die comprising ink jetting (S1702) comprising: providing a first layer of a first powder comprising a first material; forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation.

Although a preferred embodiment has been shown and described, it will be appreciated by those skilled in the art that various changes and modifications might be made without departing from the scope of the invention, as defined in the appended claims and as described above. Notes

In addition, while a particular feature or aspect of an embodiment of the invention may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise".

Furthermore, it should be understood that embodiments of the invention may be implemented in discrete circuits, partially integrated circuits or fully integrated circuits or programming means. Also, the term "exemplary" is merely meant as an example, rather than the best or optimal. It is also to be appreciated that features and/or elements depicted herein are illustrated with particular dimensions relative to one another for purposes of simplicity and ease of understanding, and that actual dimensions may differ substantially from that illustrated herein.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof Attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at most some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, and drawings) may be replaced by alternative features sewing the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims (15)

1. CLAIMS1. A method of packaging semiconductor die, the method comprising: placing a first set of semiconductor die, including a first semiconductor die, at a respective first set of placements, including a first placement; and providing a first package, having a first structure, for the first set of semiconductor die comprising ink jetting comprising: providing a first layer of a first powder comprising a first material; forming a first part having a first electrical conductivity comprising selectively jetting the first layer using a first ink formulation; and forming a second part having a second electrical conductivity comprising selectively jetting the first layer using a second ink formulation.
2. 2. The method according to claim 1, wherein the first ink formulation oxidises the first material, for example upon contacting and/or heating.
3. 3. The method according to any previous claim, wherein the second ink formulation reduces the first material, for example upon contacting and/or heating.
4. 4. The method according to any previous claim, wherein the first part and the second part mutually partially overlap and/or wherein the first part and the second part are mutually adjacent.
5. 5. The method according to any previous claim, wherein the first part and the second part define an electrical conductivity gradient.
6. 6. The method according to any previous claim, comprising electrically isolating the second part using the first part.
7. 7. The method according to any previous claim, wherein the second part comprises and/or is an electrical coupling for an electrical component.
8. 8. The method according to any previous claim, comprising selectively jetting the first layer using a third ink formulation.
9. 9. The method according to any previous claim, comprising preparing the first ink formulation and/or the second ink formulation.
10. 10. The method according to any previous claim, comprising: providing a second layer on the first layer; selectively jetting the second layer using the first ink formulation; and/or selectively jetting the second layer using the second ink formulation.
11. 11. A computer comprising a processor and a memory configured to implement, at least in part, a method according to any of claims 1 to 10, a computer program comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to any of claims 1 to 10 or a non-transient computer-readable storage medium comprising instructions which, when executed by a computer comprising a processor and a memory, cause the computer to perform a method, at least in part, according to any of claims 1 to 10.
12. 12. A packaged semiconductor die comprising: a first set of semiconductor die, including a first semiconductor die, placed at a respective first set of placements, including a first placement; and a first package, having a first structure, for the first set of semiconductor die, wherein the first package is provided, at least in part, by ink jetting wherein the first package comprises: a first layer of a bound first powder comprising a first material; wherein the first layer comprises: a first part having a first electrical conductivity formed by selectively jetting the first layer using a first ink formulation; and a second part having a second electrical conductivity formed by selectively jetting the first layer using a second ink formulation.
13. 13. The packaged semiconductor die according to claim 12, wherein the first set of semiconductor die includes N semiconductor die, wherein N is a natural number greater than or equal to 2, for example 2, 3, 4, 5, 6, 7, 8, 9, 10 or more.
14. 14. The packaged semiconductor die according to any of claims 12 to 13, wherein the first structure comprises a first set of electrical isolators, including a first electrical isolator, wherein the first electrical isolator is disposed to electrically isolate a part of the first semiconductor die.
15. 15. The packaged semiconductor die according to any of claims 12 to 14, wherein the first structure comprises a first set of thermal couplings, including a first thermal coupling, wherein the first thermal coupling is thermally coupled to the first semiconductor die.