GB2630781A

GB2630781A - Memory error tracker

Info

Publication number: GB2630781A
Application number: GB2308498.1A
Authority: GB
Inventors: Julian Moule David; Singh Kashmir
Original assignee: ZF Automotive UK Ltd
Current assignee: ZF Automotive UK Ltd
Priority date: 2023-06-07
Filing date: 2023-06-07
Publication date: 2024-12-11
Also published as: GB202308498D0

Abstract

A method of tracking memory error defects of a control system includes receiving at a processor 540 error correction code ECC information from a memory unit 510, including location information, and determining the cumulative number of error correction codes for each memory location. The cumulative number or rate of occurrence of ECCs may be compared to a threshold (stored in a lookup table) and an output flag or warning alert alarm sounded or lighted 570 when a threshold is exceeded. A threshold may be adjusted, increased, decreased, depending on a memory unit parameter such as operational time, age, temperature, workload, altitude location. A failure mode may be determined by comparing the active, operational time or age of the memory unit to a threshold. Whether a code is new, repeated or code type, may be determined. The memory units may form part of a microprocessor. An assessment of memory unit condition and determination of failure likelihood may be made. A power steering control system for a vehicle may use the memory error tracking method.

Description

MEMORY ERROR TRACKER

This invention relates generally to a memory error tracker. More specifically, although not exclusively, this invention relates to a method of tracking memory errors of a control system, 5 a memory error tracking system, a steering control system comprising such a memory error tracking system and a vehicle comprising such a steering control system.

Control systems, for example as found within electric power steering systems, generally use a plurality of microcontrollers that each include a memory unit/ memory function. The memory unit is used to store instructions that are accessed and applied to incoming data or information, used to store information that is to be retained when power is removed and is essential to the successful function of the control system.

There are a number of mechanisms by which a memory unit can malfunction or fail, with one such mechanism being the corruption of a bit when data is being read from the memory unit. This is overcome through the use of error correction code (ECC) logic whereby a message can be recovered even if one or more bits are erroneously corrupted. ECC logic therefore reduces the likelihood of memory read failure and increases a memory unit's availability.

However, it has been found that in prior art control systems there is no association of memory errors with the location, operational usage or operational age of a memory unit. It has been found that such an association can allow for an assessment of the condition of a memory unit, and the determination of the likelihood of failure. In the case of safety critical control systems, such a determination can be particularly advantageous.

It has been found that one or more of the aforementioned issues may be overcome by determining the cumulative number of error correction codes associated with each memory location of a control system during operation thereof.

In accordance with the present invention, there is provided a method of tracking memory errors of a control system comprising a processor and a plurality of memory units, the method comprising: receiving, at the processor, error correction code information from one or more of the plurality of memory units, wherein the error correction code information comprises memory location information of the memory unit from the which the error correction code information is received; and determining, from the error correction code information, the cumulative number of error correction codes associated with each memory location during operation of the control 5 system.

Advantageously, by identifying the location of a memory unit from which error correction code information is received, a more reliable assessment of the condition of individual memory units of a control system can be made. This, in turn, can provide an improved determination of the likelihood of failure of a control system as a whole, or individual parts thereof.

Instead of being a method of tracking memory errors of a control system, the method may instead be a method of tracking memory errors of a sensor or computer device.

The method may comprise receiving, at the processor, error correction code information from each of the plurality of memory units.

The processor and memory units may be connected via a bus, e.g. a high-speed bus.

The error correction code information may be received by the processor in the event that one or more of the memory units experiences an error, for example a memory read error, bit corruption or a bit error/bit flip error.

The error correction code information may comprise an error correction code. The error correction code may be an identifier of an error. The error correction code may be an identifier of which of the plurality of memory units has experienced an error. One or more, or each, of the memory units may incorporate error correction code logic that enables the correct data to be read from a memory unit in the event of an error, e.g. a bit error. The so error correction code logic may determine or output the error correction code information from a respective memory unit.

The memory location information or memory location may be the location of a memory unit within the control system or the location of a memory error within a respective memory unit.

The memory location information may comprise a memory address. The memory location may comprise an address or location within a memory map.

In an embodiment, one or more of the memory units may form part of a microcontroller. In an embodiment, one or more of the memory units may be a semiconductor memory The method may comprise determining, e.g. from the error correction code information, the rate of occurrence of error correction codes received from each of the plurality of memory units.

The method according may comprise determining, e.g. from the error correction code information, the rate of occurrence of error correction codes received from one or more of the plurality of memory units.

The method may comprise comparing the cumulative number of error correction codes, e.g. of a respective memory unit, with a predetermined error correction code threshold for said respective memory unit.

The method may comprise comparing the cumulative number of error correction codes from all memory units with a predetermined error correction code threshold for all memory units.

The method may comprise comparing the rate of occurrence of error correction codes, e.g. of a respective memory unit with a predetermined error rate threshold for said respective memory unit.

The method may comprise comparing the rate of occurrence of error correction codes for all memory units with a predetermined error rate threshold for all memory units.

Each memory unit may have a respective predetermined threshold. Each memory unit may have a respective predetermined error correction code threshold. Each memory unit may have a respective predetermined error rate threshold. The predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold may be determined based on the type or category of memory unit.

The method may comprise providing an alert or waming when the predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold is exceeded for a respective memory unit. The alert or warning may comprise an audible alarm or warning light. Additionally or alternatively, the alert or warning may comprise providing or sending a signal to a remote system.

In an embodiment, at least one predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold may be adjustable. The method may comprise adjusting at least one predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold.

In some embodiments, at least one predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold may change over time. The method may comprise changing or adjusting at least one predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold over time.

The method may comprise determining an operational parameter of a memory unit. The method may comprise determining an operational parameter of each of the memory units. The operational parameter may comprise one or more of an operational time of a memory unit, an age or an operational age of a memory unit, an operational temperature of a memory unit, a workload or frequency of use of a memory unit, a stored usage history of a memory unit, a storage period of a memory unit, a storage condition of a memory unit and/or the location of the memory unit.

The operational time of a memory unit may comprise the cumulative time in which the memory unit is in an active or operational state, e.g. throughout its life. The operational time of a memory unit may comprise the age or operational age of the memory unit. The age or operational age of a memory unit may be a time since manufacture of the memory unit.

The location of the memory unit may be the location within a control system. The location of the memory unit may be an environmental or geographical location of operation, e.g. a history of the environmental or geographical location of the memory unit throughout its life. The location, e.g. the environmental or geographical location, of the memory unit may be an altitude of operation, e.g. a history of the altitude of operation of the memory unit throughout its life.

The stored usage history of a memory unit may comprise a record of the memory unit being in an active or operational state, e.g. throughout its life, or a record of an operational temperature history, e.g. throughout its life.

The method may comprise adjusting at least one predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold of a respective memory unit in dependence on a determined operational parameter of the memory unit. The method may comprise reducing the error correction code threshold with increased operational time of a respective memory unit and/or with increased age or operational age of a respective memory unit. The method may comprise reducing or increasing the error correction code threshold with reduced frequency of use of a respective memory unit.

The method may comprise adjusting at least one predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold of a respective memory unit in dependence on a determined operational parameter of the memory unit in comparison with population data.

The operational parameter may be of a particular vehicle, e.g. within which the memory unit is installed.

A particular memory unit or vehicle may be determined to have different behaviour to the other memory units or vehicles in or proximate a particular location. The method may comprise retrieving population data from a remote storage means, e.g. when the vehicle or memory unit is connected thereto. The population data may represent the general or averaged behaviour or operational parameter of memory units or vehicles in or proximate a particular location.

The operational parameter may be a memory unit or vehicle location, overall or cumulative vehicle mileage, average annual vehicle mileage and/or average operational altitude of the 30 vehicle.

The method may comprise reducing the error rate threshold with increased operational time of a respective memory unit and/or with increased operational age of a respective memory unit. The method may comprise reducing or increasing the error rate threshold with reduced 35 frequency of use of a respective memory unit.

The method may comprise determining a failure mode or a predicted failure mode (hereinafter failure mode) of a memory unit.

The failure mode of a memory unit may be determined by: comparing the cumulative number of error correction codes of a memory unit with a predetermined error correction code threshold for said respective memory unit; and/or by comparing the rate of occurrence of error correction codes of a memory unit with a predetermined error rate threshold for said respective memory unit; if the error correction threshold and/or error rate threshold is exceeded, determine the 10 failure mode by comparing the cumulative time in which the memory unit is in an active or operational state throughout its life or the operational age of the memory unit with one or more predetermined failure mode thresholds.

In an embodiment, the predetermined threshold, predetermined failure mode threshold(s), predetermined error correction code threshold and/or predetermined error rate threshold is/are stored in and/or retrieved from a lookup table. The lookup table may be stored within a memory of the control system or stored externally of the control system, e.g. on an external server or memory.

zo The method may comprise comparing with two failure mode thresholds, e.g. a first failure mode threshold and a second failure mode threshold.

In some embodiment, the predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold represents an expected background cumulative number of error correction codes and/or rate of occurrence of error correction codes of a memory unit.

The failure mode of a respective memory unit may be determined by comparing the rate of occurrence of new error correction codes of a memory unit with a predetermined error rate threshold for said respective memory unit.

If it is determined that the rate of occurrence of new error correction codes is greater than or exceeds the error rate threshold, e.g. as determined from the lookup table, then the cumulative time in which the memory unit has been in an active or operational state 35 throughout its life may be determined or the age of the memory unit may be determined.

In order to determine the failure mode of the memory unit, the cumulative time in which the memory unit has been in an active or operational state throughout its life may be compared with one or more predetermined failure mode thresholds.

In order to determine the failure mode of the memory unit, the age or operational age of the memory unit may be compared with one or more predetermined failure mode thresholds.

A failure mode may be characterized as an infant failure mode if the cumulative time or age is less than a first failure mode threshold. A failure mode may be characterized as a midlife failure mode if the cumulative time or age is between the first failure mode threshold and a second failure mode threshold. A failure mode may be characterized as an aging failure mode if the cumulative time or age is greater than the second failure mode threshold.

If it is determined that the rate of occurrence of new error correction codes does not exceed the predetermined error rate threshold, then there is no failure mode of the respective memory unit.

The method may comprise providing an output flag or waming in dependence on the determined failure mode. The output flag or warning may be provided in the form of a warning in a written log, an audible alarm or a warning light.

The method may comprise determining from the received error correction code information whether a received error correction code is new or a repeat, e.g. for a respective memory unit.

A new error correction code may be unique, or one which has not been received within a given operational cycle of the memory unit. A new error correction code may be one which has not been received throughout the operational life of the memory unit.

A repeat error correction code may be one which has been received within a given operational cycle of the memory unit. A repeat error correction code may be one which has been received at some point throughout the operational life of the memory unit.

When determining the cumulative number of error correction codes, e.g. from a respective 35 memory unit or memory location, the method may comprise categorising the error correction codes in dependence on whether they are identified as new or repeat. The method may comprise determining a cumulative number of new error correction codes and/or a cumulative number of repeat error correction codes.

The method may comprise determining, e.g. from the error correction code information, the rate of occurrence of new error correction codes and/or repeat error correction codes received from one or more of the plurality of memory units.

The method may comprise comparing the cumulative number of new error correction codes, e.g. of a respective memory unit, with a predetermined new error correction code threshold for said respective memory unit.

The method may comprise comparing the cumulative number of repeat error correction codes, e.g. of a respective memory unit, with a predetermined repeat error correction code threshold for said respective memory unit.

The method may comprise comparing the cumulative number of new error correction codes from all memory units with a predetermined new error correction code threshold for all memory units.

The method may comprise comparing the cumulative number of repeat error correction codes from all memory units with a predetermined repeat error correction code threshold for all memory units.

The predetermined new error correction code threshold and predetermined repeat error correction threshold may be different from one another, e.g. for a respective memory unit.

The method may comprise comparing the rate of occurrence of new error correction codes, e.g. of a respective memory unit with a predetermined new error rate threshold for said respective memory unit.

The method may comprise comparing the rate of occurrence of repeat error correction codes, e.g. of a respective memory unit with a predetermined repeat error rate threshold for said respective memory unit.

The method may comprise comparing the rate of occurrence of new error correction codes for all memory units with a predetermined new error rate threshold for all memory units.

The method may comprise comparing the rate of occurrence of repeat error correction codes for all memory units with a predetermined repeat error rate threshold for all memory units.

The predetermined new error rate threshold and predetermined repeat error rate threshold may be different from one another, e.g. for a respective memory unit.

The method may comprise providing an alert or warning when the predetermined new error correction code threshold, predetermined repeat error correction code threshold, predetermined new error rate threshold and/or predetermined repeat error rate threshold is exceeded for a respective memory unit.

One or more of the predetermined threshold, predetermined error correction code threshold, predetermined error rate threshold, predetermined new error correction code threshold, predetermined repeat error correction code threshold, predetermined new error rate threshold and/or predetermined repeat error rate threshold may be a dynamic zo threshold.

The method may comprise determining from the received error correction code information the type of error experienced by a respective memory unit.

The method may comprise categorizing or labelling the type of error, e.g. bit error. The type of error may be a single bit error correction, a double bit error correction, a triple bit error correction or a quad bit error correction.

The method may comprise temporarily storing the error correction code information in a memory, e.g. a local memory of the processor or the memory of the memory unit that has experienced an error. The error correction code information may be temporarily stored in a memory buffer. The method may comprise temporarily storing the determined cumulative number of error correction codes and/or rate of occurrence of error correction codes in a memory or memory buffer.

The method may comprise sending the determined cumulative number of error correction codes and/or rate of occurrence of error correction codes to an external memory.

The method may comprise retrieving temporarily stored error correction code information from a memory, e.g. a memory unit or a memory buffer, and permanently or semi-permanently stored or previously stored error correction code information, e.g. from a memory of the processor, and determining the cumulative number of error correction codes and their locations based on the retrieved error correction code information.

In an embodiment, the method comprises moving the temporarily stored error correction code information, determined cumulative number of error correction codes and/or rate of occurrence of error correction codes to a permanent or semi-permanent memory, e.g. at the end of an operational cycle or prior to deactivation of the control system. A permanent or semi-permanent memory may be defined as memory in which its contents are retained after deactivation or power down.

The method may comprise retrieving the error correction code information, determined cumulative number of error correction codes and/or rate of occurrence of error correction codes using a communication interface, e.g. a port, communication port or an ethernet port.

The method may comprise retrieving the predetermined threshold, predetermined error correction code threshold, predetermined error rate threshold, predetermined new error correction code threshold, predetermined repeat error correction code threshold, predetermined new error rate threshold and/or predetermined repeat error rate threshold using a communication interface, e.g. a port, communication port or an ethernet port.

An operational cycle may be defined as the time between activation of the control system or a memory unit and subsequent deactivation or power down of the control system or memory unit.

The control system may be a vehicle steering system, e.g. a vehicle power steering system or a vehicle steer-by-wire steering system The vehicle steering system may be for a vehicle of the type comprising a steering input member controlled by a driver of the vehicle, and a steering actuator which operates on the steered wheels of the vehicle as a function of the position of the steering input member.

The method may be a computer-implemented method.

Another aspect of the invention provides a memory error tracking system for use in a control system comprising a processor operatively connected with a plurality of memory units; wherein the processor is configured to receive error correction code information from one or more of the plurality of memory units, the error correction code information comprising memory location information of the memory unit from which the error correction code information is received; and wherein the system further comprises a counter or accumulation counter operatively connected with the processor and configured to calculate the cumulative number of error correction codes associated with each memory location during operation of a control system.

The processor may be configured to compare the cumulative number of error correction codes with a predetermined error correction code threshold for a respective memory unit.

The memory error tracking system may comprise an alert or warning function configured to provide an alert or warning when the predetermined error correction code threshold and/or predetermined error rate threshold is exceeded for a respective memory unit. The alert or 20 warning function may comprise an audible alarm or waming light.

In an embodiment, one or more of the memory units forms part of a microcontroller, e.g. a semiconductor microcontroller.

The memory error tracking system may comprise a communication interface, e.g. a port, communication port or an ethernet port.

According to another aspect of the invention, there is provided a steering control system for a vehicle operating in accordance with the method described above or comprising a 30 memory error tracking system as described above.

According to another aspect of the invention, there is provided a vehicle steering system comprising a memory error tracking system as described above or a steering control system as described above.

According to another aspect of the invention, there is provided a vehicle comprising a memory error tracking system as described above, a steering control system as described above or a vehicle steering system as described above.

The vehicle may be of the type comprising a steering input member controlled by a driver of the vehicle, and a steering actuator which operates on the steered wheels of the vehicle as a function of the position of the steering input member.

For the avoidance of doubt, any of the features described herein apply equally to any aspect of the invention. For example, the memory error tracking system may comprise any one or more features of the method of tracking memory errors relevant to the memory error tracking system and/or the method may comprise any one or more features or steps relevant to one or more features of the memory error tracking system.

A further aspect of the invention provides a computer program element comprising computer readable program code means for causing a processor to execute a procedure to implement one or more steps of the aforementioned method.

A yet further aspect of the invention provides the computer program element embodied on 20 a computer readable medium.

A yet further aspect of the invention provides a computer readable medium having a program stored thereon, where the program is arranged to make a computer execute a procedure to implement one or more steps of the aforementioned method.

A yet further aspect of the invention provides a control means or control system or controller comprising the aforementioned computer program element or computer readable medium.

For purposes of this disclosure, and notwithstanding the above, it is to be understood that any controller(s), control units and/or control modules described herein may each comprise a control unit or computational device having one or more electronic processors. The controller may comprise a single control unit or electronic controller or alternatively different functions of the control of the system or apparatus may be embodied in, or hosted in, different control units or controllers or control modules. As used herein, the terms "control unit" and "controller" will be understood to include both a single control unit or controller and a plurality of control units or controllers collectively operating to provide the required control functionality. A set of instructions could be provided which, when executed, cause said controller(s) or control unit(s) or control module(s) to implement the control techniques described herein (including the method(s) described herein). The set of instructions may be embedded in one or more electronic processors, or alternatively, may be provided as software to be executed by one or more electronic processor(s). For example, a first controller may be implemented in software run on one or more electronic processors, and one or more other controllers may also be implemented in software run on or more electronic processors, optionally the same one or more processors as the first controller. It will be appreciated, however, that other arrangements are also useful, and therefore, the present invention is not intended to be limited to any particular arrangement. In any event, the set of instructions described herein may be embedded in a computer-readable storage medium (e.g., a non-transitory storage medium) that may comprise any mechanism for storing information in a form readable by a machine or electronic processors/computational device, including, without limitation: a magnetic storage medium (e.g., floppy diskette); optical storage medium (e.g., CD-ROM); magneto optical storage medium; read only memory (ROM); random access memory (RAM); erasable programmable memory (e.g., EPROM ad EEPROM); flash memory; or electrical or other types of medium for storing such information/instructions.

Within the scope of this application it is expressly intended that the various aspects, embodiments, examples and alternatives set out in the preceding paragraphs, in the claims and/or in the following description and drawings, and in particular the individual features thereof, may be taken independently or in any combination. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination, unless such features are incompatible. For the avoidance of doubt, the terms "may", "and/or", "e.g.", "for example" and any similar term as used herein should be interpreted as non-limiting such that any feature so-described need not be present Indeed, any combination of optional features is expressly envisaged without departing from the scope of the invention, whether or not these are expressly claimed. The applicant reserves the right to change any originally filed claim or file any new claim accordingly, including the right to amend any originally filed claim to depend from and/or incorporate any feature of any other claim although not originally claimed in that manner.

Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings in which: Figure 1 is a schematic illustration of a vehicle steering system in accordance with the present invention; Figure 2 is a schematic illustration of a power steering vehicle steering system in accordance with the present invention; Figure 3 is a schematic illustration of a memory error tracking system in accordance with the present invention; Figure 4 illustrates a method of tracking memory errors using the memory error tracking system of Figure 3; Figure 5 is a flow diagram illustrating control logic of the memory error tracking system of Figure 3; Figure 6 is a schematic illustration of a hardware implementation of the memory error tracking system of Figure 3; Figure 7 is a cumulative error correction threshold curve showing failure mode thresholds; Figure 8 illustrates an alternative method of tracking memory errors using a memory tracking system; and Figures 9a and 9b illustrate a method of updating thresholds based on location.

Figure 1 illustrates a vehicle steering system S for a vehicle incorporating a memory error tracking system 10 in accordance with the present invention. The vehicle steering system S includes a steering input member, in the form of a steering wheel A, to allow a driver of the vehicle to provide an input steering command. The steering wheel A is connected to an end of an elongate steering shaft B. A steering input applied through the steering wheel A is measured by a steering sensor forming part of the steering column assembly, shown schematically at C in Figure 1. An electrical signal representative of the steering input (i.e. the rotation of the steering wheel A and steering shaft B) is transmitted from the steering sensor C to a control system, in the form of a steering controller 20, which incorporates the memory error tracking system 10. The steering controller 20 controls a current provided to a steering actuator E, which is an electric motor in this example, in dependence on the electrical signal received from the steering sensor C. The steering actuator E applies the steering input to the steering axle F, and therefore steers the steered wheels G as a function of the rotational position of the steering wheel A. As will be described in greater detail below in respect of Figure 3, the memory error tracking system 10 is configured to determine the cumulative number of error correction codes associated with each of a plurality memory locations during operation of the steering controller 20.

It will be appreciated that the memory error tracking system 10 and steering controller 20 are shown in Figure 1 incorporated into a steer-by-wire vehicle steering system S. However, it will be appreciated that the memory error tracking system 10 and steering controller 20 may instead be incorporated into a power steering vehicle steering system S', as shown in Figure 2, with minor modification.

Figure 2 illustrates a vehicle steering system S' for a vehicle incorporating a memory error tracking system 10 in accordance with the present invention. The vehicle steering system S' is similar to the vehicle steering system S described above in respect of Figure 1 and includes a steering input member, in the form of a steering wheel A, to allow a driver of the vehicle to provide an input steering command. The steering wheel A is connected to an end of an elongate steering shaft B that provides a direct connection between the steering wheel A and the steering axle F. Figure 3 illustrates a memory error tracking system 10 as incorporated into the steering controller 20 as described above in respect of Figures 1 and 2. The memory error tracking system 10 includes a processor 30 operatively connected with a plurality of memory units 50. In this present embodiment, the processor 30 is a central processing unit of the steering controller 20 and is operatively connected with four memory units 50 by virtue of a wired connection 40. However, it will be appreciated that the processor 30 may instead be operatively connected to one or more memory units 50 via a wireless connection or via a high-speed bus. Alternatively, the one or more memory units 50 may be integral with the processor 30.

Each of the memory units 50 memory units is a semiconductor memory in this example and forms part of a respective microcontroller of the steering controller 20 (Figures 1 and 2). Furthermore, each of the memory units 50 has a different respective memory location. The memory location may be a location or address within a memory map.

The processor 30 further includes a counter or accumulation counter (hereinafter counter) 32 that is configured to calculate the cumulative number of error correction codes associated with each memory location during operation of steering controller 20 (Figures 1 and 2). The calculated cumulative number of error correction codes is stored in a local memory 34.

It will be appreciated that the memory error tracking system 10 may instead comprise a transmitter or transceiver configured to send the calculated cumulative number of error correction codes to an external memory.

It will be also appreciated that the counter 32 may not be provided as part of the processor 30, but may instead be provided as a standalone hardware element, e.g. as part of a separate processor. Furthermore, the memory 34 may not be integrated into the processor 30 but may instead be provided as a separate hardware component.

Figure 4 illustrates a method 100 of tracking memory errors using the memory error tracking system 10 of Figure 3.

At step 110, in the event that one or more of the memory units 50 experiences an error, for example a memory read error, bit corruption or a bit error/bit flip error, error correction code information is received by the processor 30. Each of the memory units 50 incorporates error correction code logic that enables the correct data to be read from a memory unit 50 in the event of a bit error. The error correction code information received at the processor 30 includes memory location information of the memory unit 50 from which the error correction code information is received.

At step 120 the counter 32 of the processor 30 determines, from the received error correction code information, the cumulative number of error correction codes associated with each memory location during operation of steering controller 20 (Figures 1 and 2).

Figure 5 shows a flow diagram 200 illustrating control logic that may be implemented into the memory error tracking system 10 as described above in respect of Figure 3. In particular, part of the control logic would be implemented into each of the memory units 50 and part would be implemented into the processor 30 of Figure 3, as shown by the dashed outlines in Figure 5.

In the present example, a respective memory unit 50 (Figure 3) experiences and identifies a memory error or failure. In particular, at steps 210a and 210b, in the event that a memory unit 50 experiences an error or a device defect, the error correction code logic of step 220 processes the error and determines error correction code information. In this present example, the errors experienced by the memory units 50 are categorised into hard errors in FLASH, LOGIC and SRAM memory at step 210a and soft errors affecting SRAM and LOGIC in step 210b. At step 220, the error correction code information includes location information.

At step 230, the processor 30 retrieves temporarily stored error correction code information from a memory, e.g. a memory buffer, and permanently or semi-permanently stored error correction code information. The cumulative number of error correction codes and their locations are determined.

The processor 30 then categorises the error correction codes in dependence on whether they are identified as new or repeat. At step 240 the processor 30 determines a cumulative number of new error correction codes based on their location and at step 250 the processor 30 determines a cumulative number of repeat error correction codes based on their location.

At step 260 processor 30 determines the rate of occurrence of new error correction codes and at step 270 the processor 30 determines the rate of occurrence of repeat error correction codes received from one or more of the plurality of memory units 50.

The processor outputs at steps 240 to 270 are brought together at step 280 in order to determine a predicted failure mode of a memory unit 50 by virtue of a calculation at step 290.

In the present example, the failure mode of a respective memory unit 50 is determined by comparing the rate of occurrence of new error correction codes with a predetermined error rate threshold for said respective memory unit 50. The predetermined error rate threshold is determined from a lookup table at step 290. The lookup table may be stored within a local memory 34 of the processor 30.

If it is determined that the rate of occurrence of new error correction codes is greater than or exceeds the error rate threshold as determined from the lookup table, then the cumulative time in which the memory unit 50 has been in an active or operational state throughout its life is provided at step 300 and one or more predetermined failure mode thresholds are provided at step 310. The information from steps 300 and 310 are brought together at step 320 and fed into the calculation at step 290.

In order to determine the failure mode of the memory unit 50, the cumulative time in which the memory unit 50 has been in an active or operational state throughout its life is compared with the one or more predetermined failure mode thresholds. In the present example, the failure mode may be characterised as shown in Figure 7 below. In particular, Figure 7 shows the change in the rate of occurrence of new error correction codes over time. The failure mode is characterized as an infant failure mode X, a midlife failure mode Y or an aging failure mode Z in dependence on the cumulative time provided at step 300. The data representative of Figure 7 is stored in a lookup table in the present example.

In this example, there are two failure mode thresholds T1, T2 provided at step 310. A failure mode is characterized as an infant failure mode X if the cumulative time provided at step 300 is less than or equal to T1. A failure mode is characterized as a midlife failure mode Y if the cumulative time provided at step 300 is between T1 and T2. A failure mode is characterized as an aging failure mode Z if the cumulative time provided at step 300 is greater than or equal to T2.

If it is determined that the rate of occurrence of new error correction codes does not exceed the error rate threshold, then there is no failure mode of the respective memory unit 50.

Finally, based on the determination of the failure mode at step 290, an output flag is set for information and to allow for an operational decision. If it is determined that the failure mode is an infant failure mode X, then an infant failure flag is provided at step 330. If it is determined that the failure mode is an midlife failure mode Y, then a midlife failure flag is provided at step 340. If it is determined that the failure mode is an aging failure mode Z, then an aging failure flag is provided at step 350. In this example, the output flag is provided in the form of a warning in the steering controller 20 fault logs.

Figure 6 shows an exemplary hardware implementation of the memory error tracking system 10 of Figure 3 into a steering controller 20 of Figures 1 and 2.

Figure 6 shows a processor 30 having a plurality of cores 30a, 30a, 30c connected to a plurality of memory units 50 via a high speed bus 60. A plurality of different memory units are provided including DFLASH, SRAM and PFLASH. Each provides error correction code information to the processor 30 via the high speed bus 60.

The memory error tracking system 10 is in communication with an external storage means 70 via a communication interface 80. The external storage means 70 is cloud storage in this example and stores data or information including error correction codes, the cumulative number of error correction codes associated with each memory location, various thresholds and output flags. The communication interface 80 may be an ethernet port to allow for connection with the steering controller 20 and includes a transmitter or transceiver for communication with the external storage means 70.

Figure 8 illustrates an altemative method of tracking memory errors using a memory error tracking system incorporated into a vehicle. Instead of processing of memory error correction code information taking place using a processor 30 (Figure 3) within the memory error tracking system 10, in this case the processing is carried out remotely.

In particular, at step 510 in the event that one or more of the memory units 50 experiences an error, for example a memory read error, bit corruption or a bit error/bit flip error, error correction code information is stored locally, e.g. within a microcontroller containing the memory unit 50.

At step 520, when the vehicle V is parked within a garage, is connected to an electric vehicle charging point or is being serviced, the stored error correction code information is transferred to a remote memory unit 530. The transfer may take place by means of a connection interface of the vehicle V, or wirelessly.

The error correction code information is then processed at a remote processing means 540, that carries out a similar process as described above in respect of Figures 3 to 5.

In the present example, at step 550, output flags are sent back to the vehicle V in 10 dependence on a determined failure mode, as described above in respect of Figure 5. The vehicle V receives the output flags whilst connected as per step 520.

At step 570 a warning light is provided in dependence on the determined failure mode.

Therefore, the method 500 is similar to that described above in respect of Figures 3 to 5, with the difference that processing takes place remotely of the memory error tracking system or vehicle V. Figures 9a and 9b illustrate the adjusting of at least one predetermined threshold, predetermined error correction code threshold and/or predetermined error rate threshold of a respective memory unit in dependence on a determined operational parameter of the memory unit of a particular vehicle V' in comparison with population data.

In particular, vehicle V' is determined to have different behaviour to the other vehicles V in this location. This can be determined using population data that is retrieved from a remote storage means when the vehicle V' is connected thereto, e.g. when parked within a garage, is connected to an electric vehicle charging point or is being serviced 600, as shown in Figure 9b. The other vehicles V of the population also contribute to this data stored within the remote storage means when they are connected.

In this case the operational parameter may be a vehicle location, overall or cumulative vehicle mileage, average annual vehicle mileage, average operational altitude of the vehicle.

It will be appreciated by those skilled in the art that several variations to the aforementioned embodiments are envisaged without departing from the scope of the invention.

It will also be appreciated by those skilled in the art that any number of combinations of the 5 aforementioned features and/or those shown in the appended drawings provide clear advantages over the prior art and are therefore within the scope of the invention described herein.

Claims

CLAIMS1. A method of tracking memory errors of a control system comprising a processor and a plurality of memory units, the method comprising: receiving, at the processor, error correction code information from one or more of the plurality of memory units, wherein the error correction code information comprises memory location information of the memory unit from the which the error correction code information is received; and determining, from the error correction code information, the cumulative number of error correction codes associated with each memory location during operation of the control system.
2. A method according to claim 1, comprising determining the rate of occurrence of error correction codes received from each of the plurality of memory units.
3. A method according to claim 1 or claim 2, comprising comparing the cumulative number of error correction codes with a predetermined error correction code threshold for a respective memory unit.
4. A method according to claim 2, comprising comparing the rate of occurrence of error correction codes of a memory unit with a predetermined error rate threshold for a respective memory unit.
5. A method according to claim 3 or claim 4, wherein each memory unit has a respective predetermined threshold.
6. A method according to claim 3 to 5, comprising providing an alert when the predetermined threshold is exceeded for a respective memory unit.
7. A method according to any one of claims 3 to 6, wherein at least one predetermined threshold is adjustable.
8. A method according to claim 7, wherein at least one predetermined threshold changes over time.
9. A method according to claim 7 or claim 8, comprising determining an operational parameter of a memory unit, wherein the operational parameter comprises one or more of an operational time of a memory unit, an operational age of a memory unit, a workload of a memory unit and/or the location of the memory unit.
10. A method according to claim 9, comprising adjusting at least one predetermined threshold of a respective memory unit in dependence on a determined operational parameter of the memory unit.
11. A method according to claim 10, comprising reducing the error correction code threshold with increased operational time of a respective memory unit or with increased operational age of a respective memory unit.
12. A method according to any preceding claim, comprising determining a failure mode of a memory unit by: comparing the cumulative number of error correction codes of a memory unit with a predetermined error correction code threshold for said respective memory unit; and/or by comparing the rate of occurrence of error correction codes of a memory unit with a predetermined error rate threshold for said memory unit; if it is determined that either the error correction threshold or error rate threshold is exceeded, determine the failure mode by comparing the cumulative time in which the memory unit is in an active or operational state throughout its life or the operational age of the memory unit with one or more predetermined failure mode thresholds.
13. A method according to any one of claims 3 to 11 wherein the predetermined threshold(s) is/are stored in a lookup table.
14. A method according to claim 13, wherein the predetermined threshold(s) represents an expected background cumulative number of error correction codes and/or rate of occurrence of error correction codes of a memory unit.
15. A method according to any preceding claim, comprising determining from the received error correction code information whether a received error correction code is new or a repeat.
16. A method according to any preceding claim, comprising determining from the received error correction code information the type of error experienced by a respective memory unit.
17. A method according to any preceding claim, comprising temporarily storing the error correction code information in a memory.
18. A method according to claim 17, wherein the temporarily stored error correction code information is moved to a permanent memory at the end of an operational cycle.
19. A memory error tracking system for use in a control system comprising a processor operatively connected with a plurality of memory units; wherein the processor is configured to receive error correction code information from one or more of the plurality of memory units, the error correction code information comprising memory location information of the memory unit from which the error correction code information is received; and wherein the system further comprises a counter operatively connected with the processor and configured to calculate the cumulative number of error correction codes associated with each memory location during operation of a control system.
20. A memory error tracking system according to claim 19, wherein the processor is configured to compare the cumulative number of error correction codes with a predetermined error correction code threshold for a respective memory unit.
21. A memory error tracking system according to claim 20, comprising an alert function configured to provide an alert when the predetermined error correction code threshold is exceeded for a respective memory unit.
22. A memory error tracking system according to any one of claims 19 to 21, wherein one or more of the memory units forms part of a microcontroller.
23. A steering control system for a vehicle operating in accordance with the method of any of claims 1 to 18 or comprising a memory error tracking system according to any of claims 19 to 22.
24. A vehicle comprising a memory error tracking system according to any one of claims 19 to 22 or a steering control system according to claim 23.