GB2612554A - An enhanced processor data transport mechanism - Google Patents

Abstract

Disclosed herein are methods, systems, and devices for providing an enhanced processor data transport mechanism for increased throughput and mitigation of data starvation. In at least one embodiment, the invention provides the transport mechanism for all high capacity communications between integrated circuits (ICs) inside a computer or data processing system; the CPU, main memory, boot memory, mass storage, graphics, a low speed Input- Output (I/O) controller, and high speed I/O ports. The transport mechanism is deliberately void of any instruction sets or data orientation of its payload contents. Traffic routing and switching is controlled at the transport layer only. This allows the same transport infrastructure to carry all high capacity traffic between different ICs, with instructions, data orientation and data structure controlled by upper layer protocols that are applicable to the end points only and irrelevant to any intermediate ICs that just happen to switch the payload from source to destination.

Claims (21)

1. A universal transport mechanism to carry all high capacity, high speed communications between Integrated Circuits (IC) inside a data processing system using signal switching methods that provide for more bandwidth per IC pin than traditional methods for the purpose of: said transport mechanism to carry more data into and out of a Central Processing Unit (CPU) Integrated Circuit (IC) or other controller IC, per signal pin of said IC, than any Double Data Rate (DDR) mechanism in existence at the time of this invention disclosure per signal pin, whereas a small number of multiple instances of said transport mechanism are able to carry more data than a single instance of DDR using fewer pins among all of said instances of the transport mechanism than a single instance of a DDR implementation, and the CPU is able to host over 70 instances of said transport mechanism as is the case for existing technology at the time of this invention disclosure, thus mitigating a major problem with CPUs known as data starvation, and there is no practical upper limit to the number instances of the transport mechanisms an IC may have; said transport mechanism allows high use resources to be directly connected to said CPU or controller to minimize latency, and said high use resources are also connected to other less frequently used resources to enable said less frequently used resources to be accessible to the CPU or controller over the same pins of said CPU or controller as said high use resources, thus allowing all communications pins of a CPU or controller meant for high speed input and output to be used to access any resource the CPU or controller needs in the performance of its duties; and said transport mechanism carries a payload between two endpoints whose structure and organization is irrelevant to the transport mechanism, enabling any intermediate resource between a payload source and payload destination to switch said payload towards its destination even if the payload structure, content, and organization is incomprehensible to said intermediate resource.

2. The transport mechanism according to claim 1, further comprising of ICs each with a multiplicity of the transport system mechanisms: on one or more CPUs or other controllers of the data processing system; and on high use resources such that said resources can be connected directly to one or more CPUs or other controllers with multiple instances of the transport mechanism and said high use resources provide sufficient additional transport mechanisms to connect to less frequently used resources as needed for the processing system, such that over all paths into and out of the CPU or other controller any resource needed by the CPU or other controller can be accessed.

3. The transport mechanism protocol according to claim 1, containing within the protocol all necessary features to transport a payload from any data source inside the data processing system to any data destination within same said data processing system including: able to carry a payload and not utilize any field of said payload to assist in routing said payload from source to destination; and said transport mechanism containing fields within the transport protocol envelope placed around or in front of the payload which contain the address of each intermediate resourceâ s outgoing port the payload is being carried through, and after passing through said intermediate resource outgoing port, the address of the port is removed and the address of the next port is brought forward to the lead address field so that when the transport mechanism with its payload arrives at the next intermediate resource being used to switch the payload to its destination, or the destination IC itself, the payload will be delivered to the correct outgoing port of the next intermediate IC or the destination port within the destination IC.

4. The transport mechanism according to claim 1, utilizing a signal switching technology able to travel a greater distance over a Printed Circuit Board (PCB) than DDR signals can travel, for the purpose of: providing more physical space between ICs of a data processing system to make it easier to provide cooling mechanisms to each IC of said data processing system; provide more room for PCB-surface-area intensive resources such as main memory than what DDR can provide in the immediate vicinity of a CPU or other controller, to provide both higher overall bandwidth between all instances of said resource(s) and said CPU or controller, and more of said resource than what said resource being limited to the immediate vicinity of said CPU or controller could otherwise provide; and provide more room for other resources than would otherwise be available if PCB area intensive resources such as main memory consume most of the PCB area so close to the CPU or other controller that resource would otherwise by unavailable to the CPU or other controller.

5. The transport mechanism according to claim 4, capable of being easily carried over electrical cables or converted into an optical signal to be carried over optical fibers, for the purpose of allowing resources to be: located at such a distance from other resources such that the transport mechanism cannot be faithfully carried via PCB etch at full bandwidth; located on those parts of the PCB where routing electrical connections for the transport protocol on the PCB itself makes it too difficult to do so in such a way as to be able to fully utilize the transport mechanismâ s full bandwidth; located on different PCBs than other resources but still be part of the same data processing system; and easier to harden said resources from interfering or damaging electrical fields, magnetic fields, or electromagnetic fields.

6. The transport mechanism according to claim 1, with resources designed to allow the insertion or removal of additional resources located outside of the data processing system with much higher bandwidth than what most existing interfaces provide at the time of this invention disclosure: for the purpose of allowing users of said data processing system the ability to add or remove additional resources as deemed needed by the user; for the purpose of allowing users to attach said data processing system to, or detach from, an external network such as a Local Area Network (LAN) to connect said data processing system to other systems; and for other reasons of allowing users to attach or remove to said data processing system other data processing systems.

7. The transport mechanism according to claim 1, which carries a field inside the transport mechanism to identify the priority of the payload carried by the transport mechanism for the purpose of: identifying packets carrying command payloads; identifying packets carrying response payloads; identifying packets carrying various priorities of data for the purpose of moving higher priority data, command, or response packets before lower priority data when different priorities of payloads are residing in buffers waiting to pass through a Switching Engine (SWE) or passing to an outgoing port on an IC to another IC; and identifying lower priority packets that can be discarded when buffers begin to fill up.

8. The transport mechanism according to claim 7, which utilizes the priority field of said transport mechanism, to: prevent response packets, which are packets a resource sends back to a CPU or other controller acknowledging receipt of a command packet, status of a executing a command, or unsolicited responses such as alerting the CPU or other controller of conditions that need their immediate attention, from leaving a data processing system for the purpose of preventing an external controller from attempting to take control of any resource inside the data processing system by not allowing said external controller from receiving a response from any internal resource; and prevent command packets, which are packets a CPU or other controller sends to another resource requesting it to perform a function for said CPU or controller, from entering the data processing system for the purpose of preventing an external controller from attempting to take control of an internal resource or discovering the organization of said data processing system.

9. The transport mechanism according to claim 1, which utilizes higher level protocols being carried by the transport mechanism, to perform all functions of transmission reduction, that is, when any IC detects that its internal buffers are nearing capacity, otherwise known as suffering congestion, shall send out high priority packets to all other ICs connected to it that for a limited length of time will temporarily restrict transmission of packets to the IC suffering congestion for the purpose of allowing said IC to empty out its own internal buffers so they wonâ t overflow and lose packets, and said IC connected to an IC that is suffering congestion, when it receives a packet notifying it the IC is encountering congestion, for a brief period of times suspends transmissions of packets to said source of the congestion notification packet for the purpose of allowing the source of the congestion notification time to empty or partially empty out its buffers.

10. The transport mechanism according to claim 2, whose outgoing and destination ports will look at the lead address field of the encapsulation around a payload and accept said payload if the address matches what the port is configured to accept; said port not being restricted to accepting a single address only; and said port not being given the exclusive use of any address so that multiple outgoing ports may arbitrate to carry a payload to provide more bandwidth between two ICs by providing multiple ports and paths between them.

11. The transport mechanism according to claim 10, with a packet or packets whose lead address field is an outgoing port, and confronted with a multiplicity of outgoing ports all responding to the same address in the lead address field, to provide for a means of selecting which outgoing port will accept said packet or packets, based on the criteria of, a) the said outgoing port is in communications with the receiving port of the IC it is connected to such that it can faithfully carry payloads over the transport mechanism, b) the said outgoing portâ s buffer has fewer packets pending inside it than any other outgoing ports it is competing against to receive said payload, and c) if a tie exists among two or more outgoing ports, a round-robin or arbitrary priority scheme is used to select the port that will accept the packet(s) of the payload.

12. A transport mechanism whose payload contents can replace all other types of signal pins except reset on a CPU IC by using high speed packets destined for internal ports inside the CPU IC which provide the same function as traditional pins on a CPU IC, with the goal of reducing the pin count of said CPU IC, which reduces the manufacturing costs of said CPU IC, leaving only power pins, power return pins otherwise commonly referred to as ground, a reset signal, and the transport mechanism ports as the only pins needed on a CPU IC.

13. The transport mechanism according to claim 12 further including integrated circuits (ICs) for the suppling of controller configuration information and boot code as needed by a CPU IC to operate in a diverse environment, that the environment configuration over a high speed transport mechanism between the two ICs, and provide an enhanced Local Bus Controller function in a separate IC package to keep the pin count of the CPU low enough to use smaller packages, and said support ICs are not just limited to providing configuration information and boot code, but may optionally provide 10 signals commonly used in processing mechanisms, time-of-day clock and calendar functions, health monitoring functions for the processing system, and other features or functions as deemed needed for the processing system.

14. The transport mechanism according to claim 13 further including a separate enhanced Local Bus Controller IC that accesses boot code, configuration information, and low speed I/O functions, and supplies it to a CPU over a high speed transport mechanism to a CPU such that said CPU does not need to use pins to provide for the enhanced local bus and thus can keep its pin count down so it can be installed in a lower cost package.

15. The transport mechanism according to claim 12 that can suspend all signal switching on its outgoing ports for the purpose of signaling to the receiving ports that a reset is in progress, such that said receiving IC no longer needs a reset pin but will place itself in reset when the receiving ports of all transport mechanisms of said IC are no longer transitioning, the purpose be to reduce the pin count and hence the packaging costs of said IC.

16. A transport mechanism according to claim 15 wherein the pin assignments of an IC are completely symmetrical to the point where a rectangular shaped IC package can be inserted in either orientation and the IC will properly function, and where a square shaped IC package can be inserted in any of the four different directions and the IC will properly function, the purpose of which is to ease in the manufacturing of printed circuit boards with said IC in that the orientation of the IC will be irrelevant and thus if not installed in the correct orientation the IC will still function as intended with no loss of efficiency or throughput.

17. A computing module comprising: a semiconductor carrier having a four sided pin configuration; a central processing unit (CPU); serial port circuitry electrically coupled with the CPU; and a plurality of serial ports electrically coupled with the serial port circuitry, wherein: a first serial port of the plurality of serial ports is electrically coupled with a first plurality of pins positioned on a first side of the semiconductor carrier; a second serial port of the plurality of serial ports is electrically coupled with a second plurality of pins positioned on a second side of the semiconductor carrier; a third serial port of the plurality of serial ports is electrically coupled with a third plurality of pins positioned on a third side of the semiconductor carrier; a fourth serial port of the plurality of serial ports is electrically coupled with a fourth plurality of pins positioned on a fourth side of the semiconductor carrier; and the first, second, third, and fourth plurality of pins each have a commonly positioned transmit output port and transmit input port associated with the given serial port.

18. The computing module of claim 17, wherein the serial port circuitry includes a non-blocking switching engine for connectivity of payloads between the CPU and each serial port.

19. The computing module of claim 17, wherein the first, second, third, and fourth plurality of pins each have one or more commonly positioned power pin(s) and one or more commonly positioned ground pin(s).

20. The computing module of claim 19, wherein: each transmit output port includes a differential transmit output port; and each receive input port includes a differential receive input port.

21. The computing module of claim 17, wherein the semiconductor carrier is at least one of: a 44-pin plastic leaded chip carrier (PLCC); a 68-pin PLCC and the plurality of serial ports includes at least eight serial ports; a 100-pin PLCC and the plurality of serial ports includes at least twelve serial ports; a 144-pin Quad Flat Pack (QFP) and the plurality of serial ports includes at least sixteen serial ports; and a 208-pin QFP and the plurality of serial ports includes at least twenty serial ports.