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GB2610344A - Secure chip identification using resistive processing unit as a physically unclonable function - Google Patents

Secure chip identification using resistive processing unit as a physically unclonable function Download PDF

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Publication number
GB2610344A
GB2610344A GB2217559.0A GB202217559A GB2610344A GB 2610344 A GB2610344 A GB 2610344A GB 202217559 A GB202217559 A GB 202217559A GB 2610344 A GB2610344 A GB 2610344A
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Prior art keywords
values
midrange
rpus
condition
high values
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Granted
Application number
GB2217559.0A
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GB2610344B (en
GB202217559D0 (en
Inventor
Kumar Arvind
Ando Tasashi
Pfeiffer Dirk
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International Business Machines Corp
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International Business Machines Corp
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Publication of GB2610344A publication Critical patent/GB2610344A/en
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Publication of GB2610344B publication Critical patent/GB2610344B/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0059—Security or protection circuits or methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Storage Device Security (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Adjustable Resistors (AREA)
  • Saccharide Compounds (AREA)
  • Logic Circuits (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)

Abstract

A technique relates to biasing, using a control system (220), a crossbar array (100) of resistive processing units (102) under a midrange condition, the midrange condition causing resistances of the resistive processing units (102) to result in a random output of low values and high values in about equal proportions. The control system (220) reinforces the low values and the high values of the random output by setting the resistances of the resistive processing units (102) to a state that forces the low values and the high values having resulted from the midrange condition. Reinforcing the low values and the high values makes the random output permanent even when the crossbar array (100) of the resistive processing units (102) is not biased under the midrange condition. The control system (220) records a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.

Claims (20)

1. A computer-implemented method for identification, the computer-implemented method comprising: biasing, using a control system, a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions; reinforcing, using the control system, the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition, reinforcing the low values and the high values making the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition; and recording, using the control system, a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.
2. The computer-implemented method of claim 1, wherein in response to receiving predefined voltages under the midrange condition, the RPUs generate a stochastic response.
3. The computer-implemented method of claim 1, wherein in response to receiving predefined voltages under the midrange condition, the RPUs generate a stochastic response of the low values and the high values in the about equal proportions.
4. The computer-implemented method of claim 1, wherein reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to the state that forces the low values and the high values having resulted from the midrange condition comprises using voltage pulses under the midrange condition that drive the resistances of the RPUs.
5. The computer-implemented method of claim 1, wherein reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to the state that forces the low values and the high values having resulted from the midrange condition comprises using voltage pulses to shift resistance values up and down to ensure the low values and the high values in the about equal proportions.
6. The computer-implemented method of claim 1, wherein the crossbar array of the RPUs is configured to be authenticated by reading out a verification sequence that matches the random output, the verification sequence being read out under a different condition than the midrange condition.
7. The computer-implemented method of claim 1 further comprising preventing the resistances of the RPUs from being subsequently programmed, responsive to recording the sequence of the low values and the high values of the random output.
8. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising: biasing a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions; reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition, reinforcing the low values and the high values making the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition; and recording a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.
9. The computer program product of claim 8, wherein in response to receiving predefined voltages under the midrange condition, the RPUs generate a stochastic response.
10. The computer program product of claim 8, wherein in response to receiving predefined voltages under the midrange condition, the RPUs generate a stochastic response of the low values and the high values in the about equal proportions.
11. The computer program product of claim 8, wherein reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to the state that forces the low values and the high values having resulted from the midrange condition comprises using voltage pulses under the midrange condition that drive the resistances of the RPUs.
12. The computer program product of claim 8, wherein reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to the state that forces the low values and the high values having resulted from the midrange condition comprises using voltage pulses to shift resistance values up and down to ensure the low values and the high values in the about equal proportions.
13. The computer program product of claim 8, wherein the crossbar array of the RPUs is configured to be authenticated by reading out a verification sequence that matches the random output, the verification sequence being read out under a different condition than the midrange condition.
14. The computer program product of claim 8 further comprising preventing the resistances of the RPUs from being subsequently programmed, responsive to recording the sequence of the low values and the high values of the random output.
15. A system comprising: a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising: biasing a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions; reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition, reinforcing the low values and the high values making the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition; and recording a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.
16. The system of claim 15, wherein in response to receiving predefined voltages under the midrange condition, the RPUs generate a stochastic response.
17. The system of claim 15, wherein in response to receiving predefined voltages under the midrange condition, the RPUs generate a stochastic response of the low values and the high values in the about equal proportions.
18. The system of claim 15, wherein reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to the state that forces the low values and the high values having resulted from the midrange condition comprises using voltage pulses under the midrange condition that drive the resistances of the RPUs.
19. The system of claim 15, wherein reinforcing the low values and the high values of the random output by setting the resistances of the RPUs to the state that forces the low values and the high values having resulted from the midrange condition comprises using voltage pulses to shift resistance values up and down to ensure the low values and the high values in the about equal proportions.
20. The system of claim 15, wherein the crossbar array of the RPUs is configured to be authenticated by reading out a verification sequence that matches the random output, the verification sequence being read out under a different condition than the midrange condition.
GB2217559.0A 2020-04-30 2021-03-19 Secure chip identification using resistive processing unit as a physically unclonable function Active GB2610344B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/862,663 US11501023B2 (en) 2020-04-30 2020-04-30 Secure chip identification using resistive processing unit as a physically unclonable function
PCT/IB2021/052314 WO2021220071A1 (en) 2020-04-30 2021-03-19 Secure chip identification using resistive processing unit as a physically unclonable function

Publications (3)

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GB202217559D0 GB202217559D0 (en) 2023-01-11
GB2610344A true GB2610344A (en) 2023-03-01
GB2610344B GB2610344B (en) 2025-01-15

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US (1) US11501023B2 (en)
JP (1) JP7553201B2 (en)
CN (1) CN115191030B (en)
AU (1) AU2021264045B2 (en)
DE (1) DE112021000582T5 (en)
GB (1) GB2610344B (en)
IL (1) IL296249B2 (en)
WO (1) WO2021220071A1 (en)

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DE112021000582T5 (en) 2022-12-08
AU2021264045B2 (en) 2024-03-28
CN115191030A (en) 2022-10-14
JP7553201B2 (en) 2024-09-18
AU2021264045A1 (en) 2022-09-22
GB2610344B (en) 2025-01-15
JP2023523233A (en) 2023-06-02
IL296249B1 (en) 2025-04-01
WO2021220071A1 (en) 2021-11-04
US20210342489A1 (en) 2021-11-04
IL296249A (en) 2022-11-01
US11501023B2 (en) 2022-11-15
IL296249B2 (en) 2025-08-01
CN115191030B (en) 2023-05-23
GB202217559D0 (en) 2023-01-11

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