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GB2642768A - Storage usage - Google Patents

Storage usage

Info

Publication number
GB2642768A
GB2642768A GB2412284.8A GB202412284A GB2642768A GB 2642768 A GB2642768 A GB 2642768A GB 202412284 A GB202412284 A GB 202412284A GB 2642768 A GB2642768 A GB 2642768A
Authority
GB
United Kingdom
Prior art keywords
operations
execution
location data
physical storage
intermediate block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
GB2412284.8A
Inventor
Hugo Symes Dominic
Olson Jens
Maurice Simon Rosemarine Elliot
Rudolf Bratt Ian
Corey Smolens Jared
Priyanka Marigi Rajanarayana
Peter Stolt Fredrik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARM Ltd
Original Assignee
ARM Ltd
Advanced Risc Machines Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/778,179 external-priority patent/US20260023684A1/en
Priority claimed from US18/778,203 external-priority patent/US12547330B2/en
Application filed by ARM Ltd, Advanced Risc Machines Ltd filed Critical ARM Ltd
Priority to PCT/GB2025/051608 priority Critical patent/WO2026018025A1/en
Priority to PCT/GB2025/051607 priority patent/WO2026018024A1/en
Publication of GB2642768A publication Critical patent/GB2642768A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

A processor comprises storage, execution circuitry and a handling unit configured to obtain task data that describes a task to be executed, comprising a plurality of operations representable as a directed graph of operations (Figure 1a). The plurality of operations comprises production operations comprising generating blocks comprising an intermediate block generated by a production operation in determining a final block, and a consumption operation. The handling unit generates a set of location data indicative of respective physical storage locations allocated to store respective blocks, and for execution of at least part of a consumption operation traverses 252 the set of location data to obtain location data indicative of a physical storage location for storing the intermediate block, and generates 254 and sends 256 execution instructions to instruct the execution circuitry to execute at least part of the consumption operation to read the intermediate block from the physical storage location, the execution instructions comprising the location data.
GB2412284.8A 2024-07-19 2024-08-20 Storage usage Pending GB2642768A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/GB2025/051608 WO2026018025A1 (en) 2024-07-19 2025-07-18 Storage usage
PCT/GB2025/051607 WO2026018024A1 (en) 2024-07-19 2025-07-18 Storage usage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18/778,179 US20260023684A1 (en) 2024-07-19 2024-07-19 Storage usage
US18/778,203 US12547330B2 (en) 2024-07-19 Storage usage

Publications (1)

Publication Number Publication Date
GB2642768A true GB2642768A (en) 2026-01-21

Family

ID=98267844

Family Applications (2)

Application Number Title Priority Date Filing Date
GB2412284.8A Pending GB2642768A (en) 2024-07-19 2024-08-20 Storage usage
GB2412281.4A Pending GB2642765A (en) 2024-07-19 2024-08-20 Storage usage

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB2412281.4A Pending GB2642765A (en) 2024-07-19 2024-08-20 Storage usage

Country Status (1)

Country Link
GB (2) GB2642768A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150128151A1 (en) * 2012-05-31 2015-05-07 StreamNovation Kft. Method And System For Mapping An Integral Into A Thread Of A Parallel Architecture
US20210132945A1 (en) * 2019-11-04 2021-05-06 Apple Inc. Chained Buffers In Neural Network Processor
US20220244984A1 (en) * 2018-05-04 2022-08-04 Apple Inc. Compiling and scheduling transactions in neural network processor
US20240127392A1 (en) * 2022-10-17 2024-04-18 Intel Corporation Chained accelerator operations with storage for intermediate results
GB2626388A (en) * 2023-01-20 2024-07-24 Advanced Risc Mach Ltd Efficient data processing

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150128151A1 (en) * 2012-05-31 2015-05-07 StreamNovation Kft. Method And System For Mapping An Integral Into A Thread Of A Parallel Architecture
US20220244984A1 (en) * 2018-05-04 2022-08-04 Apple Inc. Compiling and scheduling transactions in neural network processor
US20210132945A1 (en) * 2019-11-04 2021-05-06 Apple Inc. Chained Buffers In Neural Network Processor
US20240127392A1 (en) * 2022-10-17 2024-04-18 Intel Corporation Chained accelerator operations with storage for intermediate results
GB2626388A (en) * 2023-01-20 2024-07-24 Advanced Risc Mach Ltd Efficient data processing

Also Published As

Publication number Publication date
GB2642765A (en) 2026-01-21

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