GB2642177A

GB2642177A - Electronic circuit

Info

Publication number: GB2642177A
Application number: GB2408581.3A
Authority: GB
Inventors: Knight Graham; Biggs John; Wood Neal
Original assignee: Pragmatic Semiconductor Ltd
Current assignee: Pragmatic Semiconductor Ltd
Priority date: 2024-06-14
Filing date: 2024-06-14
Publication date: 2026-01-07
Also published as: GB202408581D0; WO2025257556A1

Abstract

An electronic circuit, e.g. a D-type flip-flop 400, includes a latch 401 and an output stage 403. The latch 401 comprises a first inverter M8 and a second inverter M9. The output of the first inverter is coupled to the input of the second inverter, and the output of the second inverter is coupled to the input of the first inverter. The output stage comprises a first transistor M13 coupled between a first supply voltage VDD1 and a first output node Q, a second transistor M12 coupled between the first output node and ground, a third transistor M11 coupled between a second supply voltage and a second output node Q/, and a fourth transistor M10 coupled between the second output node Q/ and ground. The output S of the first inverter is coupled to the gate terminals of the first transistor and the fourth transistor of the output stage. The complementary output S/ of the second inverter is coupled to the gate terminals of the second transistor and the third transistor of the output stage. Each transistor in the output stage may be an NMOS transistor. The circuit avoids the use of pull-up resistors in the output stage.

Description

[0001] ELECTRONIC CIRCUIT

[0002] TECHNICAL FIELD

[0003] The present disclosure concerns an electronic circuit. More particularly, but not exclusively, the present disclosure concerns an electronic circuit comprising a latch and an output stage.

[0004] BACKGROUND

[0005] Electronic circuits typically incorporate output buffers on digital signals that are output from the electronic circuit. The output buffer prevents any further circuitry that utilises the signal loading the signal source (as this can in some circumstances affect the operation of the electronic circuit). The output buffer typically presents a high-impedance input to the signal source and generates an output that mimics one or more properties of the binary signal source. Output buffers can be non-inverting (in which case they generate an output that mirrors the signal source) or inverting On which case they generate an output that represents an inverted reproduction of the signal source). It will be appreciated that such buffers can sometimes also be used to introduce a gain factor or convert between voltage levels (for example, converting from 1.2V logic to 3.3V logic). The output buffers in an electronic circuit can also be referred to as an output stage.

[0006] In integrated circuits, an output buffer typically comprises a complementary metal oxide semiconductor (CMOS) push-pull transistor pair. Figure 1 shows a schematic view of such a prior art CMOS buffer circuit 100. Such an output buffer comprises a p-channel metal oxide semiconductor (PMOS) transistor (M1) coupled between a positive voltage supply (VDD) and an output node (OUT_C) of the buffer and an n-channel metal oxide semiconductor (NMOS) transistor (MO) coupled between the output node (OUT_C) and ground or a negative voltage supply (VSS). The gates of both the PMOS transistor (M1) and the NMOS transistor (MO) are coupled to an input node (IN_C) of the buffer (which in use will generally be driven by the signal source). When the signal source is a logic '1', the PMOS transistor (M1) is switched off and acts as an open circuit and the NMOS transistor (MO) is switched on and acts as a short circuit, pulling the output node (OUT_C_ to ground (VSS) -i.e. a logic '0'. When the signal source is a logic '0', the

[0007] --

[0008] NMOS transistor (MO) is switched off and acts as an open circuit and the PMOS transistor (M1) is switched on and acts as a short circuit, pulling the output node (OUT_C) to the positive voltage supply (VDD) -i.e. a logic '1'. Thus, the complementary operation of PMOS and NMOS transistors ensures that for any binary state of the buffer there is no leakage path between the positive voltage supply (VDD) and ground (VSS).

[0009] However, some integrated circuit fabrication technologies are NMOS-only and PMOS devices are not available for use. Thus, integrated circuit designs for such technologies must employ alternative NMOS-only circuit designs. Figure 2 shows a schematic view of such a prior art NMOS-only buffer circuit 200 (also referred to as an NMOS inverter). The NMOS-only buffer circuit 200 comprises a pull-up resistor (RO) coupled between a positive voltage supply (VDD) and an output node (OUT_N) of the buffer and an NMOS transistor (M2) coupled between the output node (OUT_C) and ground or a negative voltage supply (VSS). The gate of the NMOS transistor (M2) is coupled to an input node (IN_N) of the buffer (and thereby the signal source). When the signal source is a logic '1', the NMOS transistor (M2) is switched on and acts as a short circuit, pulling the output node (OUT_N) to ground (VSS) -i.e. a logic '0'. When the signal source is a logic '0', the NMOS transistor (M2) is switched off and acts as an open circuit. The pull-up resistor (RO) then pulls the output node (OUT_C) to the positive voltage supply (VDD) -i.e. a logic '1'. However, the use of a pull-up resistor (in the place of a PMOS transistor) means that there is significant leakage current between the positive voltage supply (VDD) and ground (VSS) when the NMOS transistor (M2) is switched on. Thus, the NMOS-only buffer 200 has higher power consumption than the CMOS buffer 100 described above. Furthermore, a resistor generally occupies a larger area of an integrated circuit than a PMOS transistor, meaning that an NMOS-only buffer is generally physically larger than a corresponding CMOS buffer.

[0010] Figure 3 shows an NMOS-only D-type flip flop 300 of the prior art. The flip flop 300 comprises a first latch 301, a second latch 305, clock buffering 307, and an output stage 303. The first latch 301 comprises a first NMOS inverter (R4, M8) and a second NMOS inverter (R5, M9). An output (S) of the first NMOS inverter (R4, M8) is coupled to an input of the second NMOS inverter (R5, M9). An output (S) of the second NMOS inverter (R5, M9) is coupled to an input of the first NMOS inverter (R4, M8). The second -2 -latch 305 comprises a third NMOS inverter (R2, M4) and a fourth NMOS inverter (R3, M5). An output of the third NMOS inverter (R2, M4) is coupled to an input of the fourth NMOS inverter (R3, M5). An output of the fourth NMOS inverter (R3, M5) is coupled to an input of the third NMOS inverter (R2, M4). The output stage 303 comprises a fifth NMOS inverter (R6, M10) and a sixth NMOS inverter (R7, M11). The output (S) of the first NMOS inverter (R4, M8) is coupled to the input of the fifth NMOS inverter (R6, M10). An output (Q) of the fifth NMOS inverter (R6, M10) is coupled to an input of the sixth NMOS inverter (R7, M11). The output (Q) of the sixth NMOS inverter (R7, M11) comprises a data output (Q) of the flip flop 300. The output (Q) of the fifth NMOS inverter (R6, M10) comprises an inverted data output (Q) of the flip flop 300. The clock buffer circuit 307 comprises two series connected NMOS inverters (R0, MO and R1, M1) and is configured to buffer an input clock signal (CLK) and to generate an inverted instance of that clock signal. The first latch 301 comprises a first NMOS transistor (M7) coupled between the output (S) of the second inverter (R5, M9) and the input of the first inverter (R4, M8). The second latch 305 comprises a second NMOS transistor (M3) coupled between the output of the fourth inverter (R3, M5) and the input of the third inverter (R2, M4). A data input (D) of the flip flop 300 is coupled to the input of the third inverter (R2, M4) via a third NMOS transistor (M2). The output of the third inverter (R2, M4) is coupled to the input of first inverter (R4, M8) via a fourth NMOS transistor (M6). The first NMOS transistor (M7) and the third NMOS transistor (M2) are driven by the inverted instance of the clock signal. The second NMOS transistor (M3) and the fourth NMOS transistor (M6) are driven by the clock signal. Together the first, second, third, and fourth NMOS transistors (M7, M3, M2, M6) control flow of a state of the data input (D) through the flip flop 300.

[0011] The present disclosure seeks to mitigate the above-mentioned problems.

[0012] Alternatively or additionally, the present disclosure seeks to provide an improved output stage for an electronic circuit.

[0013] SUMMARY

[0014] A first aspect of the present disclosure relates to a circuit comprising: -3 -a latch comprising a first inverter and a second inverter, wherein an output of the first inverter is coupled to an input of the second inverter and an output of the second inverter is coupled to an input of the first inverter; and an output stage comprising: a first transistor coupled between a first supply voltage and a first output node, a second transistor coupled between the first output node and ground, a third transistor coupled between a second supply voltage and a second output node, and a fourth transistor coupled between the second output node and ground; wherein: the output of the first inverter is coupled to the gate terminals of the first transistor and the fourth transistor; and the output of the second inverter is coupled to the gate terminals of the second transistor and the third transistor.

[0015] A second aspect of the present disclosure relates to a circuit comprising: a latch comprising a first inverter and a second inverter, wherein an output of the first inverter is coupled to an input of the second inverter and an output of the second inverter is coupled to an input of the first inverter; and an output stage comprising: a first transistor coupled between a first supply voltage and a first output node, a second transistor coupled between the first output node and ground, a third transistor coupled between the second supply voltage and a second output node, and a fourth transistor coupled between the second output node and ground; wherein: the output of the first inverter is coupled to the input terminals of the second transistor and the third transistor; and the output of the second inverter is coupled to the input terminals of the first transistor and the fourth transistor.

[0016] It will of course be appreciated that features described in relation to one aspect of the present disclosure may be incorporated into other aspects of the present -4 -disclosure. For example, the method of the present disclosure may incorporate any of the features described with reference to the apparatus of the present disclosure and vice versa.

[0017] BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 shows a schematic view of a CMOS buffer of the prior art; [0011] Figure 2 shows a schematic view of an NMOS-only buffer of the prior art; [0012] Figure 3 shows a schematic view of an NMOS-only D-type flip flop of the

[0019] prior art;

[0020] Figure 4 shows a schematic view of an electronic circuit according to the

[0021] present disclosure;

[0022] Figure 5 shows a graph comparing the achievable operating frequencies and occupied circuit areas of the NMOS-only D-type flip flop of Figure 3 and a D-type flip flop according to the present disclosure; and [0015] Figure 6 shows a graph comparing the achievable operating frequencies and power consumptions of the NMOS-only D-type flip flop of Figure 3 and a D-type flip flop according to the present disclosure.

[0023] DETAILED DESCRIPTION

[0024] Figure 4 shows a schematic view of an electronic circuit 400 according to

[0025] the present disclosure.

[0026] Electronic circuit 400 comprises a latch 401. Latch 401 comprises a first inverter (R4, M8) and a second inverter (R5, M9). An output (S) of the first inverter (R4, M8) is coupled to an input of the second inverter (R5, M9) and an output (S) of the second inverter (R5, M9) is coupled to an input of the first inverter (R4, M8).

[0027] Electronic circuit 400 further comprises an output stage 403. Output stage 403 comprises a first transistor (M13) coupled between a first supply voltage (VDD1) and a first output node (Q). Output stage 403 further comprises a second transistor (M12) coupled between the first output node (Q) and ground (VSS). Output stage 403 further comprises a third transistor M-11 coupled between a second supply voltage (VDD2) and a second output node (Q). Output stage 403 further comprises a fourth transistor (M10) -5 -coupled between the second output node (Q) and ground (VSS). The output (S) of the first inverter (R4, M8) is coupled to the gate terminals of the first transistor (M13) and the fourth transistor (M10). The output (S) of the second inverter (R5, M9) is coupled to the gate terminals of the second transistor (M12) and the third transistor (M11).

[0028] Use of an output stage comprising two NMOS transistors in a push-pull configuration can provide an output stage having the low power consumption of a traditional CMOS output stage without the need for a PMOS transistor. Thus, such an output stage can achieve analogous power consumption performance to that of a traditional CMOS output stage in the absence of a PMOS transistor such as, for example, in integrated circuits where only NMOS transistor technology is available. The present inventors have also recognised that many circuits (including, for example, latches and flip flops) retain an internal state in both an inverted and non-inverted form. For example, a latch typically comprises a pair of inverters connected such that the output of each inverter in the pair is used to drive the input of the other inverter in the pair. Thus, a first inverter in the pair outputs the stored internal state, and the other inverter in the pair outputs an inverted instance of the stored internal state. The present inventors have further recognised that those internal signals can be used as a differential output signal to efficiently control such an NMOS-only output stage. In particular, use of the inverted instance of the stored internal state can remove the need for an additional inverter to drive the second and third transistors. This can provide a reduction in the physical area required by the circuit and a reduction in power consumption.

[0029] The first supply voltage (VDD1) and the second supply voltage (VDD2) may be the same supply voltage. It may be that the electronic circuit operates using a single supply voltage (i.e. VDD = VDD1 = VDD2). The first supply voltage (VDD1) and the second supply voltage (VDD2) may each comprise a positive supply voltage. It will be appreciated that a "positive supply voltage" in this context refers to a voltage supply that is at a positive voltage compared to ground (VSS). It will also be appreciated that references to "ground" are intended to refer merely to a reference voltage in the electronic circuit 300 and are not limited to a connection to the Earth.

[0030] A drain terminal of the first transistor (M13) may be connected to the first supply voltage (VDD1). A source terminal of the first transistor (M13) may be connected -6 -to the first output node (Q). A drain terminal of the second transistor (M12) may be connected to the first output node (Q). A source terminal of the second transistor (M12) may be connected to ground (VSS).

[0031] A drain terminal of the third transistor (M11) may be connected to the second supply voltage (VDD2). A source terminal of the third transistor (M11) may be connected to the second output node (Q). A drain terminal of the fourth transistor (M1) may be connected to the second output node (Q). A source terminal of the fourth transistor (M10) may be connected to ground (VSS).

[0032] The first transistor (M13) and the second transistor (M12) may be the same type of transistor (for example, an NMOS transistor). The third transistor (M11) and the fourth transistor (M10) may be the same type of transistor (for example, an NMOS transistor). The first, second, third, and fourth transistors (M13, M12, M11, M10) may be the same type of transistor. The first, second, third, and fourth transistors (M13, M12, M11, M10) may each comprise an NMOS transistor. For example, the first, second, third, and fourth transistors (M13, M12, M11, M10) each comprise a Metal Oxide Semiconductor (MOS) transistor. For example, the first, second, third, and fourth transistors (M13, M12, M11, M10) each comprise a bipolar junction transistor (BUT) (for example, an NPN BUT). It will be appreciated that other types of transistor may alternatively be used. It will be appreciated that, where the first, second, third, and fourth transistors (M13, M12, M11, M10) comprise bipolar junction transistors, references throughout the specification to a "gate terminal" instead relate to a "base terminal", references to a "source terminal" instead relate to an "emitter terminal", and references to a "drain terminal" instead relate to a "collector terminal".

[0033] The electronic circuit 400 may be a latch. The electronic circuit 400 may comprise a flip flop (for example, a D-type data flip flop). It may be that the electronic circuit 400 is a flip flop (for example, a D-type flip flop). Thus, the electronic circuit 400 may comprise a further latch 405. An output of the further latch 405 may be coupled to an input of the latch 401.

[0034] The further latch 405 may comprise a third inverter (R2, M4) and a fourth inverter (R3, M5). An output of the third inverter (R2, M4) is coupled to an input of the fourth inverter (R3, M5) and an output of the fourth inverter (R3, M5) is coupled to an -7 -input of the third inverter (R2, M4). The output of the third inverter (R2, M4) may be coupled to the input of the first inverter (R4, M8).

[0035] The output of the second inverter (R5, M9) may be coupled to the input of the first inverter (R4, M8) via a fifth transistor (M7). A drain terminal of the fifth transistor (M7) may be coupled to the output of the second inverter (R5, M9) and a source terminal of the fifth transistor (M7) may be coupled to the input of the first inverter (R4, M8). The output of the fourth inverter (R3, M5) may be coupled to the input of the third inverter (R2, M4) via a sixth transistor (M3). A drain terminal of the sixth transistor (M3) may be coupled to the output of the fourth inverter (R3, M5) and a source terminal of the sixth transistor (M3) may be coupled to the input of the third inverter (R2, M4).

[0036] A data input (D) of the circuit 400 may be coupled to the input of the third inverter (R2, M4) via a seventh transistor (M2). A drain terminal of the seventh transistor (M2) may be coupled to the data input (D) and a source terminal of the seventh transistor (M2) may be coupled to the input of the third inverter (R2, M4).

[0037] The output of the third inverter (R2, M4) may be coupled to the input of the first inverter (R4, M8) via an eighth transistor (M6). A drain terminal of the eighth transistor (M6) may be coupled to the output of the third inverter (R2, M4) and a source terminal of the eighth transistor (M6) may be coupled to the input of the first inverter (R4, M8).

[0038] The electronic circuit 400 may further comprise clock buffer circuit 407.

[0039] Clock buffer circuit 407 is configured to buffer an input clock signal (CLK) and to generate an inverted instance of that clock signal. The clock buffer circuit 407 may comprise a fifth inverter (RO, MO) and a sixth inverter (R1, M1). An input of the fifth inverter (RO, MO) may be coupled to the input clock signal (CLK). An output of the fifth inverter (RO, MO) may be coupled to an input of the sixth inverter (R1, M1). The output of the fifth inverter (R0, MO) may comprise the inverted instance of the clock signal. The output of the sixth inverter (R1, M1) may comprise a buffered instance of the clock signal. The fifth inverter (P0, MO) and the sixth inverter (R1, M1) may each comprise an NMOS inverter (for example, as illustrated in Figure 2).

[0040] A gate terminal of the fifth transistor (M7) may be driven on the basis of the inverted instance of the clock signal. A gate terminal of the sixth transistor (M3) may be driven on the basis of the clock signal. A gate terminal of the seventh transistor (M2) may -8 -be driven on the basis of the inverted instance of the clock signal. A gate terminal of the eighth transistor (M6) may be driven on the basis of the clock signal. The flow of a data input (D) signal through the circuit 400 may be controlled by at least the fifth and the eighth transistors (M7, M6). For example, the flow of a data input (D) signal through the circuit 400 may be controlled by the fifth, sixth, seventh, and eighth transistors (M7, M3, M2, M6).

[0041] The gate terminals of the second transistor (M12) and the third transistor (M11) may be connected directly to the output of the second inverter (R5, M9). It will be appreciated that "directly connected" in this context indicates that there are no active components in the signal path between the output of the second inverter (R5, M9) and the respective one of the second transistor (M12) and the third transistor (M11). There may, in such cases, be one or more passive components (for example, capacitors or resistors) on that signal path. Connecting the gate terminals of the second transistor (M12) and the third transistor (M11) directly to the output of the second inverter (R5, M9) reduces the time delay between a change in states of the first output node (Q) and the corresponding change in state of the second output node (0). Alternatively, the gate terminals of the second transistor (M12) and the third transistor (M11) may be connected directly to the input of the first inverter (R4, M8). Thus, the gate terminals of the second transistor (M12) and the third transistor (Mu) 1) may be connected to either the source or drain terminals of the fifth transistor (M7).

[0042] The first inverter (R4, M8) and the second inverter (R5, M9) each comprise an NMOS inverter (for example, as illustrated in Figure 2). The third inverter (R2, M4) and the fourth inverter (R3, M5) each comprise an NMOS inverter (for example, as illustrated in Figure 2). Thus, it may be that each of the first, second, third, and fourth inverters comprise a pull-up resistor (R4, R5, R2, R3) coupled between a voltage supply (VDD) and an output node of the inverter and an NMOS transistor (M8, M9, M4, M5) coupled between the output node and ground (VSS).

[0043] It may be that the electronic circuit 400 does not comprise a PMOS transistor. All transistors in the electronic circuit 400 may be NMOS transistors. Where the electronic circuit comprises a flip flop (for example, a D-type flip flop), it may be that -9 -the flip flop does not comprise a PMOS transistor. All transistors in the flip flop may be N MOS transistors.

[0044] The electronic circuit 400 may form part of an integrated circuit. Thus, examples of the present disclosure provide an integrated circuit comprising an electronic circuit 400 as described above.

[0045] The integrated circuit may be a flexible integrated circuit. In accordance with the present disclosure a "flexible integrated circuit" (flexible IC or flexIC) is a type of integrated circuit that is designed to be flexible and conformable, allowing it to bend, twist, and conform to non-flat or irregular surfaces. Unlike traditional rigid ICs, which are typically made on silicon wafers and are inflexible, flexible ICs, in accordance with the present disclosure, are fabricated on flexible substrates using appropriate materials and thin-film processes. The substrate is typically formed of an appropriate flexible polymer material. Nevertheless, the flexible substrate may be formed from any other materials that provide suitable electrical, chemical, and/or structural properties. The flexible substrate may be formed from a single common material, may be formed from a plurality of different materials, or may be formed from a plurality of different types of the same material. The flexible substrate may, for example, comprise one or more materials selected from the following list of materials: flexible glass, polymer materials, metal oxide materials, resin materials, resist materials, foil materials, paper, insulator coated metals, or any other suitable material.

[0046] Where a polymer based material is used, the substrate may comprise one or more polymers selected from: polyethylene naphthalates, polyethylene terephthalates; polymethyl methacrylates; polycarbonates, polyvinyl alcohols, polyvinyl acetates, polyvinyl pyrrolidones, polyvinyl phenols, polyvinyl chlorides, polystyrenes, polyimides, polyamides (e.g. Nylon); poly(hydroxy ethers), polyurethanes, polycarbonates, polysulfones, parylenes, polyarylates, polyether ether ketones (PEEKs); acrylonitrile butadiene styrene (ABS), 1 Methoxy 2 propyl acetates, Benzocyclobutenes (BCB), polylactic acid (PLA), polyhydroxyalkanoates (PHAs), polybutylene succinate (PBS), polybutylene adipate terephthalate (PBAT), cellulose polymers, or any other suitable polymer material.

[0047] -10 - [0037] Where a metal oxide based material is used, the substrate may comprise one or more metal oxides selected from: A1203, SiOxNy, Si02, Si3N4, or any other suitable metal oxide. Where a resin based material is used, the substrate may comprise one or more resins selected from: a UV-curable resin or any other suitable resin. Where a resist based material is used, the substrate may comprise one or more resists selected from: nanoimprint resists, photoresists such as, for example, Bisphenol A novolac epoxy (SU8) or polyhydroxybenzyl silsesquioxane, or any other suitable resist. Where a foil based material is used the substrate may comprise one or more foils selected from: polymeric foils or any other suitable foil. Where an insulator-coated metal is used, the substrate may comprise one or more insulator-coated metals selected from: insulator coated stainless-steel or any other suitable insulator-coated metal.

[0048] Additionally or alternatively, a flexible IC may not include the flexible substrate, which, for example, may be removed during a manufacturing step.

[0049] Figure 5 shows a graph comparing the achievable operating frequencies and occupied circuit areas of the NMOS-only D-type flip flop of Figure 3 and a D-type flip flop according to the present disclosure. It can be seen that for the given operating frequencies, the D-type flip flop according to the present disclosure (PCMOSDFF) generally occupies a smaller area of the integrated circuit than the NMOS-only D-type flip flop of Figure 3 (DFF). It will be appreciated that the data points above approximately 320kHz are at the limits of what can be achieved by the synthesis engine and that operating the synthesis engine at or near those limits can yield unusual results. The D-type flip flop according to the present disclosure includes one less inverter in the signal path between the flip flop data input (D) and the flip flop data outputs (Q, (1) than the NMOS-only D-type flip flop (DFF) of Figure 3. Furthermore, the use of an active pull-up (in the form on an NMOS transistor) rather than a resistive pull-up (in the form of a pull-up resistor) provides a faster rising edge on the flip flop data outputs (Q, Q). These two factors can enable a D-type flip flop according to the present disclosure to operate at a higher clock frequency. Furthermore, the D-type flip flop according to the present disclosure utilises fewer NMOS inverters and therefore includes fewer resistors, allowing a reduction in physical space required by the circuit.

[0050] Figure 6 shows a graph comparing the achievable operating frequencies and power consumptions of the NMOS-only D-type flip flop of Figure 3 and a D-type flip flop according to the present disclosure. It can be seen that, for the given operating frequencies, the D-type flip flop according to the present disclosure (PCMOSDFF) has reduced static power consumption compared to the NMOS-only D-type flip flop of Figure 3 (DFF). The D-type flip flop according to the present disclosure utilises fewer NMOS inverters and therefore has lower static power consumption than the D-type flip flop of Figure 3.

[0051] Whilst the present disclosure has been described and illustrated with reference to particular embodiments, it will be appreciated by those of ordinary skill in the art that the present disclosure lends itself to many different variations not specifically illustrated herein. By way of example only, certain possible variations will now be described.

[0052] Whilst the invention has been described by described by reference to electronic circuits including a latch and/or a D-type flip flop, it will be appreciated that the invention is also applicable to other types of electronic circuit. For example, it may be that the electronic circuit is a T-type 'toggle' flip flop, an SR-type 'set-reset' flip flop, a JK-type 'Jack Kilby' flip flop, a master-slave flip flop, an edge-triggered flip flop, or a level triggered flip flop.

[0053] It will be appreciated that references to "ground" are intended to refer merely to a reference voltage in the electronic circuit and are not limited to a connection to the Earth. The illustrated schematics label ground as "VSS". However, this notation is not intended to indicate that the circuit has positive and negative voltage supplies. Some embodiments of the present disclosure do have both positive and negative voltage supplies. Other embodiments have only a positive voltage supply. Similarly, it will be appreciated that, as ground merely refers to a reference voltage within the electronic circuit, alternative labelling for the electronic circuit of the present invention could designate VDD as ground, in which case VSS could instead be considered a negative supply voltage.

[0054] Similarly, whilst the illustrated embodiments utilise NMOS transistors, it will be appreciated that other types of transistor could alternatively be used. For example, in -12-other embodiments, the transistors in the electronic circuit comprise NPN BJTs. In such cases, it will be appreciated that references throughout the specification to a "gate terminal" would instead relate to a "base terminal", references to a "source terminal" would instead relate to an "emitter terminal", and references to a "drain terminal" instead relate to a "collector terminal".

[0055] Where in the foregoing description, integers or elements are mentioned which have known, obvious or foreseeable equivalents, then such equivalents are herein incorporated as if individually set forth. Reference should be made to the claims for determining the true scope of the present disclosure, which should be construed so as to encompass any such equivalents. It will also be appreciated by the reader that integers or features of the present disclosure that are described as preferable, advantageous, convenient or the like are optional and do not limit the scope of the independent claims. Moreover, it is to be understood that such optional integers or features, whilst of possible benefit in some embodiments of the present disclosure, may not be desirable, and may therefore be absent, in other embodiments. -13-

Claims

1. Claims 1. An electronic circuit comprising: a latch comprising a first inverter and a second inverter, wherein an output of the first inverter is coupled to an input of the second inverter and an output of the second inverter is coupled to an input of the first inverter; and an output stage comprising: a first transistor coupled between a first supply voltage and a first output node, a second transistor coupled between the first output node and ground, a third transistor coupled between a second supply voltage and a second output node, and a fourth transistor coupled between the second output node and ground; wherein: the output of the first inverter is coupled to the gate terminals of the first transistor and the fourth transistor; and the output of the second inverter is coupled to the gate terminals of the second transistor and the third transistor.

2. An electronic circuit according to claim 1, wherein the first, second, third, and fourth transistors each comprise an NMOS transistor.

3. An electronic circuit according to claim 1 or 2, wherein the first supply voltage and the second supply voltage each comprise a positive supply voltage. -14-

4. An electronic circuit according to any preceding claim, wherein the circuit is a D-type flip flop.

5. An electronic circuit according to claim 4, wherein: the D-type flip flop comprises a further latch; and an output of the further latch is coupled to an input of the latch.

6. An electronic circuit according to claim 5, wherein: the further latch comprises a third inverter and a fourth inverter; an output of the third inverter is coupled to an input of the fourth inverter and an output of the fourth inverter is coupled to an input of the third inverter; and the output of the third inverter is coupled to the input of the first inverter.

7. An electronic circuit according to claim 6, wherein: the output of the second inverter is coupled to the input of the first inverter via a fifth transistor; the output of the fourth inverter is coupled to the input of the third inverter via a sixth transistor; a gate terminal of the fifth transistor is driven on the basis of a clock signal, and a gate terminal of the sixth transistor is driven on the basis of an inverted instance of the clock signal.

8. An electronic circuit according to claim 7, wherein the gate terminals of the second transistor and the third transistor are connected directly to the output of the second inverter. -15-

9. An electronic circuit according to any of claims 1 to 7, wherein the gate terminals of the second transistor and the third transistor are connected directly to the input of the first inverter.

10. An electronic circuit according to any preceding claim, wherein: the drain terminal of the first transistor is connected to the first supply voltage; the source terminal of the first transistor is connected to the first output node; the drain terminal of the second transistor is connected to the first output node; and the source terminal of the second transistor is connected to ground.

11. An electronic circuit according to any preceding claim, wherein: the drain terminal of the third transistor is connected to the second supply voltage; the source terminal of the third transistor is connected to the second output node; the drain terminal of the fourth transistor is connected to the second output node; and the source terminal of the fourth transistor is connected to ground.

12. An electronic circuit according to any preceding claim, wherein the first inverter and the second inverter each comprise an NMOS inverter.

13. An electronic circuit according to any preceding claim, wherein the flip flop does not comprise a PMOS transistor.

14. An electronic circuit according to any preceding claim, wherein all transistors in the flip flop are NMOS transistors. -16-

15. An electronic circuit according to any preceding claim, wherein the first supply voltage and the second supply voltage are the same supply voltage.

16. An integrated circuit comprising an electronic circuit according to any preceding claim.

17. An integrated circuit according to claim 16, wherein the integrated circuit is a flexible integrated circuit.

18. An electronic circuit comprising: a latch comprising a first inverter and a second inverter, wherein an output of the first inverter is coupled to an input of the second inverter and an output of the second inverter is coupled to an input of the first inverter; and an output stage comprising: a first transistor coupled between a first supply voltage and a first output node, a second transistor coupled between the first output node and ground, a third transistor coupled between the second supply voltage and a second output node, and a fourth transistor coupled between the second output node and ground; wherein: the output of the first inverter is coupled to the input terminals of the first transistor and the fourth transistor; and the output of the second inverter is coupled to the input terminals of the second transistor and the third transistor. -17-