GB2641915A

GB2641915A - Semiconductor structures

Info

Publication number: GB2641915A
Application number: GB2408720.7A
Authority: GB
Inventors: Engel Zachary; Laboutin Oleg; Kastein Lewis
Original assignee: IQE PLC
Current assignee: IQE PLC
Priority date: 2024-06-18
Filing date: 2024-06-18
Publication date: 2025-12-24
Also published as: WO2025261641A1; GB202408720D0

Abstract

Semiconductor structure 300 (e.g., a HEMT, superlattice, Micro-LED) comprising substrate 110, a plurality of III-V layers 120, 330 over the substrate, and first III-V layer 340 over the plurality of III-V layers. The first III-V layer comprises a first sub-layer (e.g., an AlN or GaP nucleation layer) and a second sub-layer (e.g., an AlN or GaP extension layer) both comprising a first set of elements. The plurality of III-V layers comprises second III-V layer 330 (e.g., GaN) and the first III-V layer comprises AlN. A transition region is between the plurality of III-V layers and first III-V layer. The transition region comprises Al with a concentration between 0-50% of the group III elements. The first III-V layer (e.g., AlN) comprises Al with a concentration of greater than 50% of the group III elements. The first sub-layer and second sub-layer are grown at different rates.

Description

[0001] SEMICONDUCTOR STRUCTURES

[0002] Technical field

[0003] The present application relates to a semiconductor structure. The present application also relates to a method of forming a semiconductor structure.

[0004] Backci round Forming semiconductor devices from III-V semiconductor materials is becoming increasingly desirable. Si has dominated the semiconductor industry for many decades. However, III-V semiconductor materials possess desirable electronic and photonic properties, outperforming Si in many aspects.

[0005] Forming III-V semiconductor materials typically involves epitaxially growing layers of III-V semiconductor material on a substrate to form a layered structure. The layered structure may be grown using a number of methods, such as chemical vapour deposition (CVD), metal organic CVD (MOCVD), metalorganic vapour-phase epitaxy (MOVPE) and molecular beam epitaxy (MBE). Typically, multiple layers are grown layer-by-layer on a substrate. The substrate, and the layers, typically comprise semiconductor material.

[0006] However, other materials may also be incorporated into the layered structure.

[0007] The layers are grown on the substrate to form a layered structure, which may be referred to as a wafer. The wafer may subsequently be fabricated into an electronic or optoelectronic semiconductor device, such as a transistor, a diode, a light emitting diode (LED), a vertical cavity surface emitting laser (VCSEL), an edge emitting laser and a photodetector.

[0008] The epitaxial growth process for growing the III-V semiconductor layers dictate the quality of the layers and thus the fabricated semiconductor device. Furthermore, the quality of the III-V semiconductor layers can open-up an opportunity for advantageous semiconductor device fabrication techniques.

[0009] Summary

[0010] It is an object of the disclosure to obviate or eliminate at least some of the above-described disadvantages associated with existing techniques.

[0011] According to a first aspect there is provided a semiconductor structure comprising: a substrate; a plurality of III-V layers over the substrate; and a first III-V layer over the plurality of III-V layers. The first III-V layer comprises: a first sub-layer comprising a first set of elements; and a second sub-layer over the first sub-layer comprising the first set of elements.

[0012] According to a second aspect there is provided a method comprising: forming a plurality of III-V layers over a substrate; forming a first III-V layer over the plurality of III-V layers. Forming the first III-V layer comprises: forming a first sub-layer comprising a first set of elements; and forming a second sub-layer over the first sub-layer comprising the first set of elements.

[0013] Brief description of the drawings

[0014] For a better understanding of the techniques, and to show how it may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 is an example of a semiconductor structure; Figure 2 is another example of a semiconductor structure; Figure 3 is another example of a semiconductor structure; Figures 4a and 4b are examples of scanning transmission electron microscopy (STEM) images; Figures 5a and 5b are examples of energy dispersive X-ray spectroscopy (EDX) and STEM images; Figure 6 is another example of a semiconductor structure; Figure 7 is another example of a semiconductor structure; Figure 8 is another example of a semiconductor structure; Figures 9a-b are examples of a haze measurements; Figure 10 is an example of an atomic force microscopy (AFM) measurement.

[0015] Detailed Description

[0016] Epitaxy or epitaxial means crystalline growth of material, usually via high temperature deposition. Epitaxy can be effected in a molecular beam epitaxy (MBE) tool in which layers are grown on a heated substrate in an ultra-high vacuum environment. Elemental sources are heated in a furnace and directed towards the substrate without carrier gases. The elemental constituents react at the substrate surface to create a deposited layer. Each layer is allowed to reach its lowest energy state before the next layer is grown so that bonds are formed between the layers. Epitaxy can also be performed in a metal-organic vapour phase epitaxy (MOVPE) tool, also known as a metal-organic chemical vapour deposition (MOCVD) tool. Compound metal-organic and hydride sources are flowed over a heated surface using a carrier gas, typically hydrogen. Epitaxial deposition occurs at much higher pressure than in an MBE tool. The compound constituents are cracked in the gas phase and then reacted at the surface to grow layers of desired composition.

[0017] Deposition means the depositing of a layer on another layer or substrate. It encompasses epitaxy, chemical vapour deposition (CVD), powder bed deposition and other known techniques to deposit material in a layer.

[0018] A compound material comprising one or more materials from group III of the periodic table with one or more materials from group V is known as a III-V material. The compounds have a 1:1 combination of group III and group V regardless of the number of elements from each group. Subscripts in chemical symbols of compounds refer to the proportion of that element within that group. Thus A10.25Ga0.75As means the group III part comprises 25% Al, and thus 75% Ga, whilst the group V part comprises 100% As.

[0019] Crystalline means a material or layer with a single crystal orientation. In epitaxial growth or deposition subsequent layers with the same or similar lattice constant follow the registry of the previous crystalline layer and therefore grow with the same crystal orientation. In-plane is used herein to mean parallel to the surface of the substrate; outof-plane is used to mean perpendicular to the surface of the substrate.

[0020] Substrate means a planar wafer on which subsequent layers may be deposited or grown.

[0021] A substrate may be formed of a single element or a compound material, and may be doped or undoped. For example, common substrates include silicon (Si), gallium arsenide (GaAs), silicon germanium (SiGe), silicon germanium tin (SiGeSn), indium phosphide (InP), and gallium antimonide (GaSb).

[0022] A substrate may be on-axis, that is where the growth surface aligns with a crystal plane.

[0023] For example it has <100> crystal orientation. References herein to a substrate in a given orientation also encompass a substrate which is miscut by up to 20° towards another crystallographic direction, for example a (100) substrate miscut towards the (111) plane. Vertical or out of plane means in the growth direction; lateral or in-plane means parallel to the substrate surface and perpendicular to the growth direction.

[0024] Doping means that a layer or material contains a small impurity concentration of another element (dopant) which donates (donor) or extracts (acceptor) charge carriers from the parent material and therefore alters the conductivity. Charge carriers may be electrons or holes. A doped material with extra electrons is called n-type whilst a doped material with extra holes (fewer electrons) is called p-type.

[0025] A layer may be monolithic, that is comprising bulk material throughout. Alternatively it may be porous for some or all of its thickness. A porous layer includes air or vacuum pores, with the porosity defined as the proportion of the area which is occupied by the pores rather than the bulk material. The porosity can vary through the thickness of the layer. For example, the layer may be porous in one or more sublayer. The layer may include an upper portion which is porous with a lower portion that is non-porous. Alternatively the layer may include one or more discrete, non-continuous portions (domains) that are porous with the remainder being non-porous (with bulk material properties). The portions may be non-continuous within the plane of a sublayer and/or through the thickness of the layer (horizontally and/or vertically in the sense of the growth direction). The portions may be distributed in a regular array or irregular pattern across the layer, and/or through it. The porosity may be constant or variable within the porous regions. Where the porosity is variable it may be linearly varied through the thickness, or may be varied according to a different function such as quadratic, logarithmic or a step function.

[0026] A porous layer means that pores have been formed through bulk material so that voids are intentionally introduced. Porosity is expressed in percentages which refers to the volume of bulk material which has been removed so 25% porosity means that the 25% of the equivalent volume of bulk material is voided.

[0027] Where a device is described it should be understood that it will typically be formed on a circular substrate wafer of 4" (100mm), 6" (150mm), 8" (200mm), 12" (300mm) or greater diameter. After growth, deposition, bonding and other fabrication steps the devices are separated by dicing the wafer and layers into devices (chips) of appropriate dimensions. Typically tens, hundreds or thousands of devices are cut from a single wafer.

[0028] Throughout the present disclosure corresponding elements in the Figures are labelled with corresponding reference numerals.

[0029] Examples according to the present disclosure provide a technique for epitaxially forming a semiconductor structure comprising a two-step growth technique. A plurality of III-V semiconductor layers are formed over a substrate and a first III-V semiconductor layer is formed over the plurality of III-V semiconductor layers. The first III-V semiconductor layer is formed using the two-step growth technique. A first sub-layer is formed, which may be referred to as a nucleation layer. A second sub-layer is formed over the first sub-layer, which may be referred to as an extension layer. The first sub-layer comprises a first set of elements and the second sub-layer comprises the first set of elements. The two-step growth technique according to examples of the present disclosure may be applied to a variety of semiconductor structures to improve the formation of the second III-V semiconductor layer.

[0030] In one example, the two-step growth technique may be applied to an epitaxial growth technique for a high electron mobility transistor (HEMT). As will be described in more detail below, it is desirable to form a sharp interface between the channel layer and barrier layer of a HEMT to improve formation of the two-dimensional electron gas (2DEG) in the channel layer. However, it is challenging to form a sharp interface between some semiconductor materials selected for the channel layer and barrier layer. In particular, it can be challenging to form a sharp interface between a GaN channel layer and a AIN barrier layer. Examples according to the present disclosure enable the formation of a sharp interface between the GaN channel layer and a AIN barrier layer by forming the AIN barrier layer using the two-step growth technique.

[0031] In another example, the two-step growth technique may be applied to an epitaxial growth technique for a microLED. As will be described in more detail below, it is desirable to form a smooth cap layer for a microLED to bond the microLED structure to other structures during device fabrication. However, it can be challenging to form smooth cap layers in some materials such as the III-P material system. Examples according to the present disclosure enable the formation of a smooth cap layer for a microLED by forming the cap layer using a two-step growth technique.

[0032] In some examples, the composition of the first sub-layer and the composition of the second sub-layer of the first III-V semiconductor layer may both consist essentially of a first set of elements. For example, where the second III-V semiconductor layer comprises a AIN barrier for a HEMT, the composition of the first sub-layer and the composition of the second sub-layer may consist essentially of AIN. Group III elements such as Ga or In may be incorporated into the composition of the first or second sub-layer, which consists essentially of AIN. In a similar manner, where the second III-V semiconductor layer comprises a GaP cap layer for a microLED, the composition of the first sub-layer and the composition of the second sub-layer may consist essentially of GaP. In some examples, the first or second sub-layer of the GaP cap layer may also consist essentially of other elements or impurities such as dopants, for example, C. To provide additional context to the description of the examples according to the present disclosure, there now follows a discussion of the drawbacks, which some HEMTs suffer from.

[0033] The high electron mobility transistor (HEMT) is a semiconductor device commonly formed from III-N materials. The HEMT has found use in many applications. III-N HEMTs typically exhibit a higher breakdown voltage and greater electron mobility than Si MOSFETs. The use of III-N HEMTs has therefore found use in power and radio frequency (RF) communications applications.

[0034] III-N HEMT fabrication involves epitaxially growing layers of III-N semiconductor material on a substrate. Figure 1 illustrates an example of a HEMT epitaxial semiconductor structure 100. Semiconductor structure 100 comprises a substrate 110, which can comprise SiC, Sapphire or Si.

[0035] The structure 100 further includes a buffer layer 120, which is designed to eliminate defects and provide isolation between the substrate 110 and the channel layer 130 above the buffer layer 120. The buffer layer 120 can also be doped to aid in the isolation properties. In some examples, the dopant may comprise Fe or C. In some examples, the buffer layer 120 may comprise GaN or AlGaN with a low Al content.

[0036] Semiconductor structure 100 further includes the channel layer 130. Typically, the channel layer 130 comprises GaN. Channel layer 130 provides the channel in the H EMT for charge carriers to flow. A 2-dimensional electron gas (2DEG) is formed in the channel layer 130, which confines the electrons and results in the H EMT exhibiting high electron mobility properties.

[0037] The semiconductor structure 100 further comprises a barrier layer 140. Barrier layer 140 creates a polarization discontinuity between itself and the channel layer 130, resulting in the formation of the 2DEG in the channel layer 130. In some examples, the barrier layer may comprise AIN, AlGaN, AlInN or AlGaInN.

[0038] The semiconductor structure 100 further comprises a cap layer 150, which passivates surface defects of the barrier layer 140 to improve electrical performance of the structure 100. In some examples, the cap layer 150 comprises GaN, SiN or SiO2.

[0039] In III-V epitaxial growth techniques, it is typically desirable to form epitaxial layers with a sharp interface between two layers. In particular, the interface between the channel layer 130 and barrier layer 140 can play in important role in the formation of the 2DEG in the channel layer 130. It is typically desirable to form a sharp interface between the channel layer 130 and barrier layer 140 to increase the polarization discontinuity between the two layers and thereby form a denser 2DEG with greater mobility. However, with some combinations of materials used for the channel layer 130 and barrier layer 140 it can be difficult to epitaxially form a sharp interface between the channel layer 130 and barrier layer 140.

[0040] Figure 2 illustrates another example of a semiconductor structure 200 comprising epitaxial layers for forming a H EMT. Semiconductor structure 200 comprises a channel layer 230 comprising GaN and a barrier layer 240 comprising AIN.

[0041] Recent industry trends have pushed HEMT architectures towards the use of thin barrier layers with a thickness of less than 10 nm. A thin barrier layer allows for scaling of devices and mitigation of short channel effects in small gate length devices. AIN is a good candidate for thin barrier layers in III-Nitride based devices, due to the high polarization discontinuity between itself and the GaN based alloys used in the channel layer 230. However, it is difficult to obtain an abrupt interface between a GaN channel and an AIN barrier formed by MOCVD. Often, a transition region 235 is formed between the two layers. The desirable < 10 nm thickness regime for the barrier layer 240 also includes the transition region 235. Therefore, a barrier region 260 is commonly formed which includes the AIN barrier layer material 240 and the transition region 235. In some examples, the barrier region 260 thickness is less than 10 nm. However, as illustrated in Figure 2, the majority of the barrier region 260 thickness is taken up by the transition region 235, which is significantly thicker than the AIN barrier layer 240 material. The transition region 235 typically comprises an AlGaN composition. The formation of the transition region 235 thus results in contamination of the barrier region 260 with Ga in high concentrations. It is preferable to form a barrier region 260 with reduced Ga as the high Ga content dilutes the Al content of the barrier region 260.

[0042] The formation of the transition region 235 and the Ga contamination in the barrier region 260 reduces the effectiveness of the AIN barrier 240 for multiple reasons. The transition region 235 and Ga contamination reduce the polarization discontinuity between the AIN barrier layer 240 and GaN channel 230, resulting in the formation of a less dense 2DEG. The transition region 235 can also lead to increased alloy scattering resulting in reduced mobility of the 2DEG.

[0043] Examples according to the present disclosure provide a semiconductor structure that comprises a plurality of III-V layers over a substrate and a first III-V layer over the plurality. The first III-V layer comprises a III-V nucleation layer and a III-V extension layer over the III-V nucleation layer. The examples according to the present disclosure may thus present an epitaxial deposition technique where a second III-V layer can be formed on a plurality of III-V layers using a two-step growth technique. In some examples, an uppermost layer of the plurality of III-V layers comprises GaN and the first III-V layer comprises AIN. As will be described in more detail below, a first AIN nucleation layer may be epitaxially grown on a GaN layer. The second AIN extension layer may be subsequently grown on the AIN nucleation layer. The two-step growth method according to the present disclosure forms AIN on a GaN layer which reduces or eliminates the transition region observed using conventional techniques. However, the examples according to the present disclosure may reduce or eliminate a transition region formed between any pair of III-V semiconductor layers.

[0044] Figure 3 illustrates an example of a semiconductor structure 300. Semiconductor structure 300 comprises substrate 110, buffer layer 120, channel layer 330, barrier layer 340 and cap layer 150. In some examples, buffer layer 120, channel layer 330, barrier layer 340 and cap layer 150 may be epitaxially deposited on substrate 110. In some examples, buffer layer 120, channel layer 330, barrier layer 340 and cap layer 150 may be deposited on the substrate 110 using a chemical vapour deposition (CVD) technique, such as metal-organic CVD (MOCVD).

[0045] As illustrated in Figure 3, channel layer 330 comprises GaN. In some examples, the channel layer 330 may comprise a thickness of about 10-50 nm.

[0046] As further illustrated in Figure 3, barrier layer 340 comprises AIN. The barrier layer 340 comprises a nucleation layer 342 and an extension layer 344 on the nucleation layer 342. As illustrated in Figure 3, in some examples, the barrier layer 340 may be formed on the channel layer 330 without a transition region.

[0047] As described above, examples according to the present disclosure utilise a two-step growth method to form the AIN barrier layer 340. For example, as described above, the AIN barrier layer 340 may be formed using MOCVD. The nucleation layer 342 is formed using a high temperature. In some examples, the high temperature to form the nucleation layer 342 may be between about 1000-1075 °C. The high temperature forms a nucleation layer 342 on the GaN channel layer 330 with a sharp interface which is 'transition region free', or comprises a very small transition region on the GaN channel layer 330.

[0048] The extension layer 344 is epitaxially grown at a lower temperature than the nucleation layer 342. In some examples, the extension layer growth temperature may be about 200- 300 °C lower than the nucleation layer growth temperature. In some examples, the extension layer 344 growth temperature may be about 700-850 °C. In some examples, the lower temperature for the growth of the extension layer 344 may reduce or eliminate the diffusion of Ga atoms from the channel layer 330 into the AIN barrier layer 340, compared to forming the extension layer 344 at a higher growth temperature. As such, the AIN barrier layer 340 can be formed with a high Al concentration.

[0049] Thus, the combination of the high temperature growth of the AIN nucleation layer 342 and the lower temperature growth of the AIN extension layer 344 enables the formation of the AIN barrier layer 340 on the GaN channel layer 330, where a transition region between the AIN barrier layer 340 and the GaN channel layer 330 is reduced or eliminated. The high temperature growth for the AIN nucleation layer 342 forms a sharp interface with the GaN channel layer 330. However, the AIN nucleation layer 342 comprises a thickness of 1-1.5 nm, which in some examples, may not be thick enough to enable the formation of a 2DEG in the GaN channel layer 330. The AIN extension layer 344 is thus formed at lower temperature to extend the thickness of the AIN barrier layer 340 beyond a thickness that enables the formation of a 2DEG in the GaN channel layer 330. In some examples, the 2DEG enabling thickness of the AIN barrier layer 340 may be about 2.5 nm or more. The AIN extension layer 344 may therefore comprise a thickness of about 1-1.5 nm to achieve the 2DEG enabling thickness for the AIN barrier layer 340. However, in other examples, the AIN extension layer 344 may be increased such that the AIN barrier layer 340 may comprise a total thickness of 2.5-10 nm.

[0050] Conventionally, a AIN barrier is grown at high temperatures of 1000 °C or more for the entire thickness of the AIN barrier layer. This temperature regime is conventionally preferred to form the AIN barrier layer with high crystallinity. However, as described above, this growth technique leads to the formation of a transition region and the diffusion of Ga, from the GaN channel layer, into the AIN barrier layer. Examples according to the present disclosure implement a two-step growth method where the AIN nucleation layer deposited on the GaN channel layer is grown at a high temperature. The high temperature growth for the AIN nucleation layer does result in some Ga diffusing from the GaN channel layer into the nucleation layer. However, the nucleation layer is thin, so that the Go diffusion into the AIN barrier layer is kept to a minimum. The extension layer can then be grown at a lower temperature, which helps avoid the diffusion of Ga contaminants from the GaN channel layer into the AIN barrier layer.

[0051] The two-step growth method according to examples of the present disclosure may enable the formation of a thin 10 nm) AIN barrier layer 340 with a high Al percentage incorporation. In some examples, barrier layer 340 may comprise Al, where Al comprises at least 80% of the group III elements. In some examples, barrier layer 340 may comprise Al, where Al comprises at least 95% of the group III elements. In conventional examples, using CVD techniques such as MOCVD, it is difficult to form a thin AIN barrier layer comprising Al with a concentration of more than 75 % of the group III elements.

[0052] Commonly, a conventional thin AIN barrier layer can comprise an Al concentration with a concentration of 60% of the group III elements. This can be due to the transition region and Ga diffusion observed in conventional techniques. Examples according to the present disclosure thus enable the formation of an AIN barrier layer with increased Al concentration. The increased Al concentration of the barrier layer 340 results in greater polarization discontinuity with the GaN channel layer 330 and a denser 2DEG.

[0053] In some examples, the barrier layer 340 may thus consist essentially of AIN. The composition of the nucleation layer 342 and extension layer 344 may thus both consist essentially of AIN due to the high Al incorporation into the nucleation layer 342 and extension layer 344. Impurities such as Ga may be present in the barrier layer 340, whilst the barrier layer consists essentially of AIN. In particular, as described above, the AIN nucleation layer 344 may comprise a higher concentration of Ga impurities than the AIN extension layer 342 due to the high temperature growth for the AIN nucleation layer 342.

[0054] However, in such examples, even with the Ga impurities, the AIN nucleation layer 342 and AIN extension layer 344 may both consist essentially of AIN.

[0055] As described above, in conventional MOCVD epitaxial growth techniques it is challenging to form thin AIN barrier layers with an Al content greater than about 60%.

[0056] Group III material present in the MOCVD reactor commonly occupies the group III sites in the crystal lattice decreasing the Al incorporation. Such group III material is considered an impurity. In particular, in III-N MOCVD HEMT growth techniques a relatively large proportion of Ga can be incorporated into the AIN barrier. For example, the AIN barrier layer can comprise Ga in a concentration of up to 40% of the group III material, where the Ga material is still considered an impurity in an otherwise AIN barrier layer. As such, in examples according to the present disclosure, where the AIN nucleation layer 342 or the AIN extension layer 344 consists essentially of AIN, the AIN nucleation layer 342 or the AIN extension layer 344 may comprise group III impurities, such as Ga, with a concentration of up to 40%. It will further be noted that other III-V materials formed by MOCVD may typically comprise a much lower impurity concentration. For example, GaN material formed by MOCVD typically comprises group III impurities with a concentration of less than 1%.

[0057] In some examples, the AIN barrier layer 340 may comprise a small concentration of In.

[0058] In some examples, In can be used as a surfactant, which can improve the crystal quality of the AIN barrier layer 340. The In surfactant improves the lateral mobility of atoms deposited on to the epitaxial growth surface, which in turn, improves the crystal quality of the epitaxially formed material. In some examples, the low temperature growth for the AIN extension layer 344 may exhibit poor crystallinity, as crystallinity typically degrades using lower growth temperatures. In some examples, the use of the In surfactant may therefore improve the crystallinity of the AIN extension layer 342 formed at lower temperatures.

[0059] Thus, in examples according to the present disclosure, during the growth of the AIN barrier layer 340, a small amount of In may be used. In particular, In may be used as a surfactant during formation of the AIN extension layer 344, which may be formed at low temperatures. In some examples, the In may be present at or towards the upper surface, away from the substrate 110, of the AIN barrier layer 340. In some examples, the In may thus be present in the AIN extension layer 344. In some examples, the barrier layer 340 comprises In with a concentration of less than 3% of the group III elements. In some examples, the barrier layer 340 comprises In with a concentration of less than 1% of the group III elements. In such examples, where the AIN barrier 342 or the AIN extension layer 344 consists essentially of AIN, the AIN barrier 342 or the AIN extension layer 344 may further comprise In. In such examples, the AIN barrier 342 or the AIN extension layer 344 may comprise In with a concentration of 3% or less of the group III material.

[0060] In is one example of a suitable surfactant and in other examples an alternative surfactant may be used. For example, the surfactant may comprise Sb or Bi. However, in examples according to the present disclosure based in III-N material systems, In may comprise advantages over alternative surfactants because In sources are widely available and can be readily applied to MOCVD reactors for III-N epitaxial growth. However, in other examples, an alternative surfactant can be used such as Sb or Bi.

[0061] Figures 4a-b are examples of scanning transmission electron microscopy (STEM) images 400a, 400b of semiconductor structures.

[0062] Figure 4a is a STEM image 400a of conventional semiconductor structure, such as, semiconductor structure 200 described above. As illustrated in STEM image 400a, a transition region 235 is present between the GaN channel layer 230 and the AIN barrier layer 240. In some examples, the transition region 235 may comprise AlGaN. In some examples, the transition region 235 comprises a thickness of about 4.5 nm. As described above, the thick transition region 235 can degrade the 2DEG in the channel layer 230.

[0063] Figure 4b is a STEM image 400b of a semiconductor structure according to examples of the present disclosure, such as semiconductor structure 300 described above. As illustrated in STEM image 400b, a transition region is not present between the GaN channel layer 330 and the AIN nucleation layer 342. In other examples, however, a small transition region may be present between the GaN channel layer 330 and the AIN nucleation layer 342. In any case, examples according to the present disclosure with a small or non-existent transition region may result in an improved 2DEG formation in the GaN channel layer 330.

[0064] Figures 5a-b are examples of X-ray spectroscopy (EDX) results 500a, 500b of semiconductor structures.

[0065] EDX result 500a illustrates normalized concentrations of Al and Ga across a conventional semiconductor structure, such as semiconductor structure 200 described above. As illustrated in EDX result 500a, a transition region 235 is between the GaN channel layer 230 and AIN barrier layer 240. The transition region 235 comprises Al and Ga, as indicated in the EDX result 500a. The transition region 235 comprises Al with a concentration less than 50%. The AIN barrier 240 comprises Al with a concentration greater than 50%. The transition region 235 further comprises a thickness of about 4.5 nm. The transition region 235 thus comprises a thickness more than two times greater than the thickness of the AIN barrier layer 240, which comprises a thickness of about 2 nm. As described above, in conventional examples, the barrier region 260 thickness typically comprises the transition region 235 and the AIN barrier layer 240. Therefore, whilst the barrier region 260 including the transition region 235 and AIN barrier 240 may comprise a thickness of 6.5 nm, only 2 nm of this thickness comprises the AIN barrier 240. The transition region 235 therefore reduces the polarization discontinuity between the channel layer 230 and barrier layer 240.

[0066] EDX result 500b illustrates normalized Al, Ga, In and Si concentrations across a semiconductor structure according to examples of the present disclosure, for example, semiconductor structure 300 described above. EDX result 500b illustrates a transition region 335 between the GaN channel 330 and the AIN barrier 340. The transition region 235 comprises Al with a concentration less than 50%. The AIN barrier 240 comprises Al with a concentration greater than 50%.

[0067] The transition region 335 comprises a thickness between 1-1.5 nm, which is less than a third of the thickness of transition region 235 illustrated in EDX result 500a. In other examples, transition region 335 may comprise a thickness of 2 nm or less. The reduced thickness of transition region 335 thus greatly improves the polarization discontinuity between the GaN channel layer 330 and the AIN barrier layer 340. For example, a barrier region 360 may comprise the transition region 335 and the AIN barrier layer 340. The barrier 360 comprises a thickness of about 6.5 nm where the AIN barrier 340 comprises between 5-5.5 nm of the barrier region 360 thickness. The vast majority of the barrier region 360 thickness thus comprises the AIN barrier layer 340 material, which leads to a denser 2DEG compared to conventional examples. Furthermore, the transition region 335 with reduced thickness results in the AIN barrier layer 340 exhibiting lower Ga contamination and higher Al concentration compared to conventional examples.

[0068] EDX result 500b further illustrates a small In concentration in the AIN barrier layer 340. As described above, In may be used as a surfactant during the epitaxial growth of the extension layer of the barrier layer 340. The small In concentration is thus present in the barrier layer 340 due to the use of In as a surfactant.

[0069] Cap layer 150 comprises SiN as indicated by the Si in cap layer 150.

[0070] Whilst examples according to the present disclosure have been described with respect to an epitaxial structure for a HEMT, one skilled in the art will appreciate that the examples according to the present disclosure may be applied to other semiconductor structures Figure 6 is another example of a semiconductor structure 600. Semiconductor structure 600 comprises a superlatfice 601 formed over the substrate 110. Superlatfice 601 may be epitaxially formed on the substrate 110. Although superlattice is 601 is illustrated directly on substrate 110, one or more layers may be present between the superlattice 601 and the substrate 110.

[0071] Superlattice 601 comprises a first unit 602a comprising a first AIN layer 620 formed over a first GaN layer 610. The superlattice 601 further comprises a second unit 602b comprising a second AIN layer 640 formed over a second GaN layer 630. The superlattice 601 further comprises a third unit 602c comprising a third AIN layer 660 formed over a third GaN layer 650. In some examples, superlattice 601 may thus be formed by repeating a plurality of units 602a-c a plurality of times. Although three units 602a-c are illustrated as forming superlattice 601, it will be appreciated that the superlattice 601 may comprise more or less than three units 602a-c.

[0072] The first, second and third AIN layers 620, 640, 660 may thus be formed on the first, second and third GaN layers 610, 630, 650, respectively, using the two-step growth method according to examples of the present disclosure. The first, second and third AIN layers 620, 640, 660 may thus each comprise a nucleation layer and extension layer, in a similar manner to the AIN barrier layer described above. In some examples, a thin transition region may thus be present between the first, second and third AIN layers 620, 640, 660 and the first, second and third GaN layer 610, 630, 650, respectively, in a similar manner to the AIN barrier layer described above.

[0073] In some examples, the superlattice 601 may be used as an active region for an optoelectronic semiconductor device. For example, the first, second and third GaN layers 610, 630, 650 may comprise quantum wells and the first, second and third AIN layers 620, 640, 660 may comprise barrier layers. In some examples, the superlattice 601 may be configured to emit light across a section of the visible light spectrum at 380-700 nm. In some examples, the superlattice 601 may be configured to emit blue light with a peak wavelength of 450-495 nm. In some examples, the superlattice 601 may be configured to emit green light with a peak wavelength of 495-570 nm. In some examples, the superlattice 601 may be configured to emit red light with a peak wavelength of 620-700 nm.

[0074] In some examples, the superlattice 601 may be used for strain relief. For example superlattice 601 can be engineered in order to control how strain is managed within an epitaxial semiconductor structure. In some examples, characteristics such as the thicknesses of one or more of the first, second and third GaN layers 610, 630, 650 may be different from one another and characteristics such as the thicknesses of one or more of the first, second and third AIN layers 620, 640, 660 may be different from each other. For example, the layer thicknesses of the first, second and third GaN layers 610, 630, 650 and the first, second and third AIN layers 620, 640, 660 can be modified to form an effective average lattice constant for the superlattice 601. The effective average lattice constant can be tailored to lie between GaN and AIN, which can relax differently than a bulk GaN/AIN/AlGaN film. Furthermore, controlling the effective lattice constant of the superlattice 601 can change how relaxation occurs within an epitaxial semiconductor structure and the defects that can form as a result of the relaxation. Controlling the relaxation and defects can lead to major shifts in the strain state of both the superlattice 601 and the semiconductor layers grown thereon.

[0075] Although superlattice 601 is illustrated as being directly on substrate 110, it will be appreciated that, in other examples, one or more semiconductor layers may be positioned between the substrate 110 and the superlattice 601. Furthermore, in some examples, one or more semiconductor layers may be formed over the superlattice 601.

[0076] Examples according to the present disclosure have thus far been described in relation to a III-N material system where a transition region between a GaN layer and AIN layer can be reduced or eliminated. However, examples according to the present disclosure may be applicable to any III-V semiconductor material system.

[0077] For example, examples according to the present disclosure may further be applied to a III-P material system for forming a microLED.

[0078] To provide additional context to the description of the examples according to the present disclosure, there now follows a discussion of the drawbacks, which some microLEDs suffer from.

[0079] Figure 7 illustrates an example of a semiconductor structure 700 for forming a microLED.

[0080] The semiconductor structure 700 includes a substrate 710. The substrate 710 may comprise a growth substrate to enable the epitaxial formation of semiconductor layers thereon.

[0081] Semiconductor structure 700 further comprises a first cladding layer 720, an active region 730, a second cladding layer 740 and a cap layer 750 stacked on the substrate 700. In some examples, the first cladding layer 720, the active region 730, the second cladding layer 740 and the cap layer 750 may be epitaxially grown on the substrate 710, such as by MOCVD or MBE.

[0082] The active region 730 may comprise one or more light emitting layers comprising structures such as quantum wells, quantum dots, or a combination thereof. The active region 730 may further comprise one or more barrier layers separating the light emitting layers.

[0083] The cladding layers 720, 740 are disposed either side of the active region 730. The cladding layers 720, 740 are configured to form a p-n junction either side of the active region 730, such that carriers can recombine in the active region 730 for light emission. The cladding layers 720, 740 may be oppositely doped. For example, the first cladding layer 720 may be doped n-type and the second cladding layer 740 may be doped p-type.

[0084] In other examples, the first cladding layer 720 may be p-type and the second cladding layer 740 may be n-type.

[0085] Semiconductor structure 700 further comprises cap layer 750. Cap layer 750 is highly doped in order to form an ohmic contact with contacts fabricated on the cap layer 750.

[0086] In one example, the cap layer 750 may comprise a dopant concentration of about 1 x 1019 cm-2 to about 7 x 1019 cm-2, for example, about 5 x 1019 cm-2.

[0087] In some examples the semiconductor structure 700 may further comprise one or more mirrors. For example, the semiconductor structure 700 may comprise a first mirror situated between the cladding layer 720 and the substrate 710 to reflect light and increase the microLED brightness. In some examples, the semiconductor structure may comprise a second mirror situated between the cladding layer 740 and the cap layer 750. The first and second mirrors may thus form a resonant cavity, which may be used for forming a resonant cavity microLED. In such examples, the mirror may be formed of semiconductor material such as those for forming a distributed Bragg reflector (DBR).

[0088] In some examples, contacts may be fabricated on to the semiconductor structure 700 to form the microLED. For example, a first contact may be applied to the substrate 710 and a second contact may be applied to the cap layer 750. The contacts inject carriers into the active region 730, where they recombine to result in the emission of light from the microLED.

[0089] MicroLEDs are a class of LEDs with a small diameter of the order of 100 pm or less. However, in some examples, microLEDs can comprise a diameter of 10 pm or less. There is great interest in microLEDs because their smaller size leads to a greater number of emitters per pixel with increased brightness, contrast, colour gamut and efficiency compared to conventional LEDs in display applications. However, the smaller size of microLEDs leads to design and fabrication challenges.

[0090] Conventional LEDs typically include a thick cap layer, which improves current spreading in the LED. The cap layer also includes a rough morphology in order to enable diffusive light emission. Due to the smaller diameter of a microLED, the current spreading capabilities provided by a thick cap layer are not as advantageous. It is more desirable to form cap layers for a microLED with a reduced thickness of 500 nm or less, as a thicker cap layer can contribute to a high aspect ratio for the microLED, which is more challenging for etching during fabrication. Furthermore, for microLED fabrication, it is becoming desirable to bond the cap layer to driving circuitry. To achieve reliable bonding, it is desirable for the cap layer to comprise a smooth surface morphology. However, forming a smooth morphology with a reduced thickness in some semiconductor materials is challenging.

[0091] In particular, it can be challenging to form a smooth cap layer for a microLED in the III-P material system. The III-P material system is of interest for microLED applications because it can reliably achieve emission at the red part of the visible spectrum, for example, across the region of 610-650 nm.

[0092] Examples according to the present disclosure provide a semiconductor structure that comprises a plurality of III-V layers over a substrate and a first III-V layer over the plurality. The first III-V layer comprises a III-V nucleation layer and a III-V extension layer over the III-V nucleation layer. The examples according to the present disclosure may thus present an epitaxial deposition technique where a first III-V layer can be formed on a plurality of III-V layers using a two-step growth technique. In one example, the plurality of III-V layers may comprise a plurality of layers for forming a microLED including a cladding layer. The first III-V layer may comprise a cap layer for a microLED. In one example, the cladding layer may comprise Alln(Ga)P and the cap layer may comprise GaP. In such examples, the two-step growth technique may enable the formation of a GaP cap layer with a reduced thickness and smooth morphology. In particular, as will be described in more detail below, the two-step growth technique balances an etchback/growth regime to achieve the smooth morphology.

[0093] Figure 8 is an example of a semiconductor structure 800 for forming a microLED. In one example, the semiconductor structure 800 may comprise III-P semiconductor material for forming a red-emitting microLED.

[0094] In some examples, substrate 710 may thus comprise GaAs or Ge. GaAs and Ge may permit the formation of an epitaxial III-P layer stack thereon.

[0095] In some examples, first cladding layer 720 and second cladding layer 740 may comprise Alln(Ga)P material. In some examples, the first cladding layer 720 and second cladding layer 740 may comprise a plurality of layers comprising varying compositions of Alln(Ga)P. In some examples, the first cladding layer 720 and second cladding layer 740 may be doped. For example, the first cladding layer 720 may be doped n-type and second cladding layer 740 may be doped p-type. In some examples, the n-type dopant may comprise Si and the p-type dopant may comprise C. In some examples, the first cladding layer 720 and second cladding layer 740 may comprise a doping concentration of about lx 1018 cm-2 to about 2 x 1018 cm-2.

[0096] In some examples, the active region 730 may comprise one or more InGaP quantum wells and one or more Alln(Ga)P barrier layers configured to confine carriers into the InGaP quantum wells. In some examples, the InGaP quantum wells may be tuned to emit light in the red part of the visible light spectrum across a region of about 610-650 nm.

[0097] In some examples, the cap layer 850 may comprise GaP. As described above, the cap layer 850 may be highly doped to form an ohmic contact with a contact for injecting carriers into the microLED. In some examples, the cap layer 850 may comprise a doping concentration of about 1 x 1019 cm-2 to about 7 x 1019 cm-2, for example, about 5 x 1019 cm-2. In some examples, the cap layer 850 may be doped p-type. In some examples, the p-type dopant may comprise C. As illustrated in Figure 8, the cap layer 850 comprises a GaP nucleation layer 852 and a GaP extension layer 854. The GaP nucleation layer 852 and the GaP extension layer 854 may be formed using different growth conditions to result in the GaP cap layer 850 comprising a smooth morphology and thin thickness. The cap layer 850 may thus be formed using a two-step growth technique where the nucleation layer 852 is formed using a first set of growth conditions and the extension layer 854 is formed on the nucleation layer 852 using a second set of growth conditions. In some examples, the cap layer 850 comprises a thickness of 500 nm or less. In some examples, the cap layer 850 may comprise a thickness of 100 nm or less.

[0098] The two-step growth technique according to examples of the present disclosure balances an etch-back and growth regime to result in the formation of a smooth cap layer 850. In epitaxial growth techniques, certain materials and conditions can result in an etching effect where epitaxial material is removed during growth. Typically, this is undesirable as it removes deposited material and increases growth time. However, in examples, according to the present disclosure, the etch-back effect is utilised to result in smoothing of the cap layer 850 during epitaxial growth. The etch-back effect is balanced with deposition to achieve a low growth rate, where the etching effect also aids smoothing the surface of the epitaxially deposited material.

[0099] As described above, the cap layer 850 comprises GaP, which may be doped with C. In some examples, CBr4 may be used as the material for incorporating C into the cap layer 850. CBr4 results in etching of the GaP material under some growth conditions. For example, at low growth rates Br radicals, thermally decomposed from CBr4, can combine with group III atoms such as Ga, which are desorbed from the growth surface into the vapor phase, with subsequent thermal removal of P. In conventional examples, where thick and rough GaP layers are desired, it is common to grow a GaP cap layer at a growth rate of about 3 pm per hour. In some examples, such a growth rate can be achieved with a V/III ratio of about 6 and at a temperature of about 650-700 °C. Under these growth conditions, a growth rate is achieved, which is not mass transport or thermodynamically limited and the etch-back effect of CBr4 does not therefore have an impact on growth rate.

[0100] Examples according to present disclosure utilise growth conditions to take advantage of the etch-back effect of CBr4. Examples according to the present disclosure utilise growth conditions to achieve a low growth rate where the etch-back effect can be used to achieve smoothing and thus reduce the surface roughness of the cap layer 850.

[0101] In some examples, the cap layer 850 may be grown at a low growth temperature. For example, the low growth temperature may range from about 510-600 °C. In some examples, the cap layer 850 may be grown at a growth temperature of about 520-560 °C. In one example, the growth temperature may be about 540 °C.

[0102] In epitaxial growth techniques, the epitaxy reaction rate has kinetic and mass transport limiting factors. In the mass transport limited regime, the growth rate, within a suitable temperature window, is expected to be linear with group III flow. In this regime increasing the V/III ratio will decrease the growth rate, and decreasing the V/III ratio will increase the growth rate. However, at low temperatures the growth is further limited by the reduced cracking of the group V atoms. Examples according to the present disclosure utilise a low temperature for forming the cap layer 850, where there is reduced cracking of the group V atoms. Increasing the group V flow rate can increase the growth rate in this regime. Additionally, in this lower temperature regime, the DopantN ratio at the growth interface strongly controls the reaction rate and surface kinetics. In this regime, the etch-back effects of CBr4 have an effect on the growth rate, which is not typically observed for higher temperature growth. A higher DopantN ratio results in increased etch back, and decreased overall growth rate. However, the etch-back effect also results in smoothing of the growth surface. Examples according to the present disclosure therefore involve controlling the dopant/V ratio in the low temperature regime to result in a low growth rate where the etch back effect of CBr4 is utilised to smooth the growth surface. In examples according to the present disclosure, the V/III ratio and the dopant/V ratio are therefore controlled during the epitaxial growth of the cap layer 850 to achieve a net positive growth rate, but which also utilises the etch-back effect of CBr4 to achieve smoothing of the cap layer 850.

[0103] Cap layer 850 is thus formed using a low growth temperature to reduce the growth rate of the cap layer 850 to become dependent on the V/III ratio and dopant/V ratio. At low growth temperatures, it can be difficult to nucleate some materials such as GaP on the cladding layer 740. As such, growth conditions are configured to form a nucleation layer 852 on the cladding layer 740 to nucleate the cap layer 850. In some examples, the growth conditions for the nucleation layer 852 are adjusted to achieve a very low growth rate such that a smooth nucleation layer 852 is formed on the cladding layer 740. The smooth nucleation layer 852 may provide a suitable high-quality smooth surface on which an extension layer 854 may be grown. The formation of the nucleation layer 852 and the extension layer 854 thus represents a two-step growth technique to form the cap layer 850.

[0104] In some examples, the extension layer 854 may be thicker than the nucleation layer 852 and form the majority of the thickness of the cap layer 850. In some examples, the extension layer 854 may be grown at a faster growth rate than the nucleation layer 852. The growth rate for the nucleation layer 852 may be very low to nucleate the cap layer 850 with a smooth surface. However, once the smooth surface of the nucleation layer 852 has been established, the growth rate for the extension layer 854 may be increased, such that the extension layer also forms with the smooth surface, set by the nucleation layer 852, but which can be grown at a faster rate.

[0105] As described above, the nucleation layer 852 may be formed at a low growth temperature, such that the growth rate for the nucleation layer 852 becomes dependent on the V/III ratio and dopantN ratio. In some examples, the nucleation layer 852 may be formed at a temperature of about 510-600 °C. In some examples, the nucleation layer 852 may be grown at a growth temperature of about 520-560 °C. In some examples, the growth temperature may be about 540 °C.

[0106] In some examples, the V/III ratio and dopant/V ratio for the nucleation layer 852 may be controlled to achieve a growth rate of about 0.01-0.2 pm per hour, for example, about 0.06 pm per hour. In such examples, the growth rate for the nucleation layer 852 may be achieved with a V/III ratio of about 38-8 and a dopant/V ratio of about 0.01-0.03. In some examples, the growth rate of the nucleation layer 852 may be ramped to initially start at a very low growth rate and ramp to a higher growth rate. In some examples, the growth rate of the nucleation layer 852 may be ramped from a low growth rate to a higher growth rate to match the growth rate for the extension layer 854. In such examples, the nucleation layer growth rate may be controlled from about 0.01-0.2 pm per hour, and ramp to about 0.3-0.9 pm per hour. The V/III ratio and dopant/ratio may thus be adjusted accordingly to achieve the growth rate ramp. In some examples, maintaining the dopantN ratio at a constant value and ramping the V/III ratio may adjust the growth rate during the formation of the nucleation layer 852. The nucleation layer 852 may be thin, as it may not be practical to grow an entire cap layer 850 at the low grow rate of the nucleation layer 852. In some examples, the nucleation layer 852 may comprise a thickness of about 5-20 nm.

[0107] Extension layer 854 is epitaxially grown over the nucleation layer 852. Extension layer 854 is formed at a low growth temperature in a similar manner to the nucleation layer 852 such that the growth rate becomes dependent on the V/III ratio and dopantN ratio. In some examples, the extension layer 854 may be formed at a temperature of about 510-600 °C. In some examples, the extension layer 854 may be grown at a growth temperature of about 520-560 °C. In some examples, the growth temperature may be about 540 °C. In some examples, the growth temperature for the nucleation layer 852 and extension layer 854 may thus comprise the same temperature.

[0108] Extension layer 854 is formed at a low growth rate compared to conventional examples, but at a higher growth rate than the nucleation layer 852 growth rate. In some examples, the extension layer 854 growth rate may comprise 0.2-1 pm per hour. In some examples, the extension layer growth rate may comprise about 0.5-1 pm per hour, for example, 0.6 pm per hour. Thus, in some examples, the extension layer 852 may comprise a growth rate 10 times greater than the nucleation layer 852 growth rate. The increased growth rate between the extension layer 854 and nucleation layer 852 may be controlled by adjusting the V/III ratio. For example, the extension layer 854 may be formed with a V/III ratio of up to 6, for example, about 4. In some examples, the dopant/V ratio for the extension layer 854 may comprise about 0.01-0.03.

[0109] In some examples, the dopantN ratio may be dictated by the desired doping concentration of the cap layer 850. As such, the dopant/V ratio may be the same for the nucleation layer 852 and extension layer 854 and therefore the V/III ratio may be the variable that is adjusted to control the growth rate of the nucleation layer 852 and extension layer 854. However, in other examples, the dopant/V ratio and the V/III ratio may be adjusted to control the growth rate of the nucleation layer 852 and extension layer 854. In particular, C dopants occupy the group V sites within the lattice structure of III-P materials. Therefore, increasing the group V flow, and therefore increasing the V/III ratio, during the epitaxial growth, can reduce the amount of C dopant incorporation into the cap layer 850. Therefore, changes to the V/III ratio may result in changes to the dopant flow in order to achieve a V/III ratio and dopant/V ratio that results in a positive growth rate, without excessive etch back and high C dopant incorporation.

[0110] In some examples, the cap layer 850 may consist essentially of GaP. The composition of the GaP nucleation layer 852 and the GaP extension layer 854 may both consist essentially of GaP.

[0111] Figures 9a-b are examples of haze measurements. Haze measurements provide a measure of surface roughness, as one skilled in the art would readily understand.

[0112] Figure 9a illustrates a first haze measurement 900a performed on a GaP cap layer of a conventional semiconductor structure. As illustrated, the cap layer is so rough that individual imperfections on the wafer surface cannot be resolved by the haze measurement tool.

[0113] Figure 9b illustrates a second haze measurement 900b performed on a GaP cap layer of a semiconductor structure according to examples of the present disclosure. As illustrated, the surface roughness of the GaP cap layer is greatly improved compared to the first haze measurement 900a, formed with conventional examples. The haze measurement has a defect count of 6.03 cm-2. The haze measurement is therefore significantly improved compared to conventional examples.

[0114] Figure 10 is an example of atomic force microscope (AFM) result 1000.

[0115] Figure 10 is an AFM result 1000 performed on a GaP cap layer of a semiconductor structure according to examples of the present disclosure. AFM result 1000 has a root mean square (RMS) roughness value of 3.86 nm measured over a 10 pm x 10 pm area. Conventional cap layers for LEDs commonly achieve a RMS roughness value of 50 nm or more, as measured over a 10 pm x 10 pm area.

[0116] Examples according to the present disclosure may therefore comprise a RMS roughness value of less than 50 nm, as measured over a 10 pm x 10 pm area using an AFM. In some examples, a cap layer according to examples of the present disclosure may comprise a RMS roughness value of less than 30 nm, as measured over a 10 pm x 10 pm area using a AFM. In some examples, a cap layer according to examples of the present disclosure may comprise a RMS roughness value of less than 20 nm, as measured over a 10 pm x 10 pm area using a AFM. In some examples, a cap layer according to examples of the present disclosure may comprise a RMS roughness value of less than 10 nm, as measured over a 10 pm x 10 pm area using a AFM. In some examples, a cap layer according to examples of the present disclosure may comprise a RMS roughness value of less than 5 nm, as measured over a 10 pm x 10 pm area.

[0117] Examples according to the present disclosure therefore improve the surface roughness of a cap layer for a microLED.

[0118] Examples according to the present disclosure have thus provided a way for forming a smooth cap layer for a microLED. However, in other examples, examples according to the present disclosure may be applied to a cap layer for any semiconductor device, such as a LED, resonant cavity LED (RCLED) or a VCSEL.

[0119] The present disclosure further provides a semiconductor device comprising a semiconductor structure according to examples of the present disclosure. In some examples the semiconductor device may comprise a semiconductor device for wireless radio frequency (RF) communication. In some examples the semiconductor device for wireless radio frequency (RF) communication may comprise a high electron mobility transistor (HEMT). In some examples the semiconductor device may comprise a photonic semiconductor device. In some examples the photonic semiconductor device may comprise one of: a light emitting diode (LED) or a micro LED (pLED).

[0120] The present disclosure further provides an RF module comprising a semiconductor device according to examples of the present disclosure. In some examples the RF module may comprise one of a switch module, a power amplifier module, a transmitter module, a receiver module and a transceiver module.

[0121] The present disclosure further provides an electronic device comprising an RF module according to examples of the present disclosure.

[0122] In some examples the electronic device may comprise a communication device for user operation such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a communications infrastructure device, such as a communication infrastructure device for a base station, a cell tower or similar. In some examples the electronic device may comprise a communication hub, such as a W-Fi router or switch. In some examples the electronic device may comprise a communications device for a radar device, such as a radar transmitter, radar receiver, radar transceiver or similar.

[0123] In some examples the electronic device may comprise an electronic device for user operation. In some examples the electronic device may comprise a communication device such as a mobile telephone, smartphone or similar. In some examples the electronic device may comprise a handheld computing device, such as a tablet or similar. In some examples the electronic device may comprise a visual display device, such as a television, a monitor or similar. In some examples the electronic device may comprise a wearable device, such as a smartwatch, smart glasses, or similar. In some examples the electronic device may comprise a gaming device such as a games console or similar. In some examples the electronic device may comprise a headset such as a virtual reality (VR) headset, an augmented reality (AR) headset, or similar. In some examples the electronic device may comprise an audio accessory device, such as headphones, earphones, wireless headphones, true wireless headphones, earbuds, or similar. In some examples the electronic device may comprise an appliance such as a household appliance, for example a refrigerator or a washing machine, or similar.

[0124] It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, "a" or "an" does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. CLAIMS 3. 4. 6. 7. 8. 9.A semiconductor structure comprising: a substrate; a plurality of III-V layers over the substrate; and a first III-V layer over the plurality of III-V layers, wherein the first III-V layer comprises: a first sub-layer comprising a first set of elements; and a second sub-layer over the first sub-layer comprising the first set of elements.

2. The semiconductor structure according to claim 1 wherein the first sub-layer comprises a nucleation layer and the second sub-layer comprises an extension layer.

3. The semiconductor structure according to claim 1 or 2 wherein the second sub-layer is thicker than the first sub-layer.

4. The semiconductor structure according to any preceding claim wherein the first sub-layer consists essentially of the first set of elements and the second sub-layer consists essentially of the first set of elements.

5. The semiconductor structure according to claim 1 wherein the plurality of III-V layers comprise a second III-V layer comprising GaN and the first III-V layer comprises AIN.

6. The semiconductor structure according to claim 5 wherein the first III-V layer comprises Al with a concentration of at least 80% of the group III elements.

7. The semiconductor structure according to any preceding claim wherein the first III-V layer comprises a surfactant.

8. The semiconductor structure according to claim 7 wherein the surfactant comprises In.

9. The semiconductor structure according to any preceding claim wherein the first III-V layer comprises a thickness between 2.5 nm to 10 nm.

10. The semiconductor structure according to any preceding claim further comprising a transition region between the plurality of III-V layers and the first III-V layer; wherein the first III-V layer is thicker than the transition region.

11. The semiconductor structure according to claim 10 wherein the transition region comprises a thickness of less than 4.5 nm.

12. The semiconductor structure according to any of claims 10-11 wherein the transition region comprises Al with a concentration between 0-50% of the group III elements; and the first III-V layer comprises Al with a concentration of greater than or equal to 50% of the group III elements.

13. The semiconductor structure according to any of claims 1-4 wherein the first III-V layer comprises Gap.

14. The semiconductor structure according to any preceding claim wherein the first III-V layer comprises an upper surface comprising a route mean square, RMS, roughness value of less than 50 nm as measured over a 10 pm x 10 pm area.

15. The semiconductor structure according to any preceding claim wherein the first III-V layer comprises a thickness of 500 nm or less.

16. The semiconductor structure according to any preceding claim wherein the first III-V layer comprises a doping concentration of 1 x 1019 cm-3 or more.

17. A method comprising: forming a plurality of III-V layers over a substrate; forming a first III-V layer over the plurality of III-V layers, wherein forming the first III-V layer comprises: forming a first sub-layer comprising a first set of elements; and forming a second sub-layer over the first sub-layer comprising the first set of elements.

18. The method according to claim 17 comprising forming the first III-V sub-layer at a first temperature and forming the second III-V sub-layer at a second temperature, wherein the first temperature is greater than the second temperature.

19. The method according to claim 18 wherein the first temperature is 200-300 °C greater than the second temperature.

20. The method according to claim 17 comprising forming the first sub-layer and the second sub-layer at a first temperature.

21. The method according to claim 20 wherein the first temperature is less than 610 °C.

22. The method according to any of claims 17-21 comprising forming the first sub-layer using a first V/III ratio and forming the second sub-layer using a second V/III ratio.

23. The method according to claim 22 wherein the first V/III ratio is greater than the second V/III ratio.

24. The method according to any of claims 17-23 comprising growing the first sub-layer at a first growth rate and growing the second sub-layer at a second growth rate.

25. The method according to claim 24 wherein the second growth rate is greater than the first growth rate.