GB2641545A - DC power distribution and protection system - Google Patents

Abstract

A DC power distribution and protection system that comprises a DC power source 2, a power bus 3, 4 connecting the power source 2 with a load R or with a further power source 20, at least one capacitor CIN, C0 connected between a positive voltage rail 3 and a negative voltage rail 4 of the power bus, a solid state power controller 100 that comprises a first switching unit S1, S2, an auxiliary switching unit SA connected between the positive voltage rail 3 and the negative voltage rail 4, wherein the auxiliary switching unit SA is configured to connect the positive voltage rail 3 and the negative voltage rail 4 when switched on, and a controller 5 configured to receive information or determine when a power bus discharging condition is present. The controller 5 is further configured to control the first switching unit S1, S2 and the auxiliary switching unit SA to be switched on, wherein a discharge current from the capacitor flows through the first switching unit S1, S2 and the auxiliary switching unit SA to discharge the capacitor CIN, C0.

Description

[0001] DC POWER DISTRIBUTION AND PROTECTION SYSTEM

[0002] FIELD

[0003] The present disclosure relates a DC power distribution and protection system and a method for operating a DC power distribution and protection system in case a power bus discharging condition is present.

[0004] BACKGROUND

[0005] There is a growing trend towards electrification of conventional aircrafts with the aim of reducing carbon emissions. A corresponding increase in voltage and power levels of more electric aircraft (MEA) and all electric aircraft (AEA) requires fast and intelligent protection circuits. The protection circuits in DC electrical systems are critical for the reliability of the system. Due to the fact that SSPCs (Solid State Power Controllers, also referred to a Solid-State Protection Controllers) show a fast response time, eliminate arcing during turn-off, and have a higher reliability, SSPCs are preferred over electro-mechanical switches. SSPCs combine the functions of connecting loads to a DC bus bar and protecting electrical installations against overload and short circuits.

[0006] One problem that has to be addressed lies in that capacitive loads such as load capacitors are common in a MEA or AEA DC distribution system. When the DC distribution system is powered down, e.g., after having detected a fault, the situation is present that the capacitors in the system need to be discharged to prevent an electrical shock. Typically, this is done by adding a discharge resistor. However, it takes a long time such as 30 minutes to discharge the capacitors and deenergize the DC distribution system. Such long time is inconvenient and may produce safety hazards. For example, in applications like Urban Air Mobility a fast turnaround time and the isolation of high voltage is crucial for the safety of personal.

[0007] There is a need to provide a DC power distribution and protection system and a corresponding method that allow to discharge capacitors in the DC power distribution and protection system in a fast manner in case the system is powered down.

[0008] SUM MARY

[0009] In a first aspect a DC power distribution and protection system is provided. The system comprises a DC power source having a positive terminal and a negative terminal, a power bus connecting the power source with a load R or with a further power source, the power bus comprising a positive voltage rail 3 connected to the positive terminal and a negative voltage rail connected to the negative terminal, and at least one capacitor arranged between the positive voltage rail and the negative voltage rail. Further, a solid state power controller is arranged in the positive voltage rail or negative voltage rail, wherein the solid state power controller comprises a first switching unit. There is also provided an auxiliary switching unit arranged between the positive voltage rail and the negative voltage rail which is configured to connect the positive voltage rail and the negative voltage rail when switched on.

[0010] The DC power distribution and protection system further comprises a controller which is configured to receive information or determine when a power bus discharging condition is present. In such case, the controller is further configured to control the first switching unit and the auxiliary switching unit to be switched on, wherein a discharge current from the capacitor flows through the first switching unit and the auxiliary switching unit to discharge the capacitor.

[0011] Aspects of the invention are thus based on the idea to provide for an auxiliary switching unit which allows to discharge the at least one capacitor by providing a short-circuit current flow through the auxiliary switching unit even after powering down of the system. In this manner, the energized power bus of the DC power distribution and protection system can be discharged in a fast and controlled manner. The time it takes to deenergize the power bus is thus substantially reduced.

[0012] At the same time, aspects of the present invention rely on an SSPC to provide for the required switching of switching units in the power bus.

[0013] It is pointed out that in the auxiliary switching unit is only operated in case the DC system is powered down. Under normal conditions, is not operated.

[0014] The auxiliary switching unit may be considered part of the solid state power controller. Also, it may be controlled by a gate driver of the solid state power controller.

[0015] However, in principle, the auxiliary switching unit may be provided as a separate part of the circuit as well.

[0016] The present invention is not related to the specific reason of why a DC power distribution and protection system is powered down. Such powering down may be for many reasons, including disconnecting the power source after a fault has been detected (such as by means of a circuit breaker). If the system is powered down, a respective signal is received by the controller, and/or the controller determines a system power down by analysing data.

[0017] In some embodiments, the first switching unit of the solid state power controller comprises a plurality of semiconductor switches arranged in parallel, wherein the semiconductor switches of the first switching unit are controlled by the controller to be switched on when a power bus discharging condition is present. By paralleling a plurality of semiconductor switches, it is easier to meet the power requirements, wherein the number of parallel semiconductor switches is determined by the current requirements. Also, by paralleling a plurality of semiconductor switches the voltage drop over the switching unit is reduced.

[0018] In some embodiments, the auxiliary switching unit also comprises a plurality of auxiliary semiconductor switches arranged in parallel, wherein the semiconductor switches of the auxiliary switching unit are controlled by the controller to be switched on when a power bus discharging condition is present. The number of parallel semiconductor switches determines the amount of current which flows through a particular semiconductor switch when the at least one capacitor is discharged.

[0019] In some embodiments, the number of semiconductor switches in the auxiliary switching unit is lower than the number of semiconductor switches in the first switching unit. In some embodiments, the controller is configured to operate the auxiliary switching unit such that pre-determined pulses are applied to the auxiliary semiconductor switches. The pulses are applied to the control terminal of the semiconductor switch (such as the gate terminal in case of a MOSFET). By applying pulses, the auxiliary semiconductor switches are open to guide the discharge current of the at least one capacitor intermittently only. Thus, the amount of current that passes the auxiliary semiconductor switches can be controlled and a potential damage of an auxiliary switching device through the discharge current can be avoided.

[0020] In some embodiments, the controller is configured to control the auxiliary switching unit such that the auxiliary switching unit is shut off during normal operation of the system. As mentioned before, the auxiliary switching unit comes into play only in case that is the system is powered down.

[0021] Each semiconductor switch of a switching unit (of the first switching unit or the auxiliary switching unit) may be arranged in combination with an antiparallel diode. Such diodes give current that flows in the opposite direction a path to flow, thereby avoiding high voltage peaks eventually caused by inductive currents. In particular, the antiparallel diode supports a continued current flow during a short circuit and prevents change in the voltage direction.

[0022] In some embodiments, the controller is configured to control the first switching unit such that the semiconductor switches of the first switching unit are operated in active pulse control mode. In such a mode, the semiconductor switch is operated in an active region. As a semiconductor switch such as a MOSFET operates in the active region (also referred as linear or non-saturation region) at a lower gate voltage than when operating in a saturated region, the signal of the respective driver may have a lower voltage than otherwise. This allows the semiconductor switches to open for conducting the discharge current of the at least one capacitor, even when the at least one capacitor is not fully connected to a supply voltage.

[0023] So far, a DC power distribution and protection system has been considered in which the solid state power controller comprises a switching unit in the positive voltage rail or in the negative voltage rail. However, in embodiments, there may be provided a further switching unit in the same voltage rail. This allows for a bidirectional SSPC architecture that allows bidirectional control of the current flow between a DC power source and a load, while a single switching unit allows for unidirectional control of the current flow only. Within the context of the present invention, a bidirectional SSPC allows both the discharge of capacitors located at a power side of the system and of capacitors located at a load side of the system.

[0024] Accordingly, in some embodiments, the at least one capacitor comprises a first capacitor arranged at a power source side of the power bus and a second capacitor arranged at a load side of the power bus. Further, the solid state power controller further comprises a second switching unit arranged in the same voltage rail as the first switching unit, and wherein the auxiliary switching unit is arranged between the positive voltage rail and the negative voltage rail such that one terminal of the auxiliary switching unit is connected to a point between the first and second switching units (the common source point). With such a configuration, if a power bus discharging condition is present, the controller is configured to control the first and second switching units and the auxiliary switching unit such that the auxiliary switching unit and at least one of the first and second switching units are switched on.

[0025] Such embodiment allows to address the situation in which a bidirectional SSPC may be connected to two energized buses or bus regions (one towards the power source side and one towards the load side, each with a capacitor), wherein after shutting down of the system the buses are still energized due to the presence of the capacitors, and wherein both bus regions may need to be deenergized. Using a bidirectional SSPC, different scenarios for discharging the capacitors can be implemented.

[0026] More particularly, in a first variant, the controller is configured to control the first and second switching units and the auxiliary switching unit such that the first and second switching units and the auxiliary switching unit are switched on concurrently, wherein a discharge current from the first capacitor flows through the first switching unit and the auxiliary switching unit, and the same time a discharge current from the second capacitor flows through the second switching unit and the auxiliary switching unit. In this embodiment, the bidirectional SSPC is used to allow discharging a capacitor at the power side and discharging of a capacitor at the load side at the same time.

[0027] For implementation of such embodiment, it may be provided that the semiconductor switches of the first and second switching units are controlled by a single gate driver, which turns all semiconductor switches of the first and second switching units on at the same time, thereby providing (together with the auxiliary semiconductor switches of the auxiliary switching unit) at the same time a current path for the capacitor at the power source side and the capacitor at the load side.

[0028] In a second variant, the controller is configured to control the first and second switching units and the auxiliary switching unit such that alternately both the first switching unit and the auxiliary switching unit and both the second switching unit and the auxiliary switching unit are switched on, wherein a discharge current flows alternately from the first capacitor through the first switching unit and the auxiliary switching unit and from the second capacitor through the second switching unit and the auxiliary switching unit. In this embodiment, it is avoided that both capacitors are discharged at the same time, thereby reducing the current flowing through the auxiliary switching unit. At the same time, it is still provided that both capacitors are discharged in an expedited manner.

[0029] In a third variant, the controller is configured to control the first and second switching units and the auxiliary switching unit such that the first or second switching unit and the auxiliary switching unit are switched on, wherein the respective other switching unit is switched off, and wherein either a discharge current from the first capacitor flows through the first switching unit and the auxiliary switching unit or a discharge current from the second capacitor flows through the second switching unit and the auxiliary switching unit. In the second and third variant, it may be provided that the semiconductor switches of the first switching unit are controlled by a first gate driver and that semiconductor switches of the second switching unit are controlled by a second gate driver. Thereby, the first and second switching units may be switched independently and differently.

[0030] In some embodiments, one or several transient voltage suppressor diodes are arranged between the positive voltage rail and the negative voltage rail. Their purpose is to suppress transient voltage spikes.

[0031] The semiconductor switches may be implemented as MOSFET, IGBT, GaN or SiC transistors in embodiments. The gate of such semiconductor switch is the control terminal to which a driver signal of the SSPC driver is applied.

[0032] In a second aspect a method for operating a DC power distribution and protection system in case a power bus discharging condition is present is provided. The DC power system in which the method is carried out comprises a DC power source having a positive terminal and a negative terminal, a power bus connecting the power source with a load or with a further power source, the power bus comprising a positive voltage rail connected to the positive terminal and a negative voltage rail connected to the negative terminal, at least one capacitor connected between the positive voltage rail and the negative voltage rail, a solid state power controller arranged in the positive voltage rail or negative voltage rail, wherein the solid state power controller comprises a first switching unit, and an auxiliary switching unit connected between the positive voltage rail and the negative voltage rail.

[0033] The method comprises: determine if a power bus discharging condition is present; and in such case switch on the first switching unit and the auxiliary switching unit such that a discharge current from the capacitor flows through the first switching unit and the auxiliary switching unit to discharge the capacitor.

[0034] The method allows to quickly discharge a capacitor in an energized power bus in case the system is powered down.

[0035] Embodiments of the method correspond to those of the system discussed above as identified in the appended claims.

[0036] The skilled person will appreciate that except where mutually exclusive, a feature or parameter described in relation to any one of the above aspects may be applied to any other aspect. Furthermore, except where mutually exclusive, any feature or parameter described herein may be applied to any aspect and/or combined with any other feature or parameter described herein.

[0037] BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The invention will be explained in more detail on the basis of exemplary embodiments with reference to the accompanying drawings in which: FIG. 1 is an embodiment of a DC power distribution and protection system that implements a unidirectional SSPC, wherein by means of an auxiliary switching unit a capacitor can be discharged in a quick manner in case a power bus discharging condition is present; FIG. 2 is a flowchart of a method allowing discharge of a capacitor in a DC power distribution and protection system in a quick manner in case a power bus discharging condition is present; FIG. 3 is an embodiment of a DC power distribution and protection system that implements a bidirectional SSPC, wherein by means of an auxiliary switching unit both a power source side capacitor and a load side capacitor can be discharged in a quick manner in case a power bus discharging condition is present; FIG. 4 is the of a DC power distribution and protection system of FIG. 3 indicating the current flow according to a first scenario; FIG. 5 is a flowchart of a more detailed method for discharging a capacitor in the scenario of FIG. 4; FIG. 6 is the of a DC power distribution and protection system of FIG. 3 indicating the current flow according to a second scenario; FIG. 7 is a flowchart of a more detailed method for discharging a capacitor in the scenario of FIG. 6; FIG. 8 is a flowchart of a variant method in the scenario of FIG. 6; FIG. 9 is the of a DC power distribution and protection system of FIG. 3 indicating the current flow according to a third scenario; FIG. 10 is the of a DC power distribution and protection system of FIG. 3 indicating the current flow according to a fourth scenario; and FIG. 11 is a flowchart of a more detailed method for discharging a capacitor in the scenarios of FIGS. 9 and 10.

[0039] DETAILED DESCRIPTION

[0040] Before discussing embodiments of the present invention, the general background of the present invention is first shortly presented. With increased penetration of electrical systems and the progression towards full electric and hybrid propulsion systems, the use DC power distribution and protection systems has gained increased use. In such systems, multiple loads and sources may be connected through a power bus which may comprise multiple lanes. For example, there may be provided DC power distribution and protection systems which comprise a plurality of input power sources such as sources fed from a turbo generator/active rectifier and sources from energy storage systems. Such systems may also comprise a plurality of output loads such as power inverters providing power to propulsion motors and/or the respective motors. All the sources and loads may be connected to a multi SSPC controller unit which comprises SSPC units that provide protection functions for each individual lane.

[0041] Such systems may be connected with sources and loads which have significant capacitors such as DC-link capacitors in power converters which, upon power down of the system, need to be discharged to prevent any electrical shock. Typically, this is done by adding a discharge resistor. However, it takes a considerable time such as 30 minutes to discharge. Before this background, the present invention regards a DC power distribution and protection system that allows to discharge a capacitor in an energized power bus in a fast and efficient manner.

[0042] A first embodiment of the invention is depicted in FIG. 1. FIG. 1 shows a DC power distribution and protection system that comprises a unidirectional solid state power controller 100, in the following referred to as SSPC. The system comprises a DC power source 2 (such as a DC battery) that has a positive terminal 21 and a negative terminal 22. Between the positive terminal 21 and the negative terminal 22 a battery voltage VDC is present. A positive voltage rail 3 is connected to the positive terminal 21 and a negative voltage rail 4 is connected to the negative terminal 22. The positive voltage rail 3 and the negative voltage rail 4 form a high-voltage bus, also referred to as a power bus in the following.

[0043] The system further comprises a load Ro, wherein the load Ro may be formed in a plurality of manners. In examples, the load may be a power converter such as an inverter and/or an electric motor. A capacitive load generally depicted as capacitor Co is arranged at a load side 32 of the high-voltage bus in parallel to the load R and extends between the positive voltage rail 3 and the negative voltage rail 4. For example, the capacitive load may be formed by DC link capacitors or include such capacitors.

[0044] Further, and input capacitor ON may be arranged at a power source side 31 of the high-voltage bus between the positive voltage rail 3 and the negative voltage rail 4. Also, several inductances L1-L4 are provided, wherein inductances L1, L2 are arranged in the positive voltage rail 3 and inductances L3, L4 are arranged in the negative voltage rail 4.

[0045] The the inductances L1, L2 are configured to limit the rate of rise of current in case of a short-circuit fault.

[0046] The SSPC 100 comprises a switching unit S1 which comprises of a plurality of semiconductor switches S11-S15 which are arranged in parallel. By paralleling a plurality of semiconductor switches S11-S15 in the switching unit S1, current capacity can be increased and/or voltage drop and power loss can be reduced. Each of the semiconductor switches S11-S15 comprises a transistor and an antiparallel bypass diode. The antiparallel diodes give current that flows in the opposite direction a path to flow. Without the diodes, inductive currents would cease instantly, generating high voltage peaks.

[0047] The SSPC 100 further comprises a gate driver 111 for the semiconductor switches S11-S15 of the switching units S1 which is schematically depicted. In another embodiment, there may be provided individual gate drivers for the individual semiconductor switches S11-515, S21-S25. The gate drivers may be commercially available off-the-shelf gate drivers in embodiments. The SSPC 100 may further comprise a microcontroller (not shown) for logic control.

[0048] The semiconductor switches may be implemented as MOSFET, IGBT, GaN or SiC transistors in embodiments. The gate of such semiconductor switch is the control terminal to which the driver signal of the SSPC driver is applied.

[0049] It is pointed out that a switching unit of SSPC 100 may additionally or alternatively be implemented in the negative voltage rail 4.

[0050] It is further pointed out that the number of five parallel semiconductor switches in the switching unit S1 is to be understood as an example only. The number of parallel devices is determined by the current requirements of the SSPC 100.

[0051] DC power distribution and protection system further comprises an auxiliary switching unit SA which is arranged between the positive voltage rail 3 and the negative voltage rail 4. In the depicted embodiment, the auxiliary switching unit SA comprises two parallel semiconductor switches SA1, SA2, but this is to be understood as an example only.

[0052] Alternatively, there may be a single semiconductor switch or more than two semiconductor switches. Each semiconductor switch SA1, SA2 comprises a transistor (such as MOSFET, IGBT, GaN or SiC transistors) and an antiparallel bypass diode. A gate driver 120 is provided which drives the gates of the semiconductor switches SA1, SA2. The gate driver 120 is depicted schematically only.

[0053] There are also arranged two transient voltage suppressor diodes TVS between the positive voltage rail 3 and the negative voltage rail 4, one at the power source side of the auxiliary switching unit SA and one at the load side of the auxiliary switching unit SA, which however is optional. Such transient voltage suppressor diodes are designed to clamp transient voltages.

[0054] Further, a controller 5 is provided which is depicted schematically. The controller 5 is configured control the function of the gate drivers 111, 120 and provides control signals to the gate drivers 111, 120 through output lines 52. The receiver is further configured to receive input information through input lines 51. Such input information includes information when a discharging condition of the power bus is present. Such information may be provided by a circuit breaker or through a higher control instance.

[0055] The controller 5 may comprise a processor for executing instructions and a memory which is coupled to the processor and in which instructions are stored which, when executed by the processor, cause the processor to perform said functions of controlling the switching units and the auxiliary switching unit to provide for a discharge current for the capacitor. The controller 5 may be a separate unit or may be integrated into a gate driver or a microcontroller of the SSPC 100. Also, the controller 5 may communicate with other control devices of the system.

[0056] In case a power bus discharging condition is received or otherwise determined by controller 5, the controller 5 is configured to control the switching unit S1 and the auxiliary switching unit SA such all semiconductor switches S11-S15 of switching unit S1 and all auxiliary semiconductor switches SA1, SA2 of auxiliary switching unit SA are switched on. To achieve this, the controller 5 provides respective control signals through output lines 52 to the gate drivers 111, 120. Thereby, a discharge current from capacitor Cm, flows through the switching unit S1 and the auxiliary switching unit to discharge the capacitor ON.

[0057] FIG. 2 is a flowchart of a method for operating a DC power distribution and protection system, such as the DC power distribution and protection system of FIG. 1. In step 201, it is determined if a power bus discharging condition is present. A corresponding signal may be received by controller 5 of FIG. 1.

[0058] If this is the case, in step 202, the (first) SSPC switching unit and the auxiliary switching unit SA are switched on, meaning that the respective semiconductor switches 511-S15, SA1, SA2 are switched on. Finally, in step 203, a discharge current is guided from a capacitor through the first switching unit and the auxiliary switching unit to discharge the capacitor. Accordingly, the first switching unit and the auxiliary switching unit work together in providing for a fast discharging of the capacitor, wherein the auxiliary switching unit that is connected between the positive voltage rail and the negative voltage rail provides for a short circuit for the capacitor current (there is no short circuit current with respect to the power source, as the system has been shut down).

[0059] FIG. 3 shows a DC power distribution and protection system that is similar to DC power distribution and protection system of FIG. 1 except that the SSPC 100 located in the positive voltage rail 3 is a bidirectional SSPC 100 and thus able to isolate voltage rail 3 in both directions.

[0060] More particularly, the solid state power controller 100 comprises a first switching unit S1 and a second switching unit S2, wherein each of the switching units 51, S2 comprises a plurality of semiconductor switches S11-515, S21-S25 arranged in parallel. The semiconductor switches of the two switching units S1, S2 are controlled by a single gate driver 112. Alternatively, two individual gate drivers for the two switching units S1, S2 are provided.

[0061] The auxiliary switching unit SA is arranged such that it is connected with one terminal to the negative voltage rail 4 and with another other terminal to the positive voltage rail 3, wherein the connection to the positive voltage rail 3 is such that the connection is at a point 35 between the first and second switching units S1, S2. This connection point 35 corresponds to the common source point. Thereby, current is guided through the switching unit S1 and through the switching unit S2 at the same time also flows through auxiliary switching unit SA.

[0062] This is further discussed with respect to FIG. 4, which is identical to FIG. 3 except that energized buses 33, 34 are indicated at both ends of the power bus and that the current flow is indicated. The energized buses 33, 34 indicate the situation that after shutdown of the system the buses are still energized due to the presence of the capacitors ON, Co at both side 31, 32. For ease of depiction, gate driver 112 is not shown in FIG. 4. Otherwise, reference is made to the description of FIG. 3.

[0063] FIG. 4 depicts a scenario in which the controller 5 controls (through gate driver 112, see FIG. 3) both switching units S1, S2 and also the auxiliary switching unit S2 to be switched on concurrently when the controller 5 receives information that a power bus discharging condition is present. Such power bus discharging condition may be signalled to controller 5 through one of its input lines 51. Such signal may be received from a circuit breaker (not shown) or a higher control instance.

[0064] Accordingly, the semiconductor switches S11-S15, S21-S25 of semiconductor units S1, S2 are switched on and the auxiliary semiconductor switches SA1, SA2 of auxiliary switching unit SA are switched on concurrently. A discharge current flows from capacitor ON located at the power source side 31 of the system through L1, the semiconductor switches S11-S15, the auxiliary semiconductor switches SA1, SA2 and L3 for discharging capacitor Cut At the same time, a discharge current flows from capacitor Co located at the load side 33 of the system through L2, the semiconductor switches S21-S25, the auxiliary semiconductor switches SA1, SA2 and L4 for discharging capacitor Co. Accordingly, in the embodiment of FIG. 4, both the power source side 31 and the load side 32 of the power bus are discharged at the same time by controlling S1, S2 and SA accordingly, wherein S1, S2 are controlled together by a single gate driver 112.

[0065] While executing the discharging process, auxiliary switching unit SA may be kept continuously in the ON state. Alternatively, a pulsed signal may be applied to the gates of the auxiliary semiconductor switches SA1, SA2 to control the current flow through the auxiliary switching unit SA.

[0066] It is further pointed out that the first switching unit S1 and the second switching unit S2 are both switched in the active pulse control mode. Accordingly, the semiconductor switches S11-S15, S21-S25 are operated in an active region. With such operation, a lower gate voltage is needed than when operated in a saturated region of the semiconductor switches. In particular, in case a MOSFET is operated in the active region, a large amount of power is dissipated, this helping to speed up the discharging process. At the same time, the power loss in the auxiliary semiconductor switches SA1, SA2 may be smaller such that an additional heat sink for the auxiliary switching unit SA may not be required.

[0067] It is pointed out that switching the switching units of the SSPC 100 with active pulse control may be implemented in all embodiments, including the embodiment of FIG. 1 discussed above and the embodiment of FIGS. 6, 9 and 10 discussed below.

[0068] FIG. 5 is a flowchart of a method for operating a DC power distribution and protection system in accordance with the scenario of FIG. 4. Start 501 is triggered by the controller receiving a signal indicating that a power bus discharging condition is present. In such case, it is checked in step 502 if the energized network shall be discharged on both sides of the power bus (discharge of both energized buses 33, 34 in FIG. 4). In such case, switching units S1, S2 are operated together an active pulse control mode, step 503.

[0069] Subsequently, the auxiliary semiconductor switches SA1, SA2 are turned on in step 504. Wth the auxiliary semiconductor switches SA1, SA2 turned on, both capacitors at the power source side and capacitors at the load side of the power bus can discharge concurrently through the auxiliary semiconductor switches SA1, SA2. The process continues until it is decided in step 505 that the discharge of the capacitors has been done. In such case, the auxiliary semiconductor switches SA1, SA2 and the semiconductor switches S11-15, S21-25 of switching units S1, S2 are turned/switched off in step 506. The process ends at step 507. The auxiliary semiconductor switches SA1, SA2 remain switched off during normal operation of the system.

[0070] A further scenario is depicted in FIG. 6, which is identical to FIG. 3 except that energized buses 33, 34 are indicated at both ends of the power bus, in that the two switching units S1, S2 are controlled by individual gate drivers 113, 114, and in that that the current flow is indicated. The energized buses 33, 34 indicate the situation that after shutdown of the system the buses are still energized due to the presence of the capacitors Coq, Co in both buses.

[0071] FIG. 6 depicts a scenario that the controller 5 (through gate drivers 113, 114) controls the switching units S1, S2 and the auxiliary switching unit SA such that, when the controller receives information that a power bus discharging condition is present, alternately both the first switching unit S1 and the auxiliary switching unit SA are switched on (while S2 is switched off), and both the second switching unit S2 and the auxiliary switching unit SA are switched on (while S1 is switched off). This allows that a discharge current flows either from the first capacitor Ciry through the first switching unit S1 and the auxiliary switching unit SA or from the second capacitor Co through the second switching unit S2 and the auxiliary switching unit SA, wherein these discharge currents are alternated. The scenario of FIG. 6 (compared to the scenario of FIG. 4) reduces the pulse current in the auxiliary semiconductor switches SA1, SA2 as the current is coming only from one side of the power bus. It is pointed out that in FIG. 6 all semiconductor switches of switching unit S1 are turned on together while at the same time the semiconductor switches of switching unit S2 are turned off, and vice versa. The period of time that switching units S1 and S2 are switched on or off can be controlled through gate drivers 113, 114 by controlling the active pulse duration of the respective semiconductor switches (wherein the gate drivers 113, 114 may be controlled by controller 5).

[0072] FIG. 7 is a flowchart of a method for operating a DC power distribution and protection system in accordance with the scenario of FIG. 6. Start 701 is triggered by the controller receiving a signal indicating that a power bus discharging condition is present. In such case, it is checked in step 702 if the system wants to discharge the energized network on both sides of the power bus (discharge of both energized buses 33, 34 in FIG. 6). If this is the case, switching units S1 and S2 are operated in complementary mode, i.e., when switching unit S1 is on, switching unit S2 is off, and vice versa. In step 704, the auxiliary switches SA1, SA2 are turned on. Accordingly, both capacitors at the power source side and capacitors at the load side of the power bus can discharge through the auxiliary semiconductor switches SA1, SA2, wherein at a given point in time the discharge current of only one of the capacitors flows through the semiconductor switches SA1, SA2. In step 705, it is checked if the discharge has been done. If this is the case, the auxiliary semiconductor switches SA1, SA2 and the semiconductor switches S11-15, S21-25 of switching units S1, S2 are turned/switched off in step 706. The process ends at step 707. The auxiliary semiconductor switches SA1, SA2 remain switched off during normal operation of the system.

[0073] FIG. 8 depicts a method which represents an embodiment of the method of FIG. 7, wherein the embodiment regards controlling the pulses provided by gate driver 120 to the auxiliary semiconductor switches SA1, SA2. The method servers to determine the pulse duration based on the maximum discharge current that is allowed to flow through the auxiliary semiconductor switches SA1, SA2 and based on how fast the system wants to discharge the energized network. The procedure starts at step 801. In step 802, an input duration between 1 and 10 microseconds is decided upon based on the device manufacturing sheet and the operating conditions of the system. In step 803, it is checked what the maximum discharge current is that is allowed to flow through the auxiliary semiconductor switches SA1, SA2 and how fast the system wants to discharge in the energized network. In step 804, the auxiliary semiconductor switches SA1, SA2 are turned on by applying a pulse signal with a pulse width from 1 to 10 microseconds, the pulsed signal being applied by gate driver 120. In step 805, switching units S1 and S2 are operated in complementary mode, i.e., when switching unit S1 is on, switching unit S2 is off, and vice versa. In step 806, it is checked if the discharge has been done. If this is the case, the auxiliary semiconductor switches SA1, SA2 are turned off (as well as the semiconductor switches S11-15, S21-25 of switching units S1, S2, step 807. The process ends at step 808.

[0074] Two further, related scenarios are depicted in FIGS. 9 and 10, which are identical to FIG. 3 except that in FIG. 9 an energized bus 33 is present on one side 31 of the power bus only, wherein a DC power source 20 is present at the other side 32 of the power bus, and except that in FIG. 10 an energized bus 34 is present on the other side 32 of the power bus only, wherein a DC power source 2 is present at the one side 31. Accordingly, in FIG. 9, in case a power bus discharging condition is present, capacitor Cm, needs to be discharged only, and in FIG. 10, in case a power bus discharging condition is present, capacitor Co needs to be discharged only. It is pointed out that in FIGS. 9 and 10 for ease of depiction the gate drivers and the controller are not shown.

[0075] The scenarios of FIGS. 9 and 10 regard an embodiment that allows selective power bus discharging. There is the option to discharge either the side 31 with energized bus 33 (FIG. 9) or the side 32 with energized bus 34 (FIG. 10). Accordingly, either the semiconductor switches S11-S15 of switching unit S1 are switched on, wherein the semiconductor switches S21-S25 of switching unit S2 are switched off during the complete discharge process, FIG. 9, or the semiconductor switches S21-325 of switching unit S2 are switched on, wherein the semiconductor switches S11-315 of switching unit S1 are switched off during the complete discharge process, FIG. 10.

[0076] FIG. 11 shows the corresponding process. The process starts in step 1101. In step 1102, it is checked which side of the power buses shall be discharged (side 31 or side 32).

[0077] If the energized network is on side 31 (which may also be termed the positive DC bus), step 1103, the semiconductor switches S11-S15 of switching unit S1 are switched on (high) during the complete discharge, step 1104, the semiconductor switches S21-S25 of switching unit S2 are switched off (low) during the complete discharge, step 1105, and the auxiliary semiconductor switches SA1, SA2, are switched on, step 1106. In step 1107, it is checked if the discharge has been completed. If this is the case, the auxiliary semiconductor switches are switched off in step 1108. The process is then ends in step 1109.

[0078] On the other hand, if it is decided in step 1103 that the energized network is not on side 31, the process continues to step 1110, wherein it is checked if a DC link capacitor (capacitor Co) is present on side 31 of the power bus (which may also be termed as the negative DC bus). If this is the case the semiconductor switches S21-S25 of switching unit S2 are switched on (high) during the complete discharge, step 1111, the semiconductor switches S11-S15 of switching unit S1 are switched off (low) during the complete discharge, step 1112, and the auxiliary semiconductor switches SA1, SA2, are switched on, step 1113.

[0079] In step 1114, it is checked if the discharge has been completed. If this is the case, the auxiliary semiconductor switches are switched off in step 1115. The process is then ends in step 1116.

[0080] It should be understood that the above description is intended for illustrative purposes only, and is not intended to limit the scope of the present disclosure in any way.

[0081] Also, those skilled in the art will appreciate that other aspects of the disclosure can be obtained from a study of the drawings, the disclosure and the appended claims. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. Various features of the various embodiments disclosed herein can be combined in different combinations to create new embodiments within the scope of the present disclosure. In particular, the disclosure extends to and includes all combinations and sub-combinations of one or more features described herein.

[0082] Any ranges given herein include any and all specific values within the range and any and all sub-ranges within the given range.

Claims (20)

1. CLAIMS1. A DC power distribution and protection system comprising: a DC power source (2) having a positive terminal (21) and a negative terminal (22); a power bus (3, 4) connecting the power source (2) with a load (Ro) or with a further power source (20), the power bus comprising a positive voltage rail (3) connected to the positive terminal (21) and a negative voltage rail (4) connected to the negative terminal (22); at least one capacitor (Cu% Co) connected between the positive voltage rail (3) and the negative voltage rail (4); a solid state power controller (100) arranged in the positive voltage rail (3) or negative voltage rail (4), wherein the solid state power controller (100) comprises a first switching unit (S1, S2); an auxiliary switching unit (SA) connected between the positive voltage rail (3) and the negative voltage rail (4), wherein the auxiliary switching unit (SA) is configured to connect the positive voltage rail (3) and the negative voltage rail (4) when switched on; and a controller (5) configured to receive information or determine when a power bus discharging condition is present; wherein, in such case, the controller (5) is further configured to control the first switching unit (S1, S2) and the auxiliary switching unit (SA) to be switched on, wherein a discharge current from the capacitor (CIN, Co) flows through the first switching unit (S1, S2) and the auxiliary switching unit (SA) to discharge the capacitor (Cm, Co).

2. The system of claim 1, wherein the first switching unit (S1, S2) of the solid state power controller (100) comprises a plurality of semiconductor switches (S11-S15, S21-S25) arranged in parallel, wherein the semiconductor switches (S11-S15, S21-S25) of the first switching unit (S1, S2) are controlled by the controller (5) to be switched on when a power bus discharging condition is present.

3. The system of claim 1 or 2, wherein the auxiliary switching unit (SA) comprises a plurality of auxiliary semiconductor switches (SA1, SA2) arranged in parallel, wherein the semiconductor switches (SA1, SA2) of the auxiliary switching unit (SA) are controlled by the controller (5) to be switched on when a power bus discharging condition is present.

4. The system of claim 3, wherein the controller (5) is configured to operate the auxiliary switching unit (SA) such that pre-determined pulses are applied to the auxiliary semiconductor switches (SA1, SA2).

5. The system of any preceding claim, wherein the controller (5) is configured to control the auxiliary switching unit (SA) such that the auxiliary switching unit (SA) is shut off during normal operation of the system.

6. The system of any preceding claim, when dependant on claim 2 or 3, wherein each semiconductor switch (S11-S15, S21-S25, SA1, SA2) is arranged in combination with an antiparallel diode.

7. The system of any preceding claim, when dependant on claim 2, wherein the controller (5) is configured to control the first switching unit (SA1, SA2) such that the semiconductor switches (511-S15, 521-525) of the first switching unit (SA1, SA2) are operated in active pulse control mode.

8. The system of any preceding claim, wherein: the at least one capacitor comprises a first capacitor (Cm]) arranged at a power source side (31) of the power bus and a second capacitor (Co) arranged at a load side (32) of the power bus; the solid state power controller (5) further comprises a second switching unit (S2, S1) arranged in the same voltage rail (3, 4) as the first switching unit (S1, S2); the auxiliary switching unit (SA) is arranged between the positive voltage rail (3) and the negative voltage rail (4) such that one terminal of the auxiliary switching unit (SA) is connected to a point (35) between the first and second switching units (S1, S2); and if a power bus discharging condition is present, the controller (5) is configured to control the first and second switching units (S1, S2) and the auxiliary switching unit (SA) such that the auxiliary switching unit (SA) and at least one of the first and second switching units (S1, S2) are switched on.

9. The system of claim 8, wherein the controller (5) is configured to control the first and second switching units (S1, S2) and the auxiliary switching unit (SA) such that the first and second switching units (S1, S2) and the auxiliary switching unit (SA) are switched on concurrently, wherein a discharge current from the first capacitor (CiN) flows through the first switching unit (S1) and the auxiliary switching unit (SA), and at the same time a discharge current from the second capacitor (Co) flows through the second switching unit (S2) and the auxiliary switching unit (SA).

10. The system of claim 9, wherein the semiconductor switches (311-S15, S21-S25) of the first and second switching units (S1, S2) are controlled by a single gate driver (111).

11. 11 The system of claim 8, wherein the controller (5) is configured to control the first and second switching units (S1, S2) and the auxiliary switching unit (SA) such that alternately both the first switching unit (S1) and the auxiliary switching unit (SA) and both the second switching unit (S2) and the auxiliary switching unit (SA) are switched on, wherein a discharge current flows alternately from the first capacitor (CIN) through the first switching unit (S1) and the auxiliary switching unit (SA) and from the second capacitor (Co) through the second switching unit (S2) and the auxiliary switching unit (SA).

12. The system of claim 8, wherein the controller (5) is configured to control the first and second switching units (S1, S2) and the auxiliary switching unit (SA) such that the first or second switching unit (S1, S2) and the auxiliary switching unit (SA) are switched on, wherein the respective other switching unit (S2, S1) is switched off, and wherein either a discharge current from the first capacitor (CIO flows through the first switching unit (S1) and the auxiliary switching unit (SA) or a discharge current from the second capacitor (Co) flows through the second switching unit (S2) and the auxiliary switching unit (SA).

13. The system of any precedin claims, when dependant on claim 2 or 3, wherein the semiconductor switches (S11-S15, S21-S25, SA1, SA2) are MOSFET, IGBT, GaN or SiC transistors.

14. A method for operating a DC power distribution and protection system in case a power bus discharging condition is present, wherein the DC power distribution and protection system comprises: a DC power source (2) having a positive terminal (21) and a negative terminal (22); a power bus (3, 4) connecting the power source (2) with a load (Ro) or with a further power source (20), the power bus comprising a positive voltage rail (3) connected to the positive terminal (21) and a negative voltage rail (4) connected to the negative terminal (22); at least one capacitor (CIN, Co) connected between the positive voltage rail (3) and the negative voltage rail (4); a solid state power controller (100) arranged in the positive voltage rail (3) or negative voltage rail (4), wherein the solid state power controller (100) comprises a first switching unit (S1, S2); and an auxiliary switching unit (SA) connected between the positive voltage rail (3) and the negative voltage rail (4), wherein the auxiliary switching unit (SA) is configured to connect the positive voltage rail (3) and the negative voltage rail (4) when switched on; the method comprising the steps of: determining (201) if a power bus discharging condition is present; and in such case switching on (202) the first switching unit (S1, S2) and the auxiliary switching unit (SA) such that a discharge current from the capacitor (CIN, Co) flows (203) through the first switching unit (S1, S2) and the auxiliary switching unit (SA) to discharge the capacitor (CiN, Co)

15. The method of claim 14, wherein the at least one capacitor (CIN, Co) comprises a first capacitor (Cm) arranged at a power source side (31) of the power bus and a second capacitor (Co) arranged at a load side (32) of the power bus, and in that the solid state power controller (5) further comprises a second switching unit (S2, S1) arranged in the same voltage rail (3, 4) as the first switching unit (S1, S2), wherein the method further comprises switching on the auxiliary switching unit (SA) and at least one of the first and second switching units (51, S2).

16. The method of claim 15, wherein the first and second switching units (S1, S2) and the auxiliary switching unit (SA) are switched on concurrently, such that a discharge current from the first capacitor (CIN) flows through the first switching unit (S1) and the auxiliary switching unit (SA), and the same time a discharge current flow from the second capacitor (Co) flows through the second switching unit (S2) and the auxiliary switching unit (SA).

17. The method of claim 15, wherein alternately both the first switching unit (S1) and the auxiliary switching unit (SA) and both the second switching unit (S2) and the auxiliary switching unit (SA) are switched on, such that a discharge current flows alternately from the first capacitor (CIN) through the first switching unit (S1) and the auxiliary switching unit (SA) and from the second capacitor (Co) through the second switching unit (S2) and the auxiliary switching unit (SA).

18. The method of claim 15, wherein the first or second switching unit (S1, S2) and the auxiliary switching unit (SA) are switched on, wherein the respective other switching unit (S2, S1) is switched off, and wherein either a discharge current from the first capacitor (Cm]) flows through the first switching unit (S1) and the auxiliary switching unit (SA) or a discharge current from the second capacitor (Co) flows through the second switching unit (S2) and the auxiliary switching unit (SA).

19. The method of any one of claims 14 to 18, wherein the auxiliary switching unit (SA) is operated by applying a pre-determined continuous stream of pulses when a power bus discharging condition is present.

20. The method of any one of claims 14 to 19, wherein the first and second switching units (S1, S2) each comprise a plurality of semiconductor switches (S11-S15, S21-S25) arranged in parallel, wherein the method further comprises that the semiconductor switches (511-S15, S21-S25) of the first and/or second switching unit (S1, S2) are operated in active pulse control mode when a power bus discharging condition is present.