GB2640859A - A method of precharging a capacitor in a power distribution and protection system - Google Patents

Abstract

A method of precharging a capacitor (Cload) in a power distribution and protection system that comprises a solid state power controller (100), wherein the solid state power controller (100) comprises at least one semiconductor switch (S1, S2), a gate driver (110), a desaturation detection circuit (140), and biasing means (120) which, when enabled, bias the at least one semiconductor switch (S1, S2) to be operated in the active region. The method comprises: applying during a first time interval, PWM pulses of a first defined duty cycle to the control terminal of the at least one semiconductor switch (S1, S2) to precharge the capacitor (Cload) while the desaturation detection circuit (140) is disabled and the biasing means (120) are enabled; in a second, subsequent time interval, disable the biasing means (120) and enable the desaturation detection circuit (140), and apply at least one pulse with a second defined duty cycle to the control terminal, determine if a short-circuit is present by the desaturation detection circuit (140) during the second time interval; if so, discontinue (604) precharging the capacitor (Cload); if not, enable the biasing means (120) and disable the desaturation detection circuit (140) again, and apply during a third time interval PWM pulses of a third defined duty cycle to the control terminal to continue precharging of the capacitor (Cload).

Description

A METHOD OF PRECHARGING A CAPACITOR IN A POWER DISTRIBUTION AND PROTECTION SYSTEM

FIELD

The present disclosure relates a method of precharging a capacitor in a power distribution and protection system and a corresponding power distribution and protection system.

BACKGROUND

With increased penetration of electrical systems and the progression towards full electric and hybrid propulsion systems, the use of energy storage systems and DC power distribution has gained increased use. Multiple loads and sources may be connected to a DC distribution system such as a hybrid propulsion system. In such system, adequate DC protection devices are required. Due to the fad that SSPCs (Solid State Power Controllers, also referred to a Solid State Circuit Breakers) show a fast response time, eliminate arcing during turn-off, and have a high reliability, SSPCs are preferred over electro-mechanical switches. SSPCs combine the functions of connecting loads to a DC bus bars and protecting electrical installations against overload and short circuits.

Another feature of SSPCs is capacitor precharge control. Capacitor precharge is an important phase of a power converter start-up as it prevents large inrush current flowing to capacitive loads associated with the power converter. For capacitor precharge control a solid-state semiconductor device may be operated in the active region to limit the current flowing to the capacitor during start-up. However, when the device is operated in the active region, a significantly large voltage drop is present that may trigger a desaturation detection even when the current is within normal range and not indicative of a short-circuit fault. On the other hand, disabling the desaturation detection circuit during precharge may lead to a situation in which the SSPC is charging an already short-circuited faulty capacitor, causing the devices to heat up and leading to failure of the SSPC.

There is a need to provide a method of precharging a capacitor in a DC power distribution and protection system that, on the one hand, avoids a faulty triggering of desaturation detection responses, and, on the other hand, secures protection during the precharge sequence.

SUM MARY

According to an aspect of the invention, a method of precharging a capacitor in a power distribution and protection system is provided. The power distribution and protection system in which the method is implemented comprises a solid state power controller which controls precharging of the capacitor, wherein the solid state power controller comprises at least one semiconductor switch, a gate driver configured to generate a driver signal of PWM pulses which is applied to a control terminal of the at least one semiconductor switch, a desaturation detection circuit, and biasing means which, when enabled, bias the at least one semiconductor switch to be operated in the active region. The method comprises: applying, during a first time interval, PWM pulses (PWM = Pulse Width Modulated) of a first defined duty cycle D1 to the control terminal of the at least one semiconductor switch to precharge the capacitor while the desaturation detection circuit is disabled and the biasing means are enabled; in a second, subsequent time interval, disabling the biasing means and enabling the desaturation detection circuit, and applying at least one pulse with a second defined duty cycle D2 to the control terminal of the at least one semiconductor switch; determining if a short-circuit is present by the desaturation detection circuit during the second time interval; if so, discontinuing precharging the capacitor; and if not, enabling the biasing means and disabling the desaturation detection circuit again, and applying during a third time interval PWM pulses of a third defined duty cycle D3 to the control terminal of the at least one semiconductor switch to continue precharging of the capacitor.

Aspects of the invention are thus based on the idea to provide for a precharging method that allows to carry out desaturation fault detection during precharge with active pulse gate control, wherein, however, the desaturation fault detection takes place during the second time interval only, while the desaturation detection circuit is disabled during the first time interval and the third time interval. Thus, a precharging sequence is provided in which the precharging of the at least one semiconductor switch is interrupted in the second time interval to allow the desaturation detection circuit to determine if a short-circuit is present.

The precharging method of the present invention provides a fast precharging process while maintaining fault protection. It prevents potential excessive heat and losses power system in case of a short-circuit. It further has the benefit that it can be implemented in a simple manner and does not require an additional circuit for the precharge.

The biasing means provide the desired voltage for the active pulse gate control such that current flowing to the solid state device is limited during precharge. The biasing means, accordingly, are disabled and enabled contrary to the desaturation detection circuit.

Desaturation detection circuits are generally known to the skilled person. They are designed to detect situations where a power semiconductor switch comes out of saturation due to an overcurrent condition. Desaturation detection circuits monitor the voltage across a semiconductor switch (typically the collector-emitter voltage for IGBTs or the drain-source voltage for MOSFETs). If the voltage across the semiconductor switch exceeds a certain threshold (indicating that the switch is no longer in saturation), the circuit triggers a protective response, such as a disabling the gate driver.

It is pointed out that within the meaning of the present description the biasing means and the desaturation detection circuit are considered to represent a part of the solid state power controller. However, this is to be understood from a functional point of view only. The biasing means and/or the desaturation detection circuit may be separate circuits such as off-the-shelf circuits functionally enhancing the solid state power controller, which may be an off-the-shelf solid state power controller with an off-the-shelf gate driver.

Generally, the at least one semiconductor switch comprises a control terminal (such as a Gate-Terminal in case of a MOSFET) which is controlled by the gate driver.

In an embodiment, the biasing means comprise a clamping circuit which clamps, when enabled, the pulsed driver signal of the gate driver to a voltage such that the at least one semiconductor switch is operated in the active region. Accordingly, when the clamping circuit is enabled, the gate voltage is clamped to a desired voltage that allows operation of the at least one semiconductor device in the active region. The clamping circuit may be connected to the output of the gate driver or a buffer IC.

In a further embodiment, a single pulse having the second defined duty cycle is applied to the control terminal of the at least one semiconductor switch in the second time interval. Thus, a single and thus short check pulse is generated in the second time interval in which the desaturation circuit is enabled to detect if a fault is present on the output capacitor.

In a further embodiment, the duty cycle of the PWM pulses in the first time interval is smaller than the duty cycle of the PWM pulses in the third time interval. For example, duty cycle of the PWM pulses in the first time interval lies in the range between 2 % and less than 15 % and the duty cycle of the PWM pulses in the third time interval lies in the range between 15% and 25%. By increasing the duty cycle in the third time interval the charging time for precharging the capacitor can accelerated once it is clear (from the desaturation detection circuit check in the second time interval) that there is no short-circuit.

In an embodiment, there is further provided a dl/dt short-circuit protection circuit which is disabled during the precharging process. A dl/dt short-circuit protection circuit monitors a change in the current I for detecting a fault condition. It has typically a better response time in isolating a short-circuit compared to a desaturation detection but also suffers from false trigger during precharging. Therefore, it is disabled during the precharging process.

In a further embodiment, the first time interval comprises a first number of PWM pulses, and the third time interval comprises a third number of PWM pulses, wherein the first number and the third number may be equal or different. Accordingly, in each of the first and third time intervals a plurality of PWM pulses are present which may have a different duty cycle, wherein a single pulse may be present in the second time interval only.

In a further embodiment, determining during the second time interval if a short- circuit is present by the desaturation detection circuit may include comparing a drain-source voltage (or collector-emitter voltage) over the at least one semiconductor switch with a reference voltage. Such comparison may be implemented, e.g., in a comparator circuit of the gate driver. As a short-circuit current goes along with the creation of a fairly large voltage, measuring the drain-source voltage is suitable to determine if a short-circuit is present. In case a short-circuit is detected, the precharging is stopped.

According to a further aspect of the invention a power distribution and protection system is provided for. The power distribution and protection system comprises a power bus connecting a power source and a load, wherein the power bus comprises a positive voltage rail and a negative voltage rail, a capacitor arranged in parallel to the load, and a solid state power controller arranged in the positive voltage rail and/or negative voltage rail. The solid state power controller comprises at least one semiconductor switch, a gate driver configured to generate a driver signal of PWM pulses which is applied to the control terminal of the at least one semiconductor switch, a desaturation detection circuit configured to shut down the gate driver when a voltage across the at least one semiconductor switch exceeds a certain threshold, and biasing means configured to bias the pulsed driver signal of the gate driver to a voltage such that the at least one semiconductor switch is operated in the active region when the biasing means are enabled.

There is further provided a controller configured to control the gate driver, the desaturation detection circuit and the biasing means to implement the method of claim 1.

The controller may be part of the solid state power controller or may be a separate part. Embodiments of the power distribution and protection system correspond to the above described embodiments of the precharging method of the present invention. For example, the controller may be configured to control the gate driver, the desaturation detection circuit and the biasing means such that in the second time interval a single pulse is applied to the control terminal of the at least one semiconductor switch.

In a further embodiment, the desaturation detection circuit comprises a switch controlled by the controller, the switch enabling or disabling the desaturation detection circuit depending on its switching status. The switch may connect a terminal connected to a drain of the semiconductor switch with a terminal connected to a source of the semiconductor switch.

In a further embodiment, the desaturation detection circuit comprises a comparator circuit, wherein the comparator circuit is configured to compare a drain-source voltage over the at least one semiconductor switch with a reference voltage to determine if a short-circuit is present, and in such case is further configured to shut down the gate driver.

In a further embodiment, the biasing means comprise a clamping circuit which clamps, when enabled, the pulsed driver signal of the gate driver to a voltage such that the at least one semiconductor switch is operated in the active region. In an example, the clamping circuit comprises a current path that includes a transistor activatable by the controller, wherein the clamping circuit is enabled when the transistor is activated and wherein the clamping circuit is disabled when the transistor is not activated. The clamping circuit may further comprise a second resistor connected in series to a first resistor that is arranged at the output of the gate driver, wherein the first resistor and the second resistor form a voltage divider for the at least one semiconductor switch. In such embodiment, when the transistor is activated, the voltage level of the generated PWM pulsed driver signal is reduced.

The at least one semiconductor switch may be implemented as MOSFET, IGBT, GaN or SiC transistors in embodiments. The gate of such semiconductor switch is the control terminal to which the driver signal of the SSPC driver is applied.

The load of the power distribution and protection system may in principle be any load. In an embodiment, the load is or comprises a power converter circuitry such as an inverter circuitry.

It is pointed out that the present invention is not limited to any specific architecture of a solid state power controller. In particular, the solid state power controller may be implemented in the positive voltage rail and/or in the negative voltage rail of the power bus. It may be implemented with a unidirectional SSPC architecture having a single switching instance or a bidirectional SSPC architecture having two switching instances in sequence, wherein a bidirectional SSPC architecture allows bidirectional control of the current flow between a power source and a load, wherein a unidirectional SSPC architecture allows for unidirectional control of the current flow only.

The skilled person will appreciate that except where mutually exclusive, a feature or parameter described in relation to any one of the above aspects may be applied to any other aspect. Furthermore, except where mutually exclusive, any feature or parameter described herein may be applied to any aspect and/or combined with any other feature or parameter described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be explained in more detail on the basis of exemplary embodiments with reference to the accompanying drawings in which: FIG. 1 is an embodiment of a DC power distribution and protection system that implements a method of precharging a capacitor to prevent large inrush current at startup, wherein active pulse gate control of the semiconductor switches of an SSPC is implemented and short-circuit detection by means of a desaturation detection circuit is enabled in a specific time interval only; FIG. 2 is an example embodiment of the desaturation detection circuit of the system of FIG. 1; FIG. 3 is an example embodiment of a clamping circuit which clamps the output voltage of a gate driver of the system of FIG. 1 such that the semiconductor switches of the SSPC are operated in the active region; FIG. 4 is a diagram showing the duty cycle of semiconductor switches of an SSPC, the switching status of a desaturation detection circuit, the switching status of a clamping circuit, and the gate voltage of the semiconductor switches dependent on time; FIG. 5 is a flowchart of an example specific method used in a DC power distribution and protection system for precharging a capacitor while maintaining a protection surveillance during the precharging process; FIG. 6 is a flowchart of a general method used in a DC power distribution and protection system for precharging a capacitor while maintaining a protection surveillance during the precharging process; and FIG. 7 is an embodiment of a DC power distribution and protection system that implements an SSCP.

DETAILED DESCRIPTION

Aspects and embodiments of the present disclosure will now be discussed with reference to the accompanying figures. Further aspects and embodiments will be apparent to those skilled in the art.

Before discussing embodiments of the present invention with respect to FIGS. 1 to 6, the background of the invention is discussed with respect to FIG. 7 to provide for a better understanding of the present invention.

FIG. 7 shows a DC power distribution and protection system that comprises a solid state power controller 100, in the following referred to as SSPC. The system comprises a DC power source 2 (such as a DC battery) that has a positive terminal 21 and a negative terminal 22. Between the positive terminal 21 and the negative terminal 22 a battery voltage VDc is present. A positive voltage rail 3 is connected to the positive terminal 21 and a negative voltage rail 4 is connected to the negative terminal 22. The positive voltage rail 3 and the negative voltage rail 4 form a high-voltage bus.

The system further comprises a load R, wherein the load R may be formed in a plurality of manners. In examples, the load may be a power converter such as an inverter and/or an electric motor. A capacitive load generally depicted as Cioad is arranged in parallel to the load R and extends between the positive voltage rail 3 and the negative voltage rail 4. For example, the capacitive load Cioad may be formed by DC link capacitors or include such capacitors.

The SSPC 100 is a bidirectional SSPC and comprises a first semiconductor switch S1 with an antiparallel bypass diode D1 and a second semiconductor switch S2 with an antiparallel bypass diode D2 both arranged in the positive voltage rail 3. As the SSPC is bidirectional, it is able to isolate the positive voltage rail 3 in both directions. In other embodiments, the SSPC 100 is unidirectional and comprises a single semiconductor switch only. In still other embodiments, the SSPC 100 additionally comprises semiconductor switches on the negative voltage rail 4, or comprises semiconductor switches on the negative voltage rail 4 only.

The switches S1, S2 may be MOSFET (metal-oxide-semiconductor field-effect transistor), GaN (Gallium Nitride), SiC (Silicon Carbide) or IGBT (Insulated Gate Bipolar Transistor) switches. A further diode D may extend between the positive voltage rail 3 and the negative voltage rail 4. Further, optionally, a transient voltage suppressor diodes TVS may extend in parallel to the semiconductor switches S1, S2.

The SSPC 100 further comprises a gate driver 110 that is responsible for controlling the switching of the semiconductor switches S1, S2 and provides the necessary gate signals to the control terminals, i.e., the gates G of semiconductor switches S1, S2. The SSPC 100 may also comprise a microcontroller (not shown) for control of the logic and for generating a pulsed signal for the gate driver 110.

In FIG. 7, the semiconductor switches 51, S2 with antiparallel diodes D1, D2 are connected in common source/emitter configuration. The antiparallel diodes D1, D2 give current that flows in the opposite direction a path to flow. Without the diodes D1, D2, inductive currents would cease instantly, generating high voltage peaks. The system further comprises two inductances L1, L2, one before switch S1 and one behind switch S2, wherein the inductances L1, L2 are configured to limit the rate of rise of current in case of a short-circuit fault.

It is pointed out that in further embodiments each switching instance S1, S2 may be implemented by paralleling a plurality of semiconductor switches.

The precharge of a capacitor such as capacitor Cload is an important phase of a converter start-up as it prevents large inrush current flowing to the capacitor which may damage not only the capacitor but also the SSPC device. Several precharge strategies have been previously proposed. One method is to use pulse control. Pulse control is performed by switching the main SSPC devices at high frequency. The precharge current can be controlled by adjusting the duty cycle of the high frequency pulses.

The present invention enhances pulse control further by using active gate control. Active gate control works by controlling the gate voltage of solid-state semiconductor device such that it operates on active region (also referred as linear or non-saturation region) where the current allowed to flow is limited. As a semiconductor switch such as a MOSFET operates in the active region at a lower gate voltage than when operating in the saturated region, the pulsed driver signal needs to have a lower voltage. With active gate control, the capacitor precharging time can be reduced with lower peak inrush current.

As a further background, it is to be noted that, typically, in power converters, a desaturation detection method is used to determine the presence of a fault such as a short-circuit fault. With a desaturation detection, a fault is detected by sensing the voltage across the semiconductor device when it is turned on. The desaturation is designed to trip when a fairly large voltage is created by short circuit current through the semiconductor device. A potential challenge arises when the semiconductor device is operated on the active region as a desaturation signal may be triggered even when the current is within normal range and not indicative of a short-circuit.

Another protection method used in SSPCs is the dl/dt detection that monitors the change in current I. Although dl/dt detection has a better response time in isolating a short-circuit, it also suffers from a false trigger during precharge. False triggers may be avoided by disabling the desaturation detection and the dl/dt detection during precharge and re-enabling them once the semiconductor device is fully turned-on or operating on the normal region. However, this approach leads to the unavailability of a protection method during precharge. This may cause detrimental effects on the system and the semiconductor device. As an example, a precharge sequence that charges an already short-circuited capacitor results in an increase in heat on the semiconductor device especially if the capacitance is large and takes a longer time to charge. Therefore, it is essential that a protection method is implemented even during the precharge sequence.

FIG. 1 shows an embodiment of a DC power distribution and protection system which implements a protection method even during precharging in an effective manner. Regarding the general architecture of the DC power distribution and protection system, reference is made to FIG. 7. Accordingly, the DC power distribution and protection system comprises a DC power source 2 having a positive terminal 21 and a negative terminal 22, a power bus having a positive voltage rail 3 and a negative voltage rail 4, an SSPC 100, a capacitive load Cioad, and a load R which may be implemented as a power electronics converter.

The SSPC 100 may comprise two switching instances in the form of semiconductor switches S1, S2 as discussed with respect to FIG. 7, but may alternatively comprise less or more semiconductor switches as discussed with respect to FIG. 7. The SSPC 100 further comprises a gate driver 110 for the semiconductor switches S1, S2. The gate driver 110 is configured to generate a driver signal of PWM pulses which are applied to the control terminal (gates) of the semiconductor switches S1, S2. Associated with the gate driver 110 is a desaturation detection circuit 140, as will be discussed with respect to FIG. 2. Further, there is provided a biasing circuit in the form of a clamping circuit 120, the output voltage of which changes the output voltage of the gate driver 110 in case the clamping circuit 120 is activated, as will be discussed with respect to FIG. 3.

The gate driver 110 may be a commercially available off-the-shelf gate driver.

There is further provided a controller 130 which may also be part of the SSPC 100 or which may be provided by another entity. For example, the controller 130 may be integrated into a microcontroller of the SSPC 100. The controller 130 is configured to control the gate driver 110, the desaturation detection circuit 140 and the clamping circuit 120. In particular, it may provide a pulsed PWM signal to the gate driver 110, a control signal EN1 to the desaturation detection circuit 140 and control signal EN2 to the clamping circuit 120.

The controller 130 may communicate with other control devices of the power distribution and protection system.

The function of the desaturation detection circuit 140 is to determine if a short-circuit is present. An example embodiment of such desaturation detection circuit is shown in FIG. 2. The desaturation detection circuit 140 comprises terminals 141, 142 connected to the drain and source of a semiconductor switch such as semiconductor switches S1, S2. The voltage difference between a terminals 141, 142 is compared in an integrated comparator circuit 145 with a reference voltage Ref. If the measured voltage difference is larger than the reference voltage Ref, a trip signal is produced which indicates the presence of a short-circuit fault. When the trip signal is present, the gate driver 110 is shut down. The background is that in case of a short-circuit within the system (such as in load capacitor ODA), the voltage between drain and source of the semiconductor switch increases.

The desaturation detection circuit 140 of FIG. 2 further comprises a switch S5 which can be switched on or off (i.e., enabled or disabled) by the control signal EN1 provided by controller 130. The presence of switch S5 is a novel feature of the desaturation detection circuit 140.

The function of the biasing circuit 120 is to bias the voltage at the gate G of the semiconductor switch S1, S2 (see FIG. 7) such that the semiconductor switch is operated in the active region. Any biasing means appropriate for that purpose may be implemented. In the depicted embodiment of FIG. 3, the biasing means are formed by a clamping circuit 120 which clamps, when activated, the pulsed driver signal of the gate driver 110 to a voltage such that the semiconductor switch S1, S2 is operated in the active region.

To this end, in the depicted embodiment, the output voltage 110-1 of the gate driver 110 is changed by clamping circuit 110 to an output voltage 110-2 with a reduced voltage. To achieve such a function, the clamping circuit 120 provides a current path 1201 that includes a transistor 01 activatable by the control signal EN2 of the controller 130. The clamping circuit 120 is enabled when the transistor 01 is activated and the clamping circuit 120 is disabled when the transistor Q1 is not activated. The current path 120-1 further comprises a resistor Rc.

When of the clamping circuit 120 is enabled, and current flows through transistor 01, the resistor Rc and a resistor Rc at the output 110-1 of the gate driver 110 form a voltage divider for the controlled semiconductor switch (such as S1, S2). Accordingly, in a first state, when the transistor Q1 is activated (i.e., conducts current), the voltage level of the generated pulsed driver signal is reduced. In such case, a lower pulsed PVVM driver signal is present on line 110-2 such that the semiconductor switch S1, S2 are operated in the active region. On the other hand, when the transistor Q1 is deactivated (i.e., does not conduct current), the voltage level at the output of gate driver 110 is not reduced such that the pulsed PWM driver signal has a voltage level such that the semiconductor switch Si, S2 is operated in the saturated region.

FIG. 4 shows a specific precharging sequence which encompasses specific duty cycles of the pulsed PWM signal provided by the gate driver 110, and a specific sequence in the control signals EN1, EN2 provided by controller 130.

More particularly, the first row in FIG. 4 shows the pulsed PWM signal provided by the gate driver 110 to the gates of the semiconductor switches S1, S2. During a first time interval T1 PWM pulses of a first defined duty cycle Di are provided. During a second time interval T2 a single pulse with a second defined duty cycle D2 is provided. During a third time interval T3 PWM pulses of a third defined duty cycle D3 are provided. The time period for precharging a capacitor is thus divided into three time intervals, wherein a first number N1 of PWM pulses is generated in the first time interval T1, a single pulse is generated in the second time interval T2, and a second number N3 of PWM pulses are generated in the third time interval T3.

As is shown in FIG. 4, the pulses of the third duty cycle D3 may be longer than the pulses of the first duty cycle D1. For example, the pulses of the first duty cycle have a duty cycle in the range between 2 % and less than 15 %, such as 5 %, the pulses of the third duty cycle have a duty cycle in the range between 15 % and 25 %.

The second first row in FIG. 4 indicates the switching status of the clamping circuit 120. The clamping circuit 120 is enabled during the first time interval T1, disabled during the second time interval T2 and enabled again during the third time interval T3. Accordingly, the semiconductor switches S1, S2 are operated in the active region in the time intervals T1, T3 but are not operated in the active region in the time interval T2.

The third row in FIG. 4 indicates the switching status of the desaturation detection circuit 140. The desaturation detection circuit 140 is disabled during the first time interval T1, enabled during the second time interval T2 and disabled during the third time interval T3. Disabling of the desaturation detection circuit 140 may be provided by shorting terminals 141, 142 through switch S5 in the embodiment of FIG. 2.

The fourth row in FIG. 4 shows the status of a dl/dt short-circuit protection circuit. Such short-circuit protection circuit may additionally be implemented in the SSPC 100 of FIG. 1. During the precharging, however, such dl/dt short-circuit protection circuit is completely disabled (as it would trigger a faulty false signal).

The fifth row in FIG. 4 indicates the gate voltage at semiconductor switches S1, S2. The time sequence of the gate voltage corresponds to the duty cycle shown in the first row. The voltage height is decreased during time intervals T1, T3 because of the enablement of the clamping circuit 120 compared to the second time interval T2.

On the other hand, during the second time interval T2, the desaturation detection circuit 140 is enabled such that it can be checked if a short-circuit is present during the precharging. The purpose of generating a single pulse with a duty cycle and D2 in the second time interval T2 is to check the presence of a short-circuit. With the desaturation detection circuit 140 being enabled in time interval T2, the gate driver 110 will trip the precharging sequence of the capacitor be stopped in case of a short-circuit already present in the system. The single pulse in the second time interval T2 has a larger duty cycle D2 than the duty cycles D1, D3 in time intervals T1, T3, wherein the duty cycle D2 may be up to 100 percent.

If a short-circuit is not detected, the precharging will continue during time interval T3 until the capacitor is fully charged. The second precharging sequence during time interval T3 can be operated with a larger duty cycle to speed up the charging time. Once the precharge is complete, the dl/dt detection and other protection methods may be enabled again to have a fast fault clearance of the SSPC.

The corresponding method is further discussed with respect to FIG. 5. The precharging of a capacitor starts in step 501. In step 502, the desaturation detection circuit and a dl/dt short-circuit protection circuit are disabled, as they may indicate the presence of a short-circuit during precharging in a faulty manner. Further, in step 503, the clamping circuit is enabled. Further, a PWM module (meaning gate driver 110 and controller 130 providing a pulsed PWM signal to the gate driver 110) are enabled. Next, in step 504, a PWM signal of a duty cycle D1 is generated and the number of cycles is counted. If the number N1 of cycles that define the first time interval T1 is reached in 505, the desaturation protection circuit is enabled and the clamping circuit is disabled in step 506. It is then created a single pulse PWM signal of duty cycle D2 in time interval T2 in step 507. This allows to detect a short-circuit condition. In case a short-circuit condition is detected, this is indicated by the trip signal of FIG. 2 being enabled, which is the case if a fault pin is at high state. Accordingly, in step 508, it is checked if the fault pin is at high state. If this is the case, the desaturation detection trips in step 519 and the precharging is ended in step 514.

If the fault pin is not at high state in step 508, the desaturation detection circuit and the short-circuit protection it provides for are disabled again in step 510 at the beginning of time interval T3. Further, the clamping circuit is enabled and the PWM module is enabled in step 511. A PWM signal of duty cycle D3 is generated to continue precharging of the capacitor. If the number N3 of cycles that define the third time interval T3 is reached in 513, precharging ends in step 514.

FIG. 6 is a flowchart that summarizes the precharging method. In step 601, during a first time interval T1, PWM pulses of a first defined duty cycle are applied to the control terminal of the at least one semiconductor switch to precharge the capacitor while the desaturation detection circuit is disabled and the biasing means are enabled. According to step 602, in a second, subsequent time interval, the biasing means are disabled and the desaturation detection circuit is enabled, and at least one pulse with a second defined duty cycle is applied to the control terminal of the at least one semiconductor switch. By disabling the biasing means, the semiconductor switches are no longer operated in the active region.

In step 603, it is then determined by means of the desaturation detection circuit if a short-circuit is present. This happens during the second time interval. If this is the case, precharging of the capacitor is discontinued in step 604. If this is not the case (i.e., there is no short-circuit) the biasing means are enabled again and the desaturation detection circuit is disabled again in step 605. It is then applied during a third time interval PWM pulses of a third defined duty cycle to the control terminal of the at least one semiconductor switch to continue precharging of the capacitor until the capacitor is fully charged or charged to a desired level.

It should be understood that the above description is intended for illustrative purposes only, and is not intended to limit the scope of the present disclosure in any way. Also, those skilled in the art will appreciate that other aspects of the disclosure can be obtained from a study of the drawings, the disclosure and the appended claims. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. Various features of the various embodiments disclosed herein can be combined in different combinations to create new embodiments within the scope of the present disclosure. In particular, the disclosure extends to and includes all combinations and sub-combinations of one or more features described herein. Any ranges given herein include any and all specific values within the range and any and all sub-ranges within the given range.

Claims (20)

1. CLAIMS1. A method of precharging a capacitor (Goad) in a power distribution and protection system that comprises a solid state power controller (100) which controls precharging of the capacitor (Cload), wherein the solid state power controller (100) comprises at least one semiconductor switch (S1, S2), a gate driver (110) configured to generate a driver signal of PWM pulses which is applied to a control terminal (G) of the at least one semiconductor switch (S1, S2), a desaturation detection circuit (140), and biasing means (120) which, when enabled, bias the at least one semiconductor switch (S1, S2) to be operated in the active region, wherein the method comprises the steps of: applying (601), during a first time interval (T1), PWM pulses of a first defined duty cycle (D1) to the control terminal (G) of the at least one semiconductor switch (S1, S2) to precharge the capacitor (Cload) while the desaturation detection circuit (140) is disabled and the biasing means (120) are enabled; in a second, subsequent time interval (T2), disabling (602) the biasing means (120) and enabling the desaturation detection circuit (140), and applying at least one pulse with a second defined duty cycle (D2) to the control terminal (G) of the at least one semiconductor switch (S1, S2); determining (603) if a short-circuit is present by the desaturation detection circuit (140) during the second time interval (T2); if so, discontinuing (604) precharging the capacitor (Cload); and if not, enabling (605) the biasing means (120) and disabling the desaturation detection circuit (140) again, and applying during a third time interval (T3) PWM pulses of a third defined duty cycle (D3) to the control terminal (G) of the at least one semiconductor switch (S1, S2) to continue precharging of the capacitor (Gland).
2. 2. The method of claim 1, wherein in the biasing means (120) comprise a clamping circuit which clamps, when enabled, the pulsed driver signal of the gate driver (110) to a voltage such that the at least one semiconductor switch (S1, S2) is operated in the active region.
3. 3. The method of claim 1 or 2, wherein in the second time interval (T2) a single pulse having the second defined duty cycle (D2) is applied to the control terminal (G) of the at least one semiconductor switch (S1, S2).
4. 4. The method of any preceding claim, wherein the duty cycle (01) of the PWM pulses in the first time interval (T1) is smaller than the duty cycle (D3) of the PWM pulses in the third time interval (T3).
5. 5. The method of claim 4, wherein the duty cycle (01) of the PWM pulses in the first time interval (T1) lies in the range between 2 % and less than 15 % and the duty cycle (D3) of the PWM pulses in the third time interval (T3) lies in the range between 15% and 25%.
6. 6. The method of any preceding claim, wherein there is further provided a dl/dt short-circuit protection circuit which is disabled during the precharging process.
7. 7. The method of any preceding claim, wherein the first time interval (T1) comprises a first number of PWM pulses, and that the third time interval (T3) comprises a third number of PWM pulses.
8. 8. The method of any preceding claim, wherein the determining if a short-circuit is present by the desaturation detection circuit (140) during the second time interval (T2) includes comparing a drain-source voltage over the at least one semiconductor switch (Si, S2) with a reference voltage.
9. 9. A power distribution and protection system comprising: a power bus (3, 4) connecting a power source (2) and a load (R), the power bus comprising a positive voltage rail (3) and a negative voltage rail (4); a capacitor (Ciond) arranged in parallel to the load (R); a solid state power controller (100) arranged in the positive voltage rail (3) and/or the negative voltage rail (4), wherein the solid state power controller (100) comprises: at least one semiconductor switch (Si; S2), the at least one semiconductor switch (Si, S2) having a control terminal (G); a gate driver (110) configured to generate a driver signal of PWM pulses which is applied to the control terminal (G) of the at least one semiconductor switch (51; S2); a desaturation detection circuit (140) configured to shut down the gate driver (110) when a voltage across the at least one semiconductor switch (Si, S2) exceeds a certain threshold; and biasing means (120) configured to bias the pulsed driver signal of the gate driver (110) to a voltage such that the at least one semiconductor switch (Si, S2) is operated in the active region when the biasing means (120) are enabled; a controller (130) configured to control the gate driver (110), the desaturation detection circuit (140) and the biasing means (120) to: apply (601), during a first time interval (T1), PWM pulses of a first defined duty cycle (D1) to the control terminal (G) of the at least one semiconductor switch (S1, S2) to precharge the capacitor (Cload) while the desaturation detection circuit (140) is disabled and the biasing means (120) are enabled; in a second, subsequent time interval (T2), disable (602) the biasing means (120) and enable the desaturation detection circuit (140), and apply at least one pulse with a second defined duty cycle (D2) to the control terminal (G) of the at least one semiconductor switch (S1, S2); determine (603) if a short-circuit is present by the desaturation detection circuit (140) during the second time interval (T2); if so, discontinue (604) precharging the capacitor (Goad); and if not, enable (605) the biasing means (120) and disable the desaturation detection circuit (140) again, and apply during a third time interval (T3) PWM pulses of a third defined duty cycle (D3) to the control terminal (G) of the at least one semiconductor switch (S1, S2) to continue precharging of the capacitor (Goad).
10. 10. The power distribution and protection system of claim 9, wherein the controller (130) is configured to control the gate driver (110), the desaturation detection circuit (140) and the biasing means (120) such that in the second time interval (T2) a single pulse having the second defined duty cycle (D2) is applied to the control terminal (G) of the at least one semiconductor switch (S1, S2).
11. 11 The power distribution and protection system of claim 9 or 10, wherein the controller (130) is configured to control the gate driver (110), the desaturation detection circuit (140) and the biasing means (120) such that the duty cycle (D1) of the PWM pulses in the first time interval (T1) is smaller than the duty cycle (D3) of the PWM pulses in the third time interval (T3).
12. 12. The power distribution and protection system of claim 11, wherein the duty cycle (D1) of the PWM pulses in the first time interval (T1) lies in the range between 2 % and less than 15 % and the duty cycle (D3) of the PWM pulses in the third time interval (T3) lies in the range between 15% and 25%.
13. 13. The power distribution and protection system of any one of claims 9 to 12, wherein the solid state power controller (100) further comprises a dl/dt short-circuit protection circuit which is disabled during the complete precharging process.
14. 14. The power distribution and protection system of any one of claims 9 to 13, wherein the controller (130) is configured to control the gate driver (110), the desaturation detection circuit (140) and the biasing means (120) such that first time interval (T1) comprises a first number of PWM pulses, and that the third time interval (T3) comprises a third number of PWM pulses.
15. 15. The power distribution and protection system of any one of claims 9 to 14, wherein the desaturation detection circuit (140) comprises a switch (S5) controlled by the controller (130), the switch (S5) enabling or disabling the desaturation detection circuit (140) depending on its switching status.
16. 16. The power distribution and protection system of any one of claims 9 to 15, wherein the desaturation detection circuit (140) comprises a comparator circuit (145), wherein the comparator circuit (145) is configured to compare a drain-source voltage over the at least one semiconductor switch (S1, S2) with a reference voltage to determine if a short-circuit is present, and in such case is further configured to shut down the gate driver (110).
17. 17. The power distribution and protection system of any one of claims 8 to 15, wherein the biasing means (120) comprise a clamping circuit which clamps, when enabled, the pulsed driver signal of the gate driver (110) to a voltage such that the at least one semiconductor switch (S1, S2) is operated in the active region.
18. 18. The power distribution and protection system of claim 17, wherein the clamping circuit (120) comprises a current path (120-1) that includes a transistor (Q1) activatable by the controller (130), wherein the clamping circuit (120) is enabled when the transistor (Q1) is activated and wherein the clamping circuit (120) is disabled when the transistor (Q1) is not activated.
19. 19. The power distribution and protection system of any one of claims 9 to 18, wherein the at least one semiconductor switch (S1, S2) comprises a MOSFET, IGBT, GaN or SiC transistor.
20. 20. The power distribution and protection system of any one of claims 9 to 19, wherein the load (R) comprises a power converter circuitry.