GB2518338A - Multi-function adaptive processor - Google Patents

Abstract

An adaptive processor for use with multiple input signals from an array of antenna elements is designed to be used in a wide range of applications with only minor changes to component values and data stored in an application PROM. The processor is operated to minimise output power subject to a weight constraint. The control algorithm employed is a weight update correlation loop algorithm of the form Wn = (1-1ϵ)Wn-1 - µEnSn where Wn is the updated weight, ϵ is an integration loss factor, µ is the update gain, En is a complex input (element) signal and Sn is a complex sum signal. The integration loss factor is varied for each input signal and is controlled as a function of the input signal power level. Preferably the control algorithm is power normalised, that is the update gain factor is variable and inversely proportional to the power of the respective input signal. The use of a variable integration loss factor enables a fixed absolute sensitivity (turn-on) threshold to be maintained. The power normalised algorithm is preferably implemented using two automatic gain control (a.g.c.) systems and logarithmic coding of power levels to reduce system complexity.

Description

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MULTI-FUNCTION ADAPTIVE PROCESSOR

This invention relates to a multi-function adaptive processor.

The inclusion of an adaptive antenna in a system which suffers from the effect of directional, external interference is widely accepted. In practice, the effectiveness of the adaptive antenna must be balanced against other factors including cost, reliability, size and weight. The disadvantages of adaptive antennas in relation to these factors can be significantly reduced by introducing a high level of integration into hardware realisations. In particular, digital integrated circuit and analogue thick film hybrid techniques can be used to great advantage. Unfortunately these techniques imply the use of a large quantity of a particular component to offset the initial non-recurring costs.

For a specific adaptive antenna application it is doubtful that the quantities involved would justify integration. However, by using a common adaptive processor for many applications, integration becomes more attractive as development costs can be shared. This is the rationale behind the Multi-function Adaptive Processor (MAP) approach which attempts by careful design to obtain the integration advantage by an acceptable increase in functional complexity. The basic MAP approach is described in our paper entitled "Multifunction adaptive processor for small antenna arrays" by J.G. Searle and C.R. Ward, tEE Proc., Vol 130 Parts F and H, No. 1 February 1983.

The optimum performance requirements for adaptive processing vary between applications. However, the acceptable requirements are relatively common and in many cases are determined by practical limitations. One of the main issues in a multifunction processor design is to achieve acceptable performance for wide variations in the desired signal characteristics, namely its format, dynamic range and bandwidth.

The present invention aims to provide various improvements to the basic MAP outlined in the abovementioned paper.

According to the present invention there is provided an adaptive processor, for use with multiple input signals such as those from an array of antenna elements, arranged to be operated whereby to minimise output power subject to a linear weight constraint and including means for the application of a weight update correlation loop control algorithm of the form Wn = (1 -)W_1 -p E*S where is the updated weight,is an itegration loss factor, is the update gain, En is a complex input (element) signal and Sn is a complex sum signal, wherein the algorithm is power normalised that is update gain p is variable and inversely proportional to the power of the respective input signal Ens and includes means for calculating the respective update gain factor for each input signal, comprising first means to which the input signals are coupled and in which the weights are applied, a sum a.g.c. circuit means coupled to the output of said first means and an element (input signal) a.g.c. circuit means selectively couplable to each input signal in turn,the a.g.c. circuit means serving to estimate the power in the respective channels, the outputs of the sum and element a.g.c circuit means being applied to means for calculating the respective update gain p for each input signal, where pa = 2/(m(N-1)P.) where is said input signal power level as estimated by the element a.g.c. means, m is a predetermined stability margin and N is the number of input signals.

Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 shows block diagram of the multi-function adaptive processor referred to in the above mentioned paper; Fig. 2 shows the effect of sub-Nyquist sampling on the convergence time constant; Fig. 3 shows P0 versus P for an ideal system; Fig. 4 shows P0 versus P including weight quantisation effects; Fig. 5 shows P0 versus for a practical system with finiteand various values of Fig. 6 illustrates a preferred version of a multi-function adaptive processorwhich is suitable for MSI; Fig. 7 illustrates a MAP based adaptive antenna, the processor of Fig. 6 being incorporated therein; Figs. 8a to 8e illustrate various a.g.c.

systems, and Figs. 9 and 10 illustrate in greater detail parts of the processor of Fig. 6.

A wide range of radar, communications and navigation applications can be met by an adaptive processor which has upper performance bounds as follows:-a cancellation level of 40dB; a convergence time constant of loous; a dynamic range of 100dB; a bandwidth of 20KHz * e to 20MHZ; an operating frequency of 100MHZ to 400MHz and six channels. These upper bounds have been deduced by combining the requirements of many applications and modifying these by practical limits where necessary. If the RF or IF of a system does not lie within the tunable range of the processor, a separate frequency conversion unit is required. Only the most demanding applications considered would require all parameters to meet the upper bounds figures quoted above.

To control an adaptive antenna optimally requires that the signal to noise plus interference ratio (SNIR) at the array output is maximised. This optimisation problem has been well discussed (J.E.

Hudson: "Adaptive Array Principles" Peter Peregrinus, 1981) and can be shown to give rise to a weight solution given by:--l * (1) where R is the total covariance matrix including the * signal interference and thermal noise, and S is the space vector corresponding to the complex envelope of the desired signal received across the array aperture.

Implementations rely, for example, upon a-priori knowledge of the desired signal angle of arrival or the production of a correlated reference signal. There are few practical applications which permit the use of these complex optimal techniques, and suboptimal control is frequently used as an alternative. This is especially true for a MAP. However, the intrinsic ability of optimal systems to avoid excessive cancellation of the desired signal is lost with sub-optimal techniques.

Hence a further essential requirement is that a means is provided to avoid cancellation of the desired signal.

Since it is not feasible to use an optimal weight control law in a MAP design, the control law used is based upon output power minimisation subject to a -weight constraint, for example a linear weight constraint, which, for omnidirectional elements, ensures an omnidirectional quiescent response. The weight solution is given by:-WM1C (2) where CT Uooo. (3) M is the covariance matrix including interference and thermal noise only, and the scalar ensures that c11w = a constant.

A constrained solution of this type is easily implemented in hardware and its use is appropriate when there is no a-priori knowledge of the angle of arrival of the desired signal. In practice this is true for many applications which require small arrays.

Fig. 1 shows a simplified block diagram of the p type of adaptive processor described in the abovementioned paper. It can be seen that the control and weighting functions are implemented using digital and analogue circuits respectively. Digital techniques are preferred because of their potential for integration.

However, since the weighting circuits must operate on the desired signal it is essential that Nyquist rate sampling and processing is performed. With a maximum desired signal bandwidth of 20MHz, the complexity of digital weighting is unacceptable for the MAP design. This is not the case for the control circuits which do not transfer the desired signal, but process signals containing information on the spatial distribution of the interference. For the control circuits, it is desirable but not essential to be able to Nyquist sample in the current operating bandwidth. This flexibility allowed various design compromises to be made. In particular, a control circuit may be used which has a sub-Nyquist sampling rate for wideband operation of the processor.

In addition the processor may be time shared between the antenna elements. The main consequence of this choice is a loss in processing efficiency. This results in the effect shown approximately in Fig. 2 where the convergence time of the processor deviates from its theoretical optimum for wide bandwidth. The on-set of these effects occur in a region beyond the convergence time requirements for most applications and is not a significant limitation. The remaining disadvantages of regular sub-Nyquist sampling, with respect to periodic signals, are greatly reduced by randomising the sampling intervals.

To obtain the weight solution given by equation (2) a gradient descent algorithm is used. This choice was made because of the resulting simplicity of the control circuits and its relatively high tolerance to component errors and failures. The basic discrete time, steepest descent algorithm used in the adaptive processor is: W(k + 1) = w(k) -p G(k) (4) where G(k) is an indication of the gradient of the array output power residue at the weight values W(k) and is the update gain factor. In practice, the update equation must be modified to include integration loss and a weight constraint. For the MAP design the algorithm becomes: W(k-s-l) = P1W(k) -F P2M(k)W(k) (5) and 2 are matrices of the form: (6) o 0 0. . 0 o i 0 1 * 1 o. . . * 1 which ensure that the clamped weight is neither updated or deweighted by the algorithm. The deweighting factor K was introduced for practical reasons and was originally made less than, but close to, unity.

If the integration loss factor, is defined as E= 1-K, then the steady state weight solution given by the. algorithm of equation (5) is: W%(M+E/jlI)'C (7) When 0 it can be seen that the solution corresponds to the desired result of equation (2). At steady state the introduction of the deweighting factor K is seen to be equivalent to raising the thermal noise level in the system. The simplicity of implementing this algorithm can be seen by considering the update equation for a single element of the weight vector: w.(k÷l) = Kw1(k) -i x(k)y(k) (8) As shown the update factor for a given weight is given by the product of the gain factor the sampled element signal x and the sampled array output (sum) signal y.

By utilising the array output signal the potential N complex multiplications per iteration is reduced to one for each element. Also since feedback from the array is involved in the algorithm it is referred to as a closed loop technique and it is this aspect which accounts for its high tolerance to errors.

It can be shown that the residual output power (P0) from this type of system for a single narrowband interference source is given by:

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p =p. (9) 0 1 where P is the interference power received at each element, is the corresponding uncorrelated thermal noise power and N is the number of array elements. (The term "power" is here taken to imply the mean squared magnitude of voltage. To be strictly accurate, when adopting the complex representation of signals, the mean squared magnitude reflects twice the true power of the signal).

Using the equation 9, P0 is plotted against P in Fig. 3, with as a parameter. It can be seen that when (a condition often met in practice) equation (9) becomes ___ (10) where is the sensitivity threshold given by = (Nl)J.1 (11) At input powers below this threshold the array operates in a linear region where equation (10) reduces to: __ (12) At input powers above this threshold the array operates in a "power inverston" region where equation (10) reduces to: po_-___ Pj2 (13) For a single, narrowband signal, the power inversion region reaches a stability limit when: __ 3.

(N-l)p (14) In this analysis the effect of weight noise has been ignored. This is acceptable whenC/li'fl cr1, since weight noise effects do not become significant until the processor is operating in a region very close to the stability limit. Equation (9) indicates that in order to minimise the output power, Eshould be set to zero, in which case the power inversion threshold is the thermal noise level. This implies that a of 50dB above thermal noise is cancelled to 50dB below thermal noise, a total cancellation of 100dB. Such levels of cancellation are not practically feasible and by consideration of the practical weighting circuits it was shown in the abovementioned paper that a finite is desirable.

The form of weighting circuit depends upon the amount of frequency dispersion which is expected in the system. Some sources of dispersion, such as channel mismatch, are controllable. Others, such as aperture dispersion, are essentially beyond the designers' control. Dispersion limits the fractional bandwidth over which the array will produce acceptable levels of cancellation. The worst situation for the multi-function processor exists in conditions when the centre frequency is set at 160MHZ and the bandwidth to 20MHz, a fractional -10 -bandwidth of approximately 12%. In terms of channel matching in a processor unit, single complex weights on each channel can provide in excess of 40dB cancellation in a 20% fractional bandwidth. To include the effects of aperture dispersion in the MAP design is difficult since no specific array configuration or radiated frequency is defined. In general, if the fractional bandwidth (now with reference to the radiated frequency) is in excess of 1-5%, aperture dispersion effects may become dominant in determining cancellation levels. If dispersion effects become significant in a multi-channel processor, then unused degress of freedom automatically aid the cancellation process.

The performance of single complex weights, implemented by inphase and quadrature networks, is just acceptable for the MAP design, and these weights are digitally controlled via n-bit digital-to-analogue converters (DACs). The use of DACs introduces a coarser quantisation effect into the applied weight such that the former continuous range of weight values becomes a series of discrete points in the complex plane. Thus for a particular interference environment only a discrete approximation to the required W is available. The cancellation performance is described by the parameter Cn and is the ratio of the array output powers in the unadaptive and adaptive modes. Weight quantisation reduces the average degree of cancellation in accordance with: Cn = 100.6n N (15) The effect of such a limit on the cancellation level alters equation (10) so that it becomes a »=!j fll + L°-+ i/tlJ (16) where t2 = (17) Equation (16) is plotted in Fig. 4 with practical results included. The shape of the P0 against P curve is now significantly changed. A third region exists where po..pi C (18) indicating that the cancellation limit has been reached.

The dynamic range of the processor may be defined as _____-1 tl -(19) As indicated in Fig. 4, the dynamic range represents the range of input power over which a departure from the linear characteristic is achieved. For constant the dynamic range is a function only ofEand again jshould be made as small as possible. In practice, circuit imperfections, such as DC offsets generated by the circuits, require that large enough to prevent the quiescent array pattern from being distorted. The level and nature of circuit imperfections are strOngly dependent on the precise implementation of the control algorithm, and the above mentioned paper stated that the then existing processor designs indicated values of E between 1O and io6 were achievable. Whereas that figure would satisfy the instantaneous dynamic range requirements of the MAP, it would not accommodate the operational dynamic range specification of 100dB. To meet this requirement an adaptively controlled update gain factor j.i is implied. If Lis fixed at a relatively large value, it is possible to generate a series of P0 -12 -against P. curves, as shown in Fig. 5, by varying u. An a.g.c. circuit can be used to set r to an optimum value based on measurements of P. For a particular P the optimum r would be given by :1= 2 m(N-l)P. (20) where in provides a chosen stability margin. This is referred to as power notmalisation. This design approach was initially adopted because in a digital control circuit, a large value ofEleads to small word lengths and large, variable gains (6dB per shift) can be easily accommodated.

The use of an a.g.c. circuit to adjust the update gain factor ensures that the speed of response to the strongest received signal is normalised to the fastest realisable time constant of adaption. The time constants for the modes of response of an adaptive array controlled by the steepest descent algorithm are inversely proportional to the product of the update gain factor and the eigenvalue associated with each mode. The fastest time constant can be shown to be given by: i max ndependent samples 2 (21) The simplicity and reliability of gradient descent processors make them an obvious choice for a cost-effective design. However, it should be nOted that, in signal environments which result in an ill-conditioned covariance matrix, the time taken for the processor to converge can be between lO to 1O4 times that taken for a simple environment. Convergence is characterised by the eigencomponents of the covariance matrix. Typical situations which result in a wide eigenvalue spread and hence slow overall convergence times include compact angular distribution of signals (in terms of the natural beamwidth of the array) or interference sources of disparate power levels. System errors and dispersion can -13 -also generate weak eigencomponents which may effect the transient response.

The arrangement described above involves a typical correlation loop algorithm employing a power normalised update equation. The loss factor is assumed constant. However, it is now proposed to make the loss factor variable (adaptive) and to control it as a function of the interference power received at each element P. In this case is given by: çZ L m P (22) where m is the stability margin referred to above and is a control variable which is actually an artificial and fixed absolute sensitivity threshold as shown below. J affects the null depth and the weight decay of the adaptive process. The sensitivity threshold is given by equation (11) as: £ (N-l)y (23) Substituting equation (22) and equation (20) into equation (23) there is obtained: Pti = .2. m(N-l)P. = PL m P (N-l) 2 (24) Hence, employing equation (22) causes an artificial sensitivity (turn-on) threshold, independent of the input power and given by the control variable L Previously this threshold was variable and dependent on the received interference power.

The application of this algorithm is to protect wanted signals below the level whilst suppressing stronger unwanted signals above the level The control algorithm thus proposed employs a variable loss -14 -factor which in turn allows the use of power thresholds.

Whilst the abovementioned paper described the basic power normalised, correlation loop algorithm, how it was to be implemented in digital hardware was not discussed.

If linear coding were employed for all the variables in the control algorithm (either the basic form or the variable loss factor form) then excessive hardware complexity would result in storage requirements for the arithmetic operations that are implied. If, however, logarithmic coding of some of the variables is used then hardware complexity is reduced due to the shorter wordlengths employed and due to the reduction of multiply and divide operations to simple additions and subtractions.

For example, a variable can be coded in a 16 bit unsigned linear form giving it approximately 96dB of dynamic range. The quantisation error suffered by this coding method relative to the magnitude of the variable will vary according to this method, with large signals suffering little relative quantisation errors and small signals suffering large quantisation errors. If the variable is to be multiplied by another similarly coded variable then a large multiplying array (16 x.16) is required.

The same dynamic range can be encoded by an 8 bit unsigned word employing logarithmic coding and using a log base of 2 with the binary point in the centre of the word. In this case the quantisation error is constant relative to the magnitude of the variable over most of its dynamic range. The equivalent of multiplying two linear numbers is to add two logarithmically coded words, requiring a simple 8 bit adder as opposed to the 16 x 16 multiplying array referred to above.

A preferred version of the MAP processor illustrated in Fig. 1 has the functional block diagram illustrated in Fig. 6. The version of Fig. 6 is particularly suitable for medium scale integration (MSI).

As indicated above, the MAP is designed to be used in a wide range of applications. This is achieved with only minor changes to component values and data stored in the application PROM (application ROM of Fig. 1 -application memory of Fig. 6). The MAP is a common core device in an adaptive antenna electronic unit. The peripheral function blocks shown in Fig. 7 are required to complete the system.

The MAP shown in Fig. 6 includes a variable beamformer 1 to which HF inputs are applied as well as being applied to an HF MUX 2. The HF output of the beamformer 1 (sum channel) is applied to an a.g.c.

amplifier 3 (sum a.g.c.) whereas the output of the RF MUX 2 (element channel) is applied to an a.g.c. amplifier 4 (element a.g.c.). The respective outputs of a.g.c.

amplifiers 3 and 4 are converted to zero I.F. in element and the respective outputs of element 5 are converted to digital form by ADC 6 for application to control circuit 7 which applies the algorithm in accprdance withtiming information, generated from pseudo random sampling patterns stored in PROM, and any externally supplied infornation by way of the external microprocessor interface, The output of the control circuit adjusts the weights applied in the beamformer 1 and controls the a.g.c. amplifiers.

The method of data acquisition employed by the MAP yields three digital words for each of the element and sum channels. In each channel two 4 bit words carry instantaneous magnitude and phase information of the channel (in inphase and quadrature form) whilst one B bit word carries the rms information of the channel. The element and sum a.g.c.'s each serve two purposes.

Firstly to estimate the power in the respective channel and secondly to divide the incoming signal by its r.m.s.

-16 -value in order to cause the result in steady state to be within the range of the following ADC.

The element signal x(k) can be derived from the three words by the equation: (25) where x1(k), i and k are defined above and used in equation (B) and where Xaaii(k) = the inphase 4 bit AD word Xadq,i(k) = the quadrature 4 bit AD word Xiri(k) the logarithmically (base 2) coded r.m.s. estimate of the channel similarly the sum signal y(k) is given by (26) Hence equation (8) becomes w(k+l) = K w1(k) -u x(k) y(k) = (l-E)w.(k) -adi,i1Xadq, i(k]*Zxir. 1(k) L[Yadi(k)+iyadq(kD*2Ylr(k) (27) Both in equations (20) and (22), the scalar variable P. (which represents the interererice power received at each element) is used without any indication as to how the control algorithm calculates it in practice. In fact for a typical system the power received at each element is not constant and in general the received power should be represented by a vector.

In the MAP design the element a.g.c. and the digital control algorithm are switched between each of the element inputs on a time shared basis. Due to the -17 - control law (described hereinafter) employed, the element a.g.c. effectively averages the power of each of the element inputs. This power is given by: average power =Z2'ir,i' (28) being the r.m.s. value squared.

Hence for power normalised fixed threshold (variableE) operation of the MAP, the control equations given by equations (20) and (22) become frm(N-l) 2x1.(k) (29) 2 ___ 2x (k) m lr,i (30) Substituting equation (29) into equation (27) gives w.(k+1) = (l-E)w.(k) -2. _________ m(N-l) ZXlr,i 1 [adi,i3'<adq, i(k]aj(k)+Yaq(k] (31) which can be reduced iffy a gain factor, is defined as follows: 2. y1(k) m(N-1) Xir,i(U (32) By logarithmically coding the variables m/2, m(N-1)/2, L andEas follows: -18 -im = log2(m/2) (33) lmn = log2(m(N-1)/2) (34) lb = log2(/ ) (35) ipi = log2(P) (36) 1 = 1og2() (37) equation (32) becomes 21b = 1 __________ Zlmn aciri1 (38) and equation (30) becomes = 1 ______ 21m *Z. X(k) (39) Taking logs in equations (38) and (39) lb = -x1.(k) -lmn (40) and l= ipi -2Xiri(k) -im (41) Thus the two control equations as represented by (40) and (41) can be implemented in low complexity subtractors and the same hardware used on a time-shared basis in order to calculate both equations. Thus a power normalised algorithm can be implemented in hardware using two automatic gain control systems and logarithmic coding of power levels in order to reduce system complexity.

The control function for the a.g.c. systems may be as follows in which the time constant of response for a step input is independent of the magnitude of the step and logarithmic implementation of the control function leads to a reduction in system complexity.

The feedback function of the a.g.c.'s is derived from the simple feedforward a.g.c. system shown in Fig.Ba. This a.g.c. is unlike many typical analogue a.g.c. systems in that the time constant of response of the a.g.c. is independent of the magnitude of the incoming signal. The system essentially estimates the "root mean square" (y') of the incoming signal (x'), the "mean" operation being carried out by the lossy integrator 80. Fig.8(b) shows the feedback equivalent of Fig.8(a), except that now the drive to the a.g.c. loop is quantised and limited by the AD converter 81. In Fig.8(c) the lossy integrator is replaced by a simple discrete time feedback digital filter 82. A multiplying factor (1-a) compensates for a loss caused by the factor a in the feedback loop of the filter and does not affect the time constant. For the a.g.c.'s in Figs.8(b) and 8(c) to have the same time constant it can be shown that a = e and that the time constant of the a.g.c. in Fig.8(c) it= -2/ln(a) samples, which is independent of the power of the incoming signal.

Let the output of the AD converter at time t = nT be 5adn = Sadl,n + Sad2,n where J = (S being equivalent to y in the previous discussion, 8adl,n being equivalent to adi and Sad2 being equivalent to adq0 Let the power estimate at the output of the digital filter at time t=nT be P5, which is actually 22Xlr,i(k) from equation (28) using the previous notation.

The energy of the input signal at this particular time is given at the output of the squarer by En = [dl)2 + (Sad2fl)2J (42) The digital filter calculates a new estimate of power.by the equation = a + {la)En s,n+l = aPs,n + (1-a) P [Sd2 + 5ad ni = P5(,a + (1-a) ESan,n + (Sad2,niJ -20 -Hence the new r.ms. estimate is je51 =,jc-;-+ (1-a) ESadln)2 + (Sad2fl)]](44) This derivation is shown schematically in Figs.B(d) and 8(e).

For convenience in order to keep digital wordlengths small the r.m.s. estimate is represented by its logarithm and the divider preceding the AD converter is in practice an antilbgarithmic analogue voltage controlled attenuator, i.e. the attenuation is given by the antilog of the control voltage.

Hence taking logs in equation (44) lojP5 = log,/P5 + 1⁄2log[a÷(l-a) ffadln2 + (Sd2)J In practice the term 1⁄2log[a+(l-a) (Sadln)+(Sad2n)*]}s generated in a PROM and summed with the log of the previous r.m.s. estimate.

The a.g.c. in Fig.8(e) works in the same manner as that in Fig.B(a) except that now the limiting of the AD converter causes the a.g.c. to have a slew rate limitation, for large changes in the input signal, given by 20(1⁄2log[a+(1-a) Esadl,n(ma2 + (S d2 (max)fJ dB/sample Figs. 9 and 10 are equivalent to parts of the schematic arrangement of Fig. 6. Fig. 9 includes the element a.g.c., the sum a.g.c., the zero IF and the ADCs whereas Fig. 10 shows the ccrreiator (control circuit) including various PRaMS, power normalisation, a weight RAM and a MAC.(multipy-accumulate block) which applies the update equation, together with overflow detection and -21 -weight limiting. Control registers (DREG) control the operation of the processor and are driven by the same clock. The element and sum a.g.c.'s (Fig. 9) are identical and serve to control gain in their respective channels such that the AD converters are exercised properly. The VCA's control the gain of the analogue signals which are applied to the inphase and quadrature AD converters for each chanr.el. A PROM (logarithmic update PROM) is used to implement the a.g.c._update algorithms which essentially involve anJiQ2 operation on the complex inputs and a logarithmic update function with a range of time constant and AD range characteristics. A lower limit for the gain control word (agc lower limit) can be used to restrict the range of the a.g.c. A comparator (COMP) detects when the control word falls below the lower limit and multiplexes the limit to the following gain control register (DREG) rather than the updated control word. The power normalisation part of Fig. 10 (top-left-hand) calculates the p andEf actors that are incorporated intO the weight update equation. Due to the similarity in the equations for p andEthe calculations are achieved by time sharing the arithmetic units between the two functions. The input element and sum a.g.c. contrOl words are logarithmically coded RMS estimates in the respective channels logJP and log%in Fig. 10. To calculate the gain factor u in power normalised mode (variable the element r.m.s. control word is subtracted from the sum r.m.s. control word (in fixed gain mode (ji constant) they are added). To calculate loss factor fixed threshold mode (Evariable) the element word is subtracted from the required power threshold (1ogfri). In both cases loss and gain constants (logJ2/m or log,j/m(N-l) ) are applied by a second adder. A compare/multiplex structure is used * to limit the range of both the gain and loss factors. A fixed loss factor (logJ) can also be applied at this -22 -point. The MAC receives weights from the weight RAM and updates them according to received gain, loss and correlation values. The updated weight, which may be limited according to the application, is returned to the weight RAM as well as passed to the beam control block (variable beamformer). Since the a.g.c. attenuator introduces a phase rotation as a function of attenuation and frequency, the element and sum signals 5ad and Ead) must be applied to PROM's to correct the phase error (sum phase rotation PROM and element phase rotation PROM) likewise for controlling the sign of Multiply PROM's iogjF5 and 1og,Ji must similarly be phase corrected (Phase correction PROM). The phase corrected signals are applied to the Multiply PROMS which essentially calculate the complex conjugate product between the element and sum signals, and also derive a limit on the update gain which is passed to the power normalisation portion of Fig. 10.

In practice the antilogarithmic voltage controlled attenuator (antilog VCA) will generate small errors in dividing the input signal by the estimated r.m.s. signal. The errors introduced by the attenuator do not, however, degrade the performance of the a.g.c.

operation, that is the AD converters will still be exercised properly. However the attenuator error will cause an equal error in the estimate of r.m.s. in the channel. Also the attenuator has a propagation delay in its control path and the ZIF filter between the attenuator and the AD converter causes a 1/bandwidth delay. Hence there is a delay between changing the attenuator control voltage and its effect becoming apparent at the AD converter input. This delay causes transient errors in the r.m.s. estimate and reduces the stability margin of the a.g.c. loop.

As mentioned in the paper referred to above, in addition to the main circuits which perform the control algorithm, some additional features are required to -23 -prevent cancellation of the desired signal. The following parameters can be controlled, namely: (a) sensitivity thresholds by a variable gain factor (b) operating frequency and bandwidth; Cc) sampling time and Cd) effective array size. For some applications the values of these parameters may be determined by the contents of a ROM. However, provision is made for external variation of the parameters via a real-time interface (external microprocessor interface).

Applications of the MAP may be categorised by the method used to avoid cancellation of the de5ired signal: (i) Sensitivity thresholds.

In systems where, at the antenna, the power level of the desired signal is less than the threshold power at-which interference becomes effective, the sensitivity threshold of the adaptive process can be set using If the sensitivity threshold is set corresponding to the interference threshold, then only those signals which degrade system performance are cancelled by the processor, the desired signal remaining in the linear region of operation. Direct-sequence spread-spectrum systems fall in this category.

In many satellite and communications systems the interference threshold, and hence the required y, is relatively constant with time.' (ii) Operating frequency and bandwidth control.

In systems where the power spectrum of the interference is different from that of the desired signal, frequency and -24 -bandwidth controls can be used to create a sampling window in the frequency domain which does not contain desired-signal components. In many situations the interference power spectrum will be significantly under than the desired-signal spectrum, in which case an offset sampling window may be used. A further application is with frequency-hopped spread-spectrum systems, where adaptation is performed on frequency channels not currently in use.

(iii) Sampling time control.

In systems where the interference power is sometimes significantly higher than the desired-signal power, a sampling window in time can be used. The processor only adapts on signal samples taken during the window period when the desired signal is below the sensitivity threshold, Such techniques may be used in some radar applications where a short dead period occurs every pulse repetition interval. - (iv) Effective array size.

This technique relies upon limiting the degrees of freedom available to the array. If a particular interference environment consisted of N interference sources which were stronger than the desired signal, then an array of the type discussed with (N.+l) elements would produce the best average improvement in SNIR for the suboptional control algorithms considered. More elements -25 -desired signal; less would prevent some of the strong interferences from being cancelled. The time-shared nature of the processor provides an efficient means of controlling the effective array size, and is applicable to many systems without constraints on the signal format.

Thus the invention provides an adaptive antenna processor which is designed to be used in a wide range of applications with only minor changes to component values and data stored in a so-called application PROM. Sub-optional techniques involving a power-normalised constrained steepest-descent control algorithm have been used. The control algorithm employs a variable loss factor, which in turn allows the use of power thresholds.

The method employed for implementing the power normalised algorithm in hardware uses two automatic gain control {a.g.c.) systems and logarithmic coding of power levels.

The agc systems may be controlled in a manner such that the time constant of response for a step input (incoming signal) is independent of the magnitude of the step.

The weight update equation can be written in various forms and in particular as follows W = (l_E)Wn1 -/.4ES where Wn = updated weight = integration loss factor = update gain En = complex element signal Sn = complex sum signal whereas the adaptive processor has been described above in relation to an antenna array, it is applicable to other systems involving multiple input signals such as an adaptive filter where the "input" signals are the signals obtained from the taps on a multi-tapped delay line, which signals are to be weighted in a predetermined manner prior to summing thereof.

Claims (6)

1. -26 -CLAIMS.1. An adaptive processor, for use with multiple input signals such as those from an array of antenna elements, arranged to be operated whereby to minimise output power subject to a linear weight constraint and including means for the application of a weight update correlation loop control algorithm of the form W = (l-E)W -UESS n n-l s n n where is the updated weight, is an integration loss factor, fi is the update gain, En is a complex input (element) signal and Sn is a complex sum signal, wherein the algorithm is power normalised that is update gain is variable and inversely proportional to the power of the respective input signal En and including means for calculating the respective update gain factor for each input signal, comprising first means to which the input signals are coupled and in which the weights are applied, a sum a.g.c. circuit means coupled to the output of said first means and an element (input signal) a.g.c. circuit means selectively couplable to each input signal in turn, the a.g.c. circuit means serving to estimate the power in the respective channels, the outputs of the sum and element a.g.c. circuit means being applied to means for calculating the respective update gain for each input signal, where f'= 2/(m(N-l)P) where P1 is said input signal power level as estimated by the element a.g.c.means, m is a predetermined stability margin and N is the number of input signals.
2. 2. An adaptive processor as claimed in claim 1, wherein said sum and element a.g.c. circuit means outputs are logarithmically coded.
3. 3. An adaptive processor as claimed in claim 1 or claim 2, wherein the sum and element a..g.c. circuit means each include a respective antilogarithmic voltage controlled attenuator and including respective PROM means whereby to correct for phase errors introduced by the -27 -antilogarithmic voltage controlled attenuators.
4. 4. An adaptive processor as claimed in any one of claims 1 to 3, wherein each a.g.c. circuit means serves also to divide the input signal applied thereto by its r.m.s. value whereby to cause the resultant signal, which is applied to a subsequent analogue-to-digital converter, to be within the range of said analogue-to-digital converter.
5. 5. An adaptive processor as claimed in any one of claims 1 to 1, wherein the time constant of response of each a.g.c. circuit means is independent of the magnitude of the input signal applied thereto.
6. 6. An adaptive processor, for use with an array of antenna elements, substantially as herein described, for a constant integration Loss factor, with reference to and as illustrated in Figs. 6 and 7 with or without reference to Fig. 8 or Figs. 9 and 10 of the accompanying drawings.Amendments to the claims have been filed as follows 7CCLAIMS.( 1. An adaptive processor, for use with multiple input signals, such as those from an array of antenna elements, arranged to be operated whereby to minimise output power subject to a linear weight constraint and including means for the application of a weight update correlation loop control algorithm of the form W = (l-E)W -nE*S n n-i nn where is the updated weight, is an integration loss factor, Jsis the update gain, En is a complex input (element) signal and Sn is a complex sum signal, wherein the algorithm is power normalised that is update gain is * variable and inversely, proportional to the power of the respective input signal and including means for calculating the respective update gain for each input signal, comprising first means to which the input signals are coupled and in which the weights are applied, a sum a.g.c. circuit means coupled to the output of said first means and an element (input signal) a.g.c. circuit means selectively couplable to each input signal in turn, the a.g.c. circuit means serving to providda gain-controlled output by dividing the input signal applied thereto by it r0ms6 value, said output, which is applied to a subsequent analogue-to-digital converter, being within the range of said analogue-to-digital converter, which r.m.s. value provides estimates of the power in the respective channels, the outputs of the sum and element -a.g.c. circuit means being applied to means for calculating the respective update gainpfor each input signal, where,M= 2/(m(N-l)P) where is said input signal power level as estimated by the element a.g.c.means, m is a predetermined stability margin and N is the number of input signals.2. An adaptive processor as claimed in claim 1, wherein said sum and element a.g.c. circuit means outputs are logarithmically coded.3. An adaptive processor as claimed in claim 1 or claim 2, wherein the Sum and element a.g.c. circuit means each include a respective antilogarithmic voltage controlled attenuator and including respective PROM means whereby to correct for phase errors introduced by the antilogarithmic voltage controlled attenuators.4. An adaptive processor as claimed in any one of claims 1 to 3, wherein the time constant of response of each a.g.c. circuit means is independent of the magnitude of the input signal applied thereto.5. An adaptive processor, for use with an array of tfls cluantd t\n tVo.Un. cwLk I antenna element7unstaEtia!1y as hereinèscribed, for a constant integration loss factor, with reference to and as illustrated in Figs. 6 and 7 with or without reference to Fig. 8 or Figs. 9 and 10 of the accompanying drawings.--