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GB2513516A - Major branch instructions with transactional memory - Google Patents

Major branch instructions with transactional memory Download PDF

Info

Publication number
GB2513516A
GB2513516A GB1414684.9A GB201414684A GB2513516A GB 2513516 A GB2513516 A GB 2513516A GB 201414684 A GB201414684 A GB 201414684A GB 2513516 A GB2513516 A GB 2513516A
Authority
GB
United Kingdom
Prior art keywords
code
segment
major branch
branch instructions
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB1414684.9A
Other versions
GB201414684D0 (en
Inventor
Brian Robert Prasky
Christopher Anthony Krygowski
Chung-Lung Kevin Shum
Fadi Yusuf Busaba
Steven Carlough
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/362,513 external-priority patent/US9229722B2/en
Priority claimed from US13/362,574 external-priority patent/US9280398B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB201414684D0 publication Critical patent/GB201414684D0/en
Publication of GB2513516A publication Critical patent/GB2513516A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.
GB1414684.9A 2012-01-31 2013-01-23 Major branch instructions with transactional memory Withdrawn GB2513516A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/362,513 US9229722B2 (en) 2012-01-31 2012-01-31 Major branch instructions with transactional memory
US13/362,574 US9280398B2 (en) 2012-01-31 2012-01-31 Major branch instructions
PCT/EP2013/051227 WO2013113595A1 (en) 2012-01-31 2013-01-23 Major branch instructions with transactional memory

Publications (2)

Publication Number Publication Date
GB201414684D0 GB201414684D0 (en) 2014-10-01
GB2513516A true GB2513516A (en) 2014-10-29

Family

ID=47624055

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1414684.9A Withdrawn GB2513516A (en) 2012-01-31 2013-01-23 Major branch instructions with transactional memory

Country Status (4)

Country Link
CN (1) CN104081343B (en)
DE (1) DE112013000453B4 (en)
GB (1) GB2513516A (en)
WO (1) WO2013113595A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10019264B2 (en) * 2016-02-24 2018-07-10 Intel Corporation System and method for contextual vectorization of instructions at runtime
US11558473B2 (en) * 2020-12-17 2023-01-17 International Business Machines Corporation Aspect aware streams computing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725334A1 (en) * 1995-02-03 1996-08-07 International Business Machines Corporation Executing speculative parallel instruction threads
US20030018826A1 (en) * 2001-07-13 2003-01-23 Shailender Chaudhry Facilitating efficient join operations between a head thread and a speculative thread
US20040103410A1 (en) * 2000-03-30 2004-05-27 Junji Sakai Program conversion apparatus and method as well as recording medium

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3665022A (en) 1969-09-02 1972-05-23 Shionogi & Co Degradation of side chain in sapogenins
US3666022A (en) 1970-11-23 1972-05-30 Edward A Bailey Striking bar
GB9015916D0 (en) 1990-07-19 1990-09-05 Schering Agrochemicals Ltd Herbicides
DE4134273C2 (en) 1991-10-17 1994-05-26 Wolfgang Mayer Device for cutting and edging plate-shaped workpieces
AU6629894A (en) 1993-05-07 1994-12-12 Apple Computer, Inc. Method for decoding guest instructions for a host computer
US5551013A (en) 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
US5790825A (en) 1995-11-08 1998-08-04 Apple Computer, Inc. Method for emulating guest instructions on a host computer through dynamic recompilation of host instructions
US5907702A (en) * 1997-03-28 1999-05-25 International Business Machines Corporation Method and apparatus for decreasing thread switch latency in a multithread processor
US6009261A (en) 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6308255B1 (en) 1998-05-26 2001-10-23 Advanced Micro Devices, Inc. Symmetrical multiprocessing bus and chipset used for coprocessor support allowing non-native code to run in a system
US6463582B1 (en) 1998-10-21 2002-10-08 Fujitsu Limited Dynamic optimizing object code translator for architecture emulation and dynamic optimizing object code translation method
US6594755B1 (en) * 2000-01-04 2003-07-15 National Semiconductor Corporation System and method for interleaved execution of multiple independent threads
US20040154010A1 (en) * 2003-01-31 2004-08-05 Pedro Marcuello Control-quasi-independent-points guided speculative multithreading
US7930695B2 (en) * 2006-04-06 2011-04-19 Oracle America, Inc. Method and apparatus for synchronizing threads on a processor that supports transactional memory
US9146745B2 (en) * 2006-06-29 2015-09-29 Intel Corporation Method and apparatus for partitioned pipelined execution of multiple execution threads
US20100162247A1 (en) * 2008-12-19 2010-06-24 Adam Welc Methods and systems for transactional nested parallelism

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0725334A1 (en) * 1995-02-03 1996-08-07 International Business Machines Corporation Executing speculative parallel instruction threads
US20040103410A1 (en) * 2000-03-30 2004-05-27 Junji Sakai Program conversion apparatus and method as well as recording medium
US20030018826A1 (en) * 2001-07-13 2003-01-23 Shailender Chaudhry Facilitating efficient join operations between a head thread and a speculative thread

Also Published As

Publication number Publication date
DE112013000453T5 (en) 2014-09-11
WO2013113595A1 (en) 2013-08-08
DE112013000453B4 (en) 2023-05-17
CN104081343A (en) 2014-10-01
GB201414684D0 (en) 2014-10-01
CN104081343B (en) 2016-08-17

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)