GB2511080A

GB2511080A - Transceiver

Info

Publication number: GB2511080A
Application number: GB1303155.4A
Authority: GB
Inventors: Wolfgang Bruchner
Original assignee: CASCODA Ltd
Current assignee: CASCODA Ltd
Priority date: 2013-02-22
Filing date: 2013-02-22
Publication date: 2014-08-27
Also published as: GB201303155D0

Abstract

The invention finds application in a receiver which applies automatic gain control (AGC) to an amplifier 2, 12. A digital gain control signal for controlling the gain of the amplifier is converted to a digital received signal strength indication (RSSI). In an embodiment multiple gain signals G1, G2, G3 are used to control multiple amplifiers 2, 12 and a filter 10. In which case, the RSSI is based on a combination (e.g. summation) of the gain control signals. The gain control signal may be converted to RSSI by inversion or through a look up table (LUT). The receiver may form part of a transceiver.

Description

TRANSCEIVER

INTRODUCTION

The present invention relates generally to a method and apparatus for obtaining a signal strength value or indicator for received signals.

Receivers and transceiver will typically include an automatic gain control (AGO) circuit and a received signal strength indicator (RSSI) circuit. The AGO circuit is typically used to optimise signal levels for processing in the receiver! transceiver and the RSSI is typically used to provide an indication on received signal quality to layers higher than the physical layer.

Various different forms of AGO and RSSI circuits have been realised and these mainly fall within one of the following examples. The AGO and the RSSI may be derived from either the received analog signal or an analog-to-digital converted signal from the received analog signal, or may be derived from a baseband signal using digital signal processing. The AGO may then be used to control various amplification stages in a receiver chain, for example, a low noise amplifier ([NA), a baseband amplifier or a mixer, for both fine and coarse gain adjustment.

Figures 1, 2, 3, 4 and 5 of the accompanying drawings illustrate known examples for deriving the AGO and RSSI. Each of the examples illustrated schematically include an analog front-end of a receiver 100 with digital processing. The analog front-end in each example comprises a [NA 102, a down conversion mixer 104 that combines the amplified signal from the [NA 102 with quadrature signals I and Q ([0) generated by a quadrature generation unit (not shown), a bandpass filter 106, an IF amplifier 108, and an analog-to-digital converter (ADO) 110. The [NA 102 at the input is connected to an antenna (not shown). The [NA 102 is typically a high-gain amplifier. The output of the [NA 102 is electrically connected to the down conversion mixer 104 or passive quadrature mixer. The down conversion mixer 104 is connected to a bandpass filter 106 and an IF amplifier 108. The bandpass filter 106 is used to remove the RF component from each of the two signals from the down conversion mixer 104. The I and O signal components from the IF amplifier 108 are fed into the ADC 110. Each of the [NA 102, the bandpass filter 106 and the IF amplifier 108 have an associated gain as illustrated as G1, G2 and G3 respectively in the figures.

The digital processing is schematically represented as all being performed together in a single digital unit 114 for simplicity, but may include digital signal processing, demodulation and Media Access Control or MAC layer processing.

In Figure 1, there is provided an RSSI unit 112 coupled to the outputs of the IF amplifier 108 so that the signal strength indication is generated the analog domain, typically using analog rectifiers and peak detectors. The RSSI unit 112 is coupled to a further ADC 116 to convert the analog RSSI signal to a digital signal for further processing by the digital processor 114. An AGC unit 134 is provided that is coupled to the RSSI unit 112 so that the AGC Control is directly derived from the analog P551, and is also in the analog domain. A fast response is typically achieved using the configuration illustrated in Figure 1. In this example, only coarse gain control is typically possible and typically an analog filter in the AGC control block is used. Also, only the control of gains Gi and G3 of the [NA 102 and the IF amplifier 108 respectively is implemented. Examples of the type of configuration illustrated in Figure 1 are found in US 6,862,438 B2 [1] and US 7,668,517 B2 [2].

In Figure 2, the P551 unit 112 and ADC 116 are configured as in Figure 1, but an AGC unit 118 is provided on the digital processing side of the transceiver 100. The AGC unit 118 provides AGC directly derived in the digital domain using the digitised PSSI signal, and may use additional signal processing. In the example illustrated in Figure 2, fine gain control is possible, but typically only coarse gain control is implemented and the control relies on dynamic range of a high resolution ADC (»= 8 bit). In some examples, additional control of the [NA 102 gain is implemented (e.g., 2 steps: high -low). Also, only the control of gains Gi and G3 of the [NA 102 and the IF amplifier 108 respectively is typically implemented. A slow response is typically achieved using the configuration illustrated in Figure 2. An example of the type of configuration illustrated in Figure 2 is found in US 6,959,055 B2 [3].

In Figure 3, the PSSI unit 112 and ADC 116 are configured as in Figure 1, but an AGC unit 120 is provided on the digital processing side of the transceiver 100. The AGC control by AGC unit is performed on the digitised signals from the ADC 110. The control of gains G1, G2 and G3 of the [NA 102, the bandpass filter 106 and the IF amplifier 108 respectively may be implemented in examples of this configuration. An example of the type of configuration illustrated in Figure 3 is found in US 6,577,852 B2 [4].

In Figure 4, an RSSI unit 122 and an AGC unit 124 are provided on the digital processing side of the transceiver 100. The computation of the PSSI signal is in the digital domain and may use the ADC converted signals from the ADC unit 110 and/or other digital signal processing performed in the digital processing unit 114. The AGC control signal, obtained by the AGC unit 124, is derived directly from the P551 signal from the RSSI unit 122. The control of gains G1, 02 and 03 of the [NA 102, the bandpass filter 106 and the IF amplifier 108 respectively may be implemented in examples of this configuration. Examples of the type of configuration illustrated in Figure 4 are found in US 7,212,798 B2 [5], US 7,386,285 B2 [6] and US 7,668,523 B2 [7].

In FigureS, the RSSI unit 112 and ADC 116 are configured as in Figure 1. An AGC unit 126 is provided is fed by the digitised signals from the ADC 110 to perform the AGC control. The AGC unit 126 controls the gain Gi of the IF amplifier 108, whereas the [NA 102 gain G3 is controlled by the digital piocessing block 114. The example illustiated in Figure 5 is based on the examples described in GB2472774B [8].

The inventors have found, however, that known approaches do not provide optimum performance in all circumstances and there is therefore desire to provide alternative techniques for deriving a receiver signal strength indicator (value) or RSSI.

SUMMARY OF THE INVENTION

According to a first aspect of the invention there is provided a signal-strength indication apparatus for a receiver, the appalatus comprising: an input unit configured to receive digital gain control signals from a gain control apparatus, the gain control signals being indicative of gain levels for one or more amplifiers of the receiver, and; a signal-strength unit configured to convert the digital gain control signals to digital received signal-strength indicator values.

In accordance with some embodiments the receiver comprises a plurality of amplifiers and the signal-strength unit comprises a combine unit configured to combine i gain control signals from respective ones of the plurality of amplifiers to generate combined digital gain control signals and wherein the digital gain control signals that are converted to digital received signal-strength indicator values comprise the combined digital gain control signals.

In accordance with some embodiments the signal-strength unit comprises an averaging unit configured to average gain control signals over a period of time.

In accordance with some embodiments the signal-strength unit comprises a memory having stored therein one or more look-up-tables associated with the one or more amplifiers and wherein the signal-strength unit is configured to convert the digital gain control signals to digital received signal-strength indicator values based on the one or more look-up-tables.

In accordance with some embodiments the signal-strength unit comprises a correction unit configured to take account of process, voltage and I or temperature measurements when establishing the digital received signal-strength indicator values In accordance with some embodiments the signal-strength unit is configured to invert the gain control signals to obtain the received signal-strength indicator values.

In accordance with some embodiments the signal-strength unit is configured to provide output signalling indicative of the received signal strength indicator values.

In accordance with a second aspect of the invention there is provided a system comprising a signal-strength indication apparatus according to the first aspect of the invention and further comprising a gain control apparatus configured to generate and output gain control signals for the input unit of the signal-strength indication apparatus.

In accordance with some embodiments the gain control apparatus comprises an absolute value conversion unit configured to determine an absolute value of a received signal.

In accordance with some embodiments the received signal includes two quadrature component signals out of phase with one another.

In accordance with some embodiments the gain control apparatus comprises a sampling unit configured to sample the two quadrature component signals at a predetermined sampling frequency.

In accordance with some embodiments the gain control apparatus comprises a maximum determination value unit configured to determine a maximum value for the two quadrature component signals.

In accordance with some embodiments the gain control apparatus comprises a comparison unit configured to compare the maximum value to a predetermined low value threshold and high value threshold and output a signal to indicate if the maximum value is above the high value threshold or below the low value threshold.

In accordance with some embodiments the gain control apparatus comprises a gain value setting unit configured to set gain values based on the received signal from the comparison unit.

In accordance with some embodiments the gain control apparatus comprises a gain value setting unit configured to set gain values using a successive approximation search algorithm.

In accordance with some embodiments the gain control apparatus comprises a gain value tracking unit to monitor the gain values and make incremental adjustments to the gain values based on the tracked gain values.

In accordance with a third aspect of the invention there is provided a receiver comprising a system according to the second aspect of the invention, the receiver further comprising an analog front-end comprising one or more amplifiers, wherein the outputted gain control signals of the gain control apparatus are received by the one or more amplifiers to control the gain of the one or more amplifiers.

In accordance with a fourth aspect of the invention there is provided a method for determining digital received signal-strength values for a receiver, the method comprising: obtaining digital gain control signals from a gain control apparatus of the receiver, the digital gain control signals being indicative of gain levels for one or more amplifiers of the receiver; and determining digital received signal-strength indicator values from the digital gain control signals.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the invention and to show how the same may be carried into effect reference is now made by way of example to the accompanying drawings in which: Figures 1, 2, 3, 4 and 5 of the accompanying drawings illustrate known examples for deriving automatic gain control signals and receiver signal-strength indicator values; Figure 6 illustrates schematically a transceiver according to a first embodiment of the invention; Figure 7 illustrates schematically the transceiver illustrated in Figure 6 with some components removed; Figure 8 illustrates schematically an AGC unit illustrated in Figure 7 in accordance with an embodiment of the invention; Figure 9 is a flow diagram to illustrate how acquisition of gain values is performed; Figure 10 is a flow diagram illustrating a search algorithm for determining a gain value for a low noise amplifier; Figure 11 is a flow diagram illustrating a search algorithm for determining the gain value for a bandpass filter; and Figure 12 illustrates schematically an RSSI unit illustrated in Figure 7 in accordance with an embodiment of the invention.

While the invention is susceptible to various modifications and alternative foims, specific embodiments are shown by way of example in the drawings and are herein described in detail.

It should be understood however that drawings and detailed description attached hereto are not intended to limit the invention to the particular form disclosed but rather the invention is to cover all modifications, equivalents and alternatives falling within the scope of the claimed invention.

DETAILED DESCRIPTION

A receiver in accordance with embodiments of the invention includes an adaptive and dynamic automatic gain control circuit or AGO circuit to allow for a low resolution (e.g., 4 bits) analog-to-digital converter between an analog front-end and a digital processing stage. The dynamic range of the ADC is continuously optimised. For improved digital signal processing (DSP) in a demodulator, the dynamic range of the ADO is optimised for an input signal, and signal noise (or interference). Therefore, all the energy at the ADO input should typically be transferred to a digital signal (i.e., high amplitude at ADO input, but no ADO clipping due to noise and interference), which typically requires both fine AGO resolution and a fast acquisition time for the received analog signal. In this example a packet based communication standard is described with 8 symbols of preamble taking 128 p5, so that the AGO loop needs to adapt and settle quickly so that the preamble can be processed without too many symbols getting lost during signal acquisition. For example, it is preferable that no more than 1 symbol is missed, or the AGO loop takes 16 ps to settle. The gain of a low noise amplifier or LNA used to amplify the received signal is typically proportional to the square root of the current consumed by the [NA, and thus power consumption. Therefore, the AGO should be optimised so that the gain is lowered when input signal strength is above the noise floor by a safe margin.

The received signal strength or RSSI of a receiver in accordance with embodiments of the invention should consume minimal power for the determination of an RSSI value such that digital only processing is preferred to analog processing. This is because analog processing is power-intensive due to the typical use of additional rectifiers and peak detection circuits, and additional anolog-to-digital conversion of an analog signal-strength indicator value.

The specification for an RSSI (or Energy Detection, ED) is dependent on the transmission standard, and in this example the IEEE8O2.15.4 specification is used which includes the following parameters: * Accuracy: ±6 dB; * Dynamic Range: 40 dB (-75 dBm to -35 dBm); and * Measurement Period: 8 symbols (128 ps).

It is noted that this may be considered as a relaxed specification and other applications (for example, ranging) require better accuracy and dynamic range, so the RSSl described herein aims to be better than the specification in the standard identified above.

Figure 6 illustrates schematically a transceiver 1 according to an embodiment of the invention.

The transceiver 1 shown in the figure is an integrated system. The external components include an antenna, an oscillator crystal and a power supply decoupler. That is to say the transceiver may be implemented on one chip, i.e. in a single integrated circuit. However, it will be appreciated that although desirable for cost reasons, a single chip solution is not a technical necessity.

The transceiver 1 illustrated in Figure 6 in general is a transceiver system that is designed to be low power (i.e., low current consumption). The transceiver is designed to have a high dynamic range (-105 dB) for the input signal from the receivel noise floor (-105 dBm) up to the transmitted power (0 dBm). The transceiver 1 utilises a packet based transmission standard that typically uses a fast signal acquisition during a preamble stage at the start of a packet. In this example reference is made to IEEE 802.15.4 standard, but other standards may be used and embodiments of the invention are not limited to this standard. In this example, a low ADC resolution («= 4 bit) is used for low power signal processing and the signal outputted by the ADC is oversampled by a factor of 8. The converted signal in this example is a OQPSK-modulated signal down-converted to intermediate frequency (IF) with constant amplitude, and means there is an 1ADC and a QADO, with a 90 degree phase shift available for processing.

The transceiver 1 has a functional split into two parts, namely a receiver Rx and a transmitter Tx, as well as a hardware split into two parts, namely an analog unit 50 and a digital unit 52.

The analog unit 50 provides a radio frequency (RF) front end for the transmitter and receiver.

The digital unit 52 comprises a digital baseband (BB) processor 54 and a system control unit 56.

The receiver components 2, 6, 10, 12, 18, 22, 24, and 26 are arranged in the upper part of the drawing with the signal path from left to right, and the transmitter components 40, 42, 44 and 46 are arranged in the lower part of the drawing with the signal path from right to left. Both the receiver and transmitter components interact with the higher level control and processing components 30 and 32 visible in the right hand part of the drawing in a control unit 56. The analog RF front end 50 forms the left hand block of the drawing and the digital components in the digital unit 52 form the right hand block of the drawing. As will be appreciated the receiver signal is initially processed with analog components and subsequently processed with digital components, whereas the transmitter signal is initially formed digitally before being processed with analog components.

First the receiver is described. The receiver Rx comprises a low noise amplifier 2 ([NA) at the input connected to an antenna (not shown). The [NA 2 is a high-gain amplifier. The gain of the LNA 2 is controllable. The signal received by the [NA 2 is at a frequency of 2.405 GHz, as specified by the IEEE 802.15.4 standard. The output of the [NA 2 is electrically connected to a down conversion mixer 6 or a passive quadrature mixer. The down conversion mixer 6 combines the amplified signal with quadrature signals I and 0 generated by a quadrature generation unit 4. The quadrature generation unit 4 provides quadrature signals I and 0, where Q is 90 degrees out of phase with I. The quadrature generation unit 4 is driven by a local oscillator 48 (LO), which produces a sine wave output at a frequency of 2.405 0Hz -2 MHz (low side injection), i.e. RF. The LO 48 may be a frequency synthesiser based on fractional-N phase locked loop (PLL) using a 3rd-order signal-delta (>A) modulator. However, it will be appreciated that other oscillators might be used. The LO 48 is also used by the transmitter Tx. The down conversion mixer 6 has two outputs, namely the in-phase component and the out-of-phase component.

The down conversion mixer 6 is connected to a bandpass filter 10 and an IF amplifier 12. The bandpass filter is used as a channel filter for the down-mixed signal. The 11F and OF signal components are fed into a dual input ADC 18.

The digital outputs for the 11F and OF signal components are fed into a digital intermediate frequency-to-baseband (IF-to-BB) down conversion mixer 22. The down conversion mixer 22 is also fed by a Sin/Cos look-up table ([UT) 20. The Sin/Cos [UT 20 provides a digitised version of a sine wave and digitised version of a 90 degree out-of-phase signal, namely a cosine wave.

The Sin/Cos LUT 20 outputs the digitised sine and cosine waves, which have a frequency of 2 MHz, but are processed at a sampling rate of 4 -16 MHz. For the purposes of the following it is assumed that a sampling rate of 16 MHz is used. The digitised sine and cosine signals from the Sin/Cos LUT 20 are multiplied with the 11F and OF signal components in the down conversion mixer 22.

The in-phase and out-of-phase components output from the down conversion mixer 22 are then fed into a low pass filter 24, before being fed into the demodulator 26. The low pass filter 24 removes the IF frequency component from the in-phase and out-of-phase signals fed from the down conversion mixer 22, such that the BB component of each of the in-phase and out-of-phase signals (IBB and OBS) is output. The BB signals 1BB and QBB having a bandwidth of 2 MHz and a chip frequency of 2 MHZ, as specified by the IEEE 802.15.4 standard. The chip frequency or chip rate is used to describe the frequency or rate of the chips in the received signal.

The demodulator 26 is a semi-coherent baseband demodulator. The operation of the semi-coherent baseband demodulator is based on maximum detection of the correlator output, more particularly maximum likelihood (ML) time-delayed double correlation and continuous frequency correction during packet reception.

The demodulated output is in the form of the transmitted packet of bytes of data, as specified by the IEEE 802.15.4 standard, which is fed to an integrated 802.15.4 upper physical layer (PHY) and media access control (MAC) layer unit 30. This is connected to a multipurpose microcontroller 32. The microcontroller 32 may also be connected to at least one input device (e.g. temperature sensor) andtoi at least one controllable device (e.g. heater).

Further details of the demodulator 26 are described in GB2472774B.

The transmittei Tx is now described. The transmitter complises a modulatoi 40 that is connected to the 802.15.4 PHY/MAC unit 30. The 802.15.4 PHY/MAC unit 30 outputs a packet of data to be transmitted in the form of a number of bytes as specified by the IEEE 802.15.4 standard. The modulator 40 is a standard modulator, as is known in the art to produce both the in-phase and out-of-phase components (l--X and Q--X) of the symbols to be transmitted. The symbols to be transmitted are modulated such that the in-phase component l--. comprises the even bits and the out-of-phase component Qr, comprises the odd bits of the 32 chip symbols.

The in-phase and out-of-phase components aie then shaped using half-sine pulse shaping. The in-phase and out-of-phase components shaped with half-sine pulse shaping are then output to an OQPSK-to-MSK converter 42.

The modulated 1Tx and QTx signals are then combined to a minimum shift keying (MSK) foimat in the OQPSK-to-MSK converter 42. The digital output from the OQPSK-to-MSK converter 42 is fed to a MSK 2-point modulator 44, as is known in the art, i.e. a dual-point MSK modulation architecture. Frequency synthesis is provided by the [0 48. The MSK 2-point modulator 44 modulates the LO 48 signal based on the digital output from the OQPSK-to-MSK converter 42.

The modulated signal from the MSK 2-point modulator 44 is fed to a power amplifier (PA) 46, which has programmable output power. PA 46 is connected to an antenna (not shown) for transmission of the signal.

Further details of the transceiver operation, including the demodulator can be found in GB2472774B [8].

The digital part 52 of the transceiver 1, fuithei includes an automatic gain contiol or AGO unit 60 that receives digitised signals from the ADC 18. The AGC unit 60 generates gain control signals, which in this example aie fed to each of the input gain stages, including the LNA 2, the bandpass filter 10 and the IF amplifiei 12. The gain control signals of the AGC unit 60 are also fed to a signal strength unit 62. The signal strength unit 62 may also optionally receive a correction value from the microcontroller 32 to correct for variations in process, voltage and temperature. The receiver signal strength indicator or RSSI signal outputted by the RSSI unit 62 is fed to the integiated 802.15.4 upper physical layei (PHY) and media access contiol (MAC) layer unit 30. The unit 30 outputs a control signal in this example to the ADC 18 to control the resolution (i.e., the number of bits) used by the ADC unit 18.

Figure 7 illustrates schematically the transceiver 1 illustrated in Figure 6, but with some of the components removed for simplicity and ease of explanation. Furthermore, embodiments of the invention apply more generally to the analog front-end 50 of the transceiver and can also be applied to other analog front-ends for other receivers/transceivers and are not limited to the example described herein. Furthermore, the digital intermediate frequency-to-baseband (IF-to-BB) down conversion mixer 22, the Sin/Cos LUT 20 and the low pass filter 24 are also omitted since these are not required for the explanation of the AGC unit 60 and the signal strength unit 62. Also the demodulator 26, the integrated 802.15.4 upper physical layer (PHY) and media access control (MAC) layer unit 30 and multipurpose microcontroller 32 in the digital part of the transceiver are all grouped together in a single block or unit 64.

The AGO unit 60 is illustrated in Figure 7 as receiving the digitised 11F and QIF signal components from ADO 18. The AGO unit 60 is coupled to each of the LNA 2, the channel filter and the IF amplifier 12, and provides gain control signals to each of the gain stages or components. In this example the channel filter 10 and the IF amplifier 12 are separate components, but may form a single apparatus or unit. The RSSI unit 62 receives gain control signals from the AGC unit 60. As mentioned above, the signal strength unit 62 may also optionally receive a correction value from the digital processing unit or block 64.

Each of the [NA 2, bandpass filter 10 and the IF amplifier 12 have an associated gain G1, G2 and G3 respectively, each of which may be described more generally as a gain stage. In this example the three gain stages having the following gain parameters: * G1 (LNA 2): 8-38 dB, comprising 8 non-linear steps (0-7) with a square-root profile; * G2 (bandpass filter 10): 4-36 dB, comprising 9 steps (0-8) of 4dB linear steps; and * G3 (IF amplifier 12): -6 -42 dB comprising 49 steps (0-48) of 1 dB linear steps.

The gain value G1 is described as being a value of 0 to 7, which corresponds to a gain of 8 to 38 dB. In other words, in this example, a gain value of 0 corresponds to a gain of 8 dB, a gain value oil corresponds to a gain of 19 dB, a gain value of 2 corresponds to a gain of 25 dB, a gain value of 3 corresponds to a gain of 29 dB, a gain value of 4 corresponds to a gain of 32 dB, a gain value of 5 corresponds to a gain of 35 dB, a gain value of 6 corresponds to a gain of 37 dB, and a gain value of 7 corresponds to a gain of 38 dB.

The gain value G2 is described as being a value of 0 to 8, which corresponds to a gain of 4 to 36 dB. In other words, in this example, a gain value of 0 corresponds to a gain of 4 dB, a gain value of 1 corresponds to a gain of 8 dB, a gain value of 2 corresponds to a gain of 12 dB, a gain value of 3 corresponds to a gain of 16 dB, a gain value of 4 corresponds to a gain of 20 dB, a gain value of 5 corresponds to a gain of 24 dB, a gain value of 6 corresponds to a gain of 28 dB, a gain value of 7 corresponds to a gain of 32 dB, and a gain value of 8 corresponds to a gain of 36 dB.

The gain value G3 is described as being a value of 0 to 48, which corresponds to a gain of -6 to 42 dB with a linear unitary range for each. In other words, in this example, a gain value of 0 corresponds to a gain of -6 dB, a gain value of 1 corresponds to a gain of-S dB, and so on.

Thus the overall system gain is 6-116 dB and is controllable in 1 dB steps.

The gain G1 of [NA 2 provides a coarse resolution, the gain G2 of bandpass filter 10 provides a medium resolution and gain G3 of IF amplifier 12 provides a fine resolution.

The overall system noise figure may be determined by the Friis' Formula, as provided below: F2-1 F3-1 E=E1+ + Gi G1tG2 where Gi and G2 are the gain values for each of the [NA 2 and the bandpass filter 10 respectively and Fl, F2, F3 are the noise figures for each of the [NA 2, bandpass filter 10 and IF amplifier 12 respectively.

As can be seen from this relationship the [NA noise figure dominates the overall noise figure.

Furthermore, the [NA noise figure is inversely proportional to the [NA current and the [NA gain is proportional to the square root of the [NA current. The [NA gain (and to some extent the bandpass filter) should typically be maximised to maximise system performance and minimise the influence of the bandpass filter noise figure (F2) and the IF amplifier noise figure (F3). It is noted that the front-end power consumption is inversely proportional to the [NA current.

Figure 8 illustrates schematically the AGC unit 60 illustrated in Figure 7 in accordance with an embodiment of the invention. The AGO unit 60 is coupled to the ADO 18 and receives as inputs the digitised I and OF signal components. The AGO unit 60 comprises two absolute value determination units 66, 68 to convert the incoming signals. This is because the incoming 1F and QIF signal components are out-of-phase sinusoidal signals. Therefore, the absolute value determination units 66, 68 will effectively rectifying the signal components in the digital domain.

Thus the incoming signal components have a positive value for a longer period of time such that the AGO unit 60 may be able to determine the gain values in a lower amount of time.

The respective output from each of the absolute value determination units 66, 68 is outputted to a sampler unit 70, 72. The sampler units 70, 72 sample the incoming absolute I and OF signal components (IF1 and IQIFI) at an oversampling rate ot 8 times 2 MHz (16 MHz), which corresponds to the sampling frequency used by the demodulator 26, but it will be appreciated that other oversample ratios or rates may be used.

The sampled signals values of the absolute 11F and QIF signal components aie fed to a maximum determination unit 74. The output of the maximum determination unit 74 is fed to a threshold comparison unit 76, which compares the maximum sample value to a predetermined threshold values. The maximum signal is compared to programmable low and high thieshold values which aie set just within the dynamic iange limits of the ADC. The comparison outputs G_HIGH and G_LOW signals to control the AGC acquisition and tracking algorithm. For example, the threshold comparison unit 76 may comprise two comparators, one to determine if the maximum value is less than the predetermined low threshold value and one to determine if the maximum value is greater than the predetermined high threshold value. The threshold comparison unit 76 unit outputs G_LOW and G_HIGH signals, each in the form of a logic 0 or 1 dependent on the outcome of the comparisons performed on the maximum value received from the maximum determination unit 74. For example, if the maximum value is less than the predetermined low value, the G_LOW signal is 1 and the G_HIGH signal isO, if the maximum value is greater than the predetermined high threshold value, the G_LOW signal is 0 and the G_HIGH signal is 1 and if the maximum value is less than the piedetermined high threshold value and greater than the predetermined low threshold value, both the G_LOW and G_HIGH signal are 0.

The G_LOW and C_HIGH signals are fed to a slope monitor unit 78 and an acquisition/track unit 80. Based on the received G_LOW and G_HIGH signals, the acquisition/track unit 80 will set each of the gains Gi, G2, and G3 using gain controls signals GC_G1, GC_G2,and GC_G3.

It will be appreciated that each ot the signals described in reference to Figure 8 will be in the form of a 8 bit woid in this example. The slope monitor unit 78 monitors the rate of change in signal amplitude and triggers an acquisition cycle if the rate exceeds a threshold rate of change, for example, at the start of a packet being received. For example, the slope monitor unit 78 counts a number of samples over a piedetermined programmable time peiiod and determines if the input signal amplitude is consistently too high (G_HIGH is high) or too low (G_LOW is high) over the time period, If the input signal amplitude is consistently too high or too low for a predetermined time! number of samples, for example for 8 ps (corresponding to 128 samples), the slope monitor outputs an acquire signal to the acquisition/track unit 80 to acquire new gain values.

The operation of the AGO unit 60 is now described.

The AGC unit 60 is working continuously when the receiver is on, and is locked onto the noise floor in the absence of a signal. Acquisition for setting the gain control values Gi, G2 and G3 are all based on modified successive approximation register (SAR) search algorithms, which are optimised here for speed at low input signal strengths, since this is important for DSP preamble synchronisation. At higher signal inputs, the AGO speed is less important, since less preamble symbols are required for synchronisation (i.e., better Signal-to-Noise ratio).

After an initial hold-off time allowing for the front-end analog components to settle when enabled, the ADO converted 1ADC and QADO values are processed by taking the absolute values in the absolute value determination units 66, 68 and sampling the absolute values at the system sampling frequency (16 MHz) over a predetermined number of signal periods (or N samples! which is programmable) using the sampler units 70, 72. The maximum signal value is determined by the maximum determination unit termination unit 74 based on all samples as a measure of signal amplitude, as below: = MaxJIJ,QJ), a' = n-N ton where N is the number of samples and n is an index for the current sample.

It is noted that no averaging at this point is performed. A direct response to a change in signal amplitude from small to large enables the fastest possible response to be achieved at the start of a packet. A delay of N samples from large to small may avoid reaction of the AGO loop to a signal minima. In this example the maximum value is determined over 8 samples. However, other values, for example between 4 and 16 samples, might equally be used.

The maximum M is then compared by the threshold comparison unit 76 to programmable low and high thresholds which are set just within the dynamic range limits of the ADC. The comparison outputs (G_HIGH and G_LOW) are then fed to the AGO acquisition and tracking unit 80.

The AOG unit 60 provides two functions in the form of acquisition and tracking. After initial acquisition when the receiver is enabled and gain values for each of G1, G2 and G3 are set, the slope monitor 78 monitors the rate of change in signal over time and is operable to trigger a re-acquisition of the gain values if the signal cannot reasonably be tracked. For example, when there is a large change in the received signal at the start of an incoming packet, as the gain control is locked onto the noise floor after the receiver has been enabled.

The tracking operation performed by the acquisition/track unit 80 involves monitoring the G-HIGH and G-LOW signals and making small incremental (i.e., increasing or decreasing the gain value by 1) changes to the gain value G3. The tracking may also involve making an incremental change to the gain value G2, but typically if it is no longer possible to track the signal based on changing only the gain value G3, then the acquisition/track unit 80 may acquire new values.

Both acquisition and tracking parts have a programmable time constant to allow the loop to react and the front-end amplification stages to settle, therefore avoiding instability.

Figure 9 is flow diagram used to illustrate how the acquisition of the gain values is performed.

In Step Si, after enabling, the gain value G1 for LNA 2 is determined using a search algorithm which is optimised for speed at low input signals (high gain setting). The highest gain value (G=7, 38 dB) is selected first and tested, as is described below. This implementation is conservative for performance and balanced towards maximum gain. During the gain value 01 search, the bandpass filtei 10 gain value 02 is set to minimum value (.e, set toO or 0 dB). This is done so that the LNA 2 gain is only decreased if a safety margin between noise and incoming signal is achieved at the noise floor, where the bandpass filter 10 gain 02 would be a maximum value. The IF amplifier 12 gain value 03 is set at a programmable nominal value or Vail, which is typically at or below a mid-range value (e.g., 03=20, 14 dB). The process then goes to Step S2.

In Step S2, the gain value G2 for the bandpass filter 10 is determined using a search algorithm, similar to the one used for gain value 01, which is also optimised for speed for high gains (low input signals). A gain value of 0=8 (36 dB) is selected first and tested, as is desciibed below.

During the gain value 02 search, gain value 01 is fixed and gain value 03 for the IF amplifier 12 is to a programmable nominal value Va12, which is typically at or below a mid-range value (e.g., G310, 4 dB). The process then goes to Step S3.

In Step S3, the gain value 03 for the IF amplifier 12 is determined using a search algorithm that is a standard successive approximation register algorithm (based on binary search principles) starting from a mid-range value. During the gain value 03 search, gain values 01 and 02 are fixed. The gain value 03 is influenced by the set gain value for 01 and 02, so the final gain value 03 should be away from the minimum and maximum gain setting, thus helping to avoid ioll-ovei during tracking. The process then goes to Step S4.

In Step S4, and after the acquisition of gain values 01, 02 and 03 is complete, the tracking mode is entered. In the tracking mode, the gain value 03 is decreased by 1 dB if the input signal amplitude is too high, and increased by 1 dB if the input signal amplitude is too low.

During the tracking stage, if the input signal amplitude is consistently too high or too low over a certain programmable time period, for example, over 8 ps (corresponding to 128 samples), it may be taken as an indication that the input signal is changing so quickly that it cannot be effectively tracked any longer, and the acquisition is restarted by going back to Step 51.

If there is a constant, but slow (e.g., at the late of single bit change ovei 8 ys /128 samples), change in the received signal at a rate that can still be tracked, but gain value 03 of the IF amplifier 12 reaches a maximum or minimum value, the gain value 02 of the band pass filter 10 is increased or decreased by one step (i.e., 4dB), and the gain value G3 of the IF amplifier 10 is decreased or increased by 3 dB, resulting in a system gain step of 1 dB, however, this roll-over condition is unlikely.

Figure 10 is a flow diagram illustrating the search algorithm for determining the gain value 01 for the LNA 2, which corresponds to Step Si in Figure 9. The process starts by setting the gain value to a value of 0=7 (Step Sb). The 0_HIGH and 0_LOW values are tested to determine if the gain value is too high or low (Step Si 1). If the gain value is too high, since 0_HIGH is high, the process goes to Step 13, where the gain value is set to 4. If both the 0_HIGH and G_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to Step S12 and ends.

In Step S13, the gain value is set to 4 and the 0_HIGH and 0_LOW values are tested to determine if the gain value is too high or low (Step S14). If the gain value is too high, since 0_HIGH is high, the process goes to Step S21, where the gain value is set to 2. If the gain value is too low, since 0_LOW is high, the process goes to Step S16, where the gain value is set to 6. If both the G_HIGH and G_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to Step S15 and ends.

In Step S16, the gain value is set to 6 and the 0_HIGH and G_LOW values are tested to determine if the gain value is too high or low (Step Sb 7). If the gain value is too high, since G_HIGH is high, the process goes to Step S19, where the gain value is set to Sand the process goes to step 20 and ends. If both the 0_HIGH and 0_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to step S18 and ends.

In Step 521, the gain value is set to 2 and the 0_HIGH and 0_LOW values are tested to determine if the gain value is too high or low (Step S22). If the gain value is too high, since 0_HIGH is high, the process goes to Step S26, where the gain value is set to 1. If the gain value is too low, since 0_LOW is high, the process goes to Step S23, where the gain value is set to 3 and the process goes to Step S24 and ends. If both the 0_HIGH and 0_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to step S25 and ends.

In Step S26, the gain value is set to 1 and the 0_HIGH and 0_LOW values are tested to determine if the gain value is too high or low (Step S27). If the gain value is too high, since 0_HIGH is high, the process goes to Step S29, where the gain value is set to 0 and the process goes to Step 530 and ends. If both the G_HIGH and G_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to Step S28 and ends.

It will be appreciated that when the process ends in the process flow illustrated in Figure 10, the process illustrated in Figure 9 goes to Step S2.

Figure 11 is a flow diagram illustrating the search algorithm for determining the gain value 02 for the bandpass filter 10, which corresponds to Step S2 in Figure 9. The process starts by setting the gain value to the highest value of G=8 (Step S41). The G_HIGH and G_LCW values are tested to determine if the gain value is too high or low (Step S42). If the gain value is too high, since G_HIGH is high, the process goes to Step S43, where the gain value is set to 9 and the process goes to Step S44 and ends. If the gain value is too low, since G_LOW is high, the process goes to Step S46, where the gain value is set to 4. If both the G_HIGH and G_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to step S45 and ends.

In Step S46, the gain value is set to 4 and the 0_HIGH and G_LOW values are tested to determine if the gain value is too high or low (Step S47). If the gain value is too high, since 0_HIGH is high, the process goes to Step S56, where the gain value is set to 2. If the gain value is too low, since G_LOW is high, the process goes to Step S48, where the gain value is set to 6. If both the G_HIGH and G_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to step S55 and ends.

In step S48, the gain value is set to 6 and the G_HIGH and G_LOW values are tested to determine if the gain value is too high or low (Step S49). If the gain value is too high, since 0_HIGH is high, the process goes to Step S52, where the gain value is set to 5 and the process goes to Step 53 and ends. If the gain value is too low, since G_LOW is high, the process goes to Step S50, where the gain value is set to 7 and the process goes to Step S51 and ends. If both the G_HIGH and G_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to step S54 and ends.

In Step S56, the gain value is set to 2 and the G_HIGH and G_LOW values are tested to determine if the gain value is too high or low (Step S57). If the gain value is too high, since 0_HIGH is high, the process goes to Step S61, where the gain value is set to 1. If the gain value is too low, since 0_LOW is high, the process goes to Step S58, where the gain value is set to 3 and the process goes to Step S59 and ends. If both the 0_HIGH and G_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to step 560 and ends.

In step 561, the gain value is set to 1 and the C_HIGH and C_LOW values are tested to determine if the gain value is too high or low (Step S62). If the gain value is too high, since G_HIGH is high, the process goes to Step S64, where the gain value is set to 0 and the process goes to Step S65 and ends. If both the G_HIGH and C_LOW values are low, because the maximum signal is between the predetermined high threshold value and the predetermined low threshold value, the process goes to step 563 and ends.

It will be appreciated that when the process ends in the process flow illustrated in Figure 11, the process illustrated in Figure 9 goes to Step S3.

Figure 12 illustrates schematically the RSSI unit 62 illustrated in Figure 7 in accordance with an embodiment of the invention. The RSSI unit is illustrated as receiving the three gain values from the AGO unit 60, but it will be appreciated that gain values from other forms of AGC may be used and embodiments of the invention are not limited to this example.

The RSSI unit 62 computes a signal strength value directly from the AGO gain setting values and there is no input from the demodulator or DSP illustrated as block 64 in Figure 7, as it is an estimate of the received signal power within the channel bandwidth. It is noted that the RSSI unit 62 may optionally receive a value for PVT correction from the block 64. It is noted that a Link Quality Indication or LQI is different from RSSI, where LQI requires detection of a standard specific signal and thus requires demodulation and/or decoding. The RSSI unit 62 is all digital and does not perform any analog processing and no additional analog-to-digital conversion is required, such that a substantial amount of power may be saved.

The RSSI unit 62 receives as an input each of the gain values 01, 02, and 03 from controls signals CC_Cl, GO_G2 and GC_G3 outputted by the AGO unit 60. Each of the gain values G1, G2 and G3 are fed to a respective look-up-table 01 LUT 82, G2 LUT 84 and 03 LUT 86.

Each of the LUT5 contains values specific to the gain stages that allow the received gain values to be converted and linearized to a signal gain with a resolution of 0.125 dB. The separate values that have been converted using the LUTs are subsequently added to obtain a system gain value.

The RSSI optionally includes a correction block 88 for compensating the summed value received form the summation for Process, Voltage and Temperature variations or PVT using programmable offset and slope correction values. These values may be stored and may also be generated based on an on-chip or remote temperature sensor.

The corrected value is fed to an averaging block 92. The averaging block 92 accumulates the values received from the correction block 88 and computes an average value over a measurement period of N cycles according to the AGO unit 60 update rate determined by the AGO time constant setting. For example, the measurement period may be 128 ps (corresponding to 2048 samples). This can be done either over a programmed measurement period after a start command or continuously in an automatic mode. The timing is shown in the example as being provided by a timing control unit 90, as part of the RSSI unit 62, but may also be provided by other elements of the transceiver 1, such as the microcontroller 32 illustrated in Figure 6.

After the signal has been averaged over a predetermined measurement period, the signal is fed to a conversion unit 94. The conversion unit converts the signal by adjusting and converting the signal from a system gain to a signal strength value (RSSI_VAL), which is subsequently output.

The specific manner of the conversion will depend on the desired parameterisation at hand. In one example the input to the averaging block 92 might comprise a 10 bit parameterisation of the summed AGC values and the input to the conversion unit 94 might comprise a 17 bit parameterisation for average AGO. An RSSI value in one simple implementation might simply be defined as corresponding to the average AGO value subtracted from the maximum average AGC value (e.g. 2'17). Thus a higher AGC average provides a lower RSSI value and vice versa. This kind of inverse relationship for parameterising the RSSI from the AGO follows from the fact that higher signal strengths require lower amplifier gains, and vice versa. It will of course be appreciated that there are any number of different ways of parameterising the RSSI values from the (average) AGO values and the specific relationship used will be an implementation choice, for example, depending on what parameterisations might be expected by higher layer processes. It will be appreciated the RSSI values might be re-digitized to fewer (or more) bits, for example 8 bits, according to the specification used to meet the expectations for RSSI values within the specification at hand. In this example the resulting values represent the signal strength in 1/2 dB steps and can be directly translated to input power in dBm using the following relationship: Pin [dBm] = (RSSI VAL -256)! 2 The resulting performance of the RSSI unit 62 is a full dynamic range from the noise floor (-105 dBm) to saturation (-10 dBm) of 95 dB, a dynamic range for an accuracy of 1 dB from -98 dBm to -16 dBm of 82 dB and an accuracy errorof±1 dB.

The AGO unit 60 described herein provides an all-digital automatic gain control (AGO) of the entire front-end amplification chain. The AGO has a high resolution (1 dB steps) for front-end gain setting over the entire dynamic range, which allows the AGO to operate on a current gain setting and ADC output amplitude and does not require more complex digital signal processing (i.e., averaging or filtering) which would typically be slower. It is noted that high gain control resolution can be implemented with no increase in power consumption, for example, G2 and G3 are constant current, and Gi would be set to a high value if no control. The AGC unit 60 works continuously when the receiver (or transceiver) is on, and is locked onto the noise floor in absence of a signal. A slope monitor monitors the rate of change in signal amplitude, and triggers an acquisition cycle if the rate exceeds a threshold, for example at the start of a packet being received. The acquisition algorithm uses a modified successive approximation for gain selection to rapidly lock onto the signal for low input signal levels. This optimises the acquisition time at the start of a packet when it is required when the signal level is low.

The optimisation of the front-end noise figure versus power consumption in gain control acquisition algorithm is achieved by modifying the [NA gain (which is proportional to the square root of supply current) when it is safe to do so when the signal-to-noise ratio is high. Finally, a direct, digital-only, derivation of RSSI is achieved from the AGC control output plus additional digital signal processing, with no analog RSSI processing required. This is possible due to high resolution of AGC control.

The embodiments have been described as a number of functional blocks. However, it will be appreciated that the blocks may be provided using one or more memory units and logic components or may be implemented in one or more purpose built ASICs or piogrammable arrays. Furthermore, the method may be performed using a general purpose computer having stored thereon instructions to perform the steps described above. Embodiments of the invention may also include a memory device or storage device having stored thereon instructions which when run on an appropriate processor perform the steps described above. It will be appreciated that each the AGC unit 60 and RSSI unit 62 described herein can be used separately.

While the invention is described herein by way of example for several embodiments and illustrative drawings, those skilled in the art will recognize that the invention is not limited to the embodiments or drawings described. It should be understood, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word "may" is used in a permissive sense (i.e. meaning "might") rather than the mandatory sense (i.e., meaning "must"). Similarly, the words "include", "including", and "includes" mean including, but not limited to.

REFERENCES

US 6,862,438 B2 [2] US 7,668,517 B2 [3] US 6,959,055 B2 [4] us 6,577,852 B2 [5] us 7,212,798 B2 [6] us 7,386,285 B2 [7] us 7,668,523 B2 [8] GB2472774B

Claims

CLAIMS1. A signal-strength indication apparatus for a receiver, the apparatus comprising: an input unit configured to receive digital gain control signals from a gain control apparatus, the gain control signals being indicative of gain levels for one or more amplifiers of the receiver, and; a signal-strength unit configured to convert the digital gain control signals to digital received signal-strength indicator values.
2. The apparatus according to claim 1, wherein the receiver comprises a plurality of amplifiers and the signal-strength unit comprises a combine unit configured to combine i gain control signals from respective ones of the plurality of amplifiers to generate combined digital gain control signals and wherein the digital gain control signals that are converted to digital received signal-strength indicator values comprise the combined digital gain control signals.
3. The apparatus according to any one of claims 1 or 2, wherein the signal-strength unit comprises an averaging unit configured to average gain control signals over a period of time.
4. The apparatus according to any one of claims 1, 2 or 3, wherein the signal-strength unit comprises a memory having stored therein one or more look-up-tables associated with the one or more amplifiers and wherein the signal-strength unit is configured to convert the digital gain control signals to digital received signal-strength indicator values based on the one or morelook-up-tables.
5. The apparatus according to any preceding claim, wherein the signal-strength unit comprises a correction unit configured to take account of process, voltage and I or temperature measurements when establishing the digital received signal-strength indicator values
6. The apparatus according to any preceding claim, wherein the signal-strength unit is configured to invert the gain control signals to obtain the received signal-strength indicator values.
7. The apparatus according to any preceding claim, wherein the signal-strength unit is configured to provide output signalling indicative of the received signal strength indicator values.
8. A system comprising a signal-strength indication apparatus according to any one of claims 1 to 7 and further comprising a gain control apparatus configured to generate and output gain control signals for the input unit of the signal-strength indication apparatus.
9. The system according to claim 8, wherein the gain control apparatus comprises an absolute value conversion unit configured to determine an absolute value of a received signal.
10. The system according to any one of claims 8 or 9, wherein the received signal includes two quadrature component signals out of phase with one another.
11. The system according to claim 10, wherein the gain control apparatus comprises a sampling unit configured to sample the two quadrature component signals at a predetermined sampling frequency.
12. The system according to any one of claims 10 or 11, wherein the gain control apparatus comprises a maximum determination value unit configured to determine a maximum value for the two quadrature component signals.
13. The system according to claim 12, wherein the gain control apparatus comprises a comparison unit configured to compare the maximum value to a predetermined low value threshold and high value threshold and output a signal to indicate if the maximum value is above the high value threshold or below the low value threshold.
14. The system according to claim 13, wherein the gain control apparatus comprises a gain value setting unit configured to set gain values based on the received signal from the comparison unit.
15. The system according to any one of claims 8 to 14, wherein the gain control apparatus comprises a gain value setting unit configured to set gain values using a successive approximation search algorithm.
16. The system according to any one of claims 8 to 15, wherein the gain control apparatus comprises a gain value tracking unit to monitor the gain values and make incremental adjustments to the gain values based on the tracked gain values.
17. A receiver comprising a system according to any one of claims 8 to 16, the receiver further comprising an analog front-end comprising one or more amplifiers, wherein the outputted gain control signals of the gain control apparatus are received by the one or more amplifiers to control the gain of the one or more amplifieis.
18. A method for determining digital received signal-strength values for a receiver, the method comprising: obtaining digital gain control signals from a gain contiol apparatus of the leceiver, the digital gain control signals being indicative of gain levels for one or more amplifiers of the receiver; and determining digital received signal-strength indicator values from the digital gain control signals.
19. An apparatus as substantially hereinbefore described with reference to Figures 6 to 12.
20. A method as substantially hereinbefore described with reference to Figures 6 to 12.