GB2500964B - Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration - Google Patents
Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alterationInfo
- Publication number
- GB2500964B GB2500964B GB1300936.0A GB201300936A GB2500964B GB 2500964 B GB2500964 B GB 2500964B GB 201300936 A GB201300936 A GB 201300936A GB 2500964 B GB2500964 B GB 2500964B
- Authority
- GB
- United Kingdom
- Prior art keywords
- loads
- stores
- forward progress
- state alteration
- progress mechanism
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB201336898 | 2012-02-08 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB201300936D0 GB201300936D0 (en) | 2013-03-06 |
| GB2500964A GB2500964A (en) | 2013-10-09 |
| GB2500964B true GB2500964B (en) | 2014-06-11 |
Family
ID=47843561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB1300936.0A Active GB2500964B (en) | 2012-02-08 | 2013-01-18 | Forward progress mechanism for stores in the presence of load contention in a system favoring loads by state alteration |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2500964B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0923031A1 (en) * | 1997-12-11 | 1999-06-16 | BULL HN INFORMATION SYSTEMS ITALIA S.p.A. | Method for reading data from a shared memory in a multiprocessor computer system |
| US20060265466A1 (en) * | 2005-05-17 | 2006-11-23 | Takashi Yasui | Shared memory multiprocessor system |
| US20070083716A1 (en) * | 2005-10-06 | 2007-04-12 | Ramakrishnan Rajamony | Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response |
| US20080215824A1 (en) * | 2005-02-10 | 2008-09-04 | Goodman Benjiman L | Cache memory, processing unit, data processing system and method for filtering snooped operations |
| US7447845B2 (en) * | 2006-07-13 | 2008-11-04 | International Business Machines Corporation | Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality |
| US20090240894A1 (en) * | 2002-08-28 | 2009-09-24 | Intel Corporation | Method and aparatus for the synchronization of distributed caches |
-
2013
- 2013-01-18 GB GB1300936.0A patent/GB2500964B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0923031A1 (en) * | 1997-12-11 | 1999-06-16 | BULL HN INFORMATION SYSTEMS ITALIA S.p.A. | Method for reading data from a shared memory in a multiprocessor computer system |
| US20090240894A1 (en) * | 2002-08-28 | 2009-09-24 | Intel Corporation | Method and aparatus for the synchronization of distributed caches |
| US20080215824A1 (en) * | 2005-02-10 | 2008-09-04 | Goodman Benjiman L | Cache memory, processing unit, data processing system and method for filtering snooped operations |
| US20060265466A1 (en) * | 2005-05-17 | 2006-11-23 | Takashi Yasui | Shared memory multiprocessor system |
| US20070083716A1 (en) * | 2005-10-06 | 2007-04-12 | Ramakrishnan Rajamony | Chained cache coherency states for sequential non-homogeneous access to a cache line with outstanding data response |
| US7447845B2 (en) * | 2006-07-13 | 2008-11-04 | International Business Machines Corporation | Data processing system, processor and method of data processing in which local memory access requests are serviced by state machines with differing functionality |
Also Published As
| Publication number | Publication date |
|---|---|
| GB201300936D0 (en) | 2013-03-06 |
| GB2500964A (en) | 2013-10-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 746 | Register noted 'licences of right' (sect. 46/1977) |
Effective date: 20140619 |