GB2589373A

GB2589373A - Semiconductor device monolithically integrated with a leakage current sense region

Info

Publication number: GB2589373A
Application number: GB1917429.1A
Authority: GB
Inventors: Rahimo Munaf; Nistor Iulian
Original assignee: Mtal GmbH; MQSemi AG
Current assignee: Mtal GmbH; MQSemi AG
Priority date: 2019-11-29
Filing date: 2019-11-29
Publication date: 2021-06-02
Also published as: GB201917429D0

Abstract

Vertical semiconductor device 100 comprises a substrate 40 and a first and second electrical contact 30, 20 on a top and bottom surface 31, 21 of the substrate respectively. An active device area (left side of dashed line) conducts current in an on-state mode, next to a junction termination area (right side of dashed line) for providing the voltage blocking capability. A leakage current sense region 6, formed by a third contact is connected to guard rings 4, 4’ in the termination region. In the off-state mode, a leakage current flows between the first and second electrical contacts and in a lateral direction along the top surface. The leakage current is estimated by detecting a portion of the leakage current flowing though the sense region 6. Sense resistor 8 (Figure 5) is connected to the sense region so that a voltage is produced by the portion of the leakage current.

Description

DESCRIPTION

SEMICONDUCTOR DEVICE MONOLITHICALLY INTEGRATED WITH A

LEAKAGE CURRENT SENSE REGION

FIELD OF THE INVENTION

The subject matter disclosed herein relates to the field of semiconductor devices having a plurality of diode, thyristor or transistor cells, and a monolithically integrated leakage current sense region, and to a circuit with such a power diode, thyristor or transistor for detecting the current flowing in the off-state mode. C\I

CO 15 TECHNICAL BACKGROUND

Semiconductor devices, and in particular high-power semiconductors (diodes, thyristors CD and transistors), are operated with high currents and high voltages, and therefore can become excessively heated. Excessive power dissipation can lead to a high junction temperature of the high-power semiconductors. To protect the semiconductor devices against thermal damage, the leakage current of the semiconductor device in off-state mode is considered one of the most sensitive parameters on which to base some protective action, like for example, to reduce the current flow through the semiconductor device in on-state mode.

Most power semiconductor devices experience different type of failure mechanisms during operation. Many of these failures are related to operational fatigue due to chip and/or packaging issues. There has been a substantial amount of work to predict such failures through current and/or temperature monitoring especially under forward bias conditions ("on-state"). However, based on the industrial experience of the inventor, many of the most critical failures occurring in power semiconductors are related to the reverse bias state ("off-state") in which both high voltages and high electric fields are applied across the semiconductor device. Many operational changes (defects) localised in small regions of the device especially in the junction termination regions can occur during the lifetime of the semiconductor device, and will eventually lead to the failure of the device. One of the most sensitive electrical parameters that could indicate such changes is the leakage current of the semiconductor device in off-state mode. Measuring the leakage current reliably and with good accuracy is not simple due to the very low current levels involved, usually in the range of gA to mA, even at elevated junction temperatures. This is especially challenging when the defect is in a small local area, which can be difficult to detect when the overall leakage current does not show signs of current increase.

Typically, the leakage current can be measured and monitored in reverse bias tests using a large shunt resistance connected in series with the semiconductor device, but this approach is not an option in real applications, i.e. power converters, because this would interfere with the normal flow of current in on-state mode. FIG. 1 shows the cross section of a basic power diode which include an active region and a junction termination region based on a standard floating guard ring concept. In this invention, we provide a new method to measure the leakage current by diverting the current through a distinct conduction path, while separating the leakage current measurement path in off-state mode, from the conducting path of the current in on-state mode.

DISCLOSURE OF THE INVENTION

It may be an object of the present invention to provide a semiconductor device with at an integrated leakage current sense region, where the semiconductor device comprises power semiconductors like diode, transistors and thyristors based on a semiconducting material such as silicon (Si), silicon carbide (SiC) or diamond or gallium oxide (Ga203) or gallium nitride (GaN) or zinc oxide (ZnO) It may also be an object of the present invention to provide methods of protecting the novel semiconductor device.

These objects may be met by the subject matter of the independent claims. Embodiments of the invention are described with respect to the dependent claims.

The problem is solved by the semiconductor device with the characteristics of claim 1.

According to one embodiment the semiconductor device comprises a power diode with a forward biased pn-junction and a main current path. A leakage current sense region is formed by at least one additional electrical contact deposited in the power semiconductor junction termination region, formed in direct contact with the first p-doped guard ring structure. A control circuit is provided being coupled to the leakage current sensor through an external resistor, being adapted to determine a leakage current through the power diode in off-state mode, and to deactivate the current flowing in on-state mode if the leakage current values exceed a corresponding threshold.

According to a further embodiment the semiconductor device is a MOS power transistor comprising a power semiconductor body with plurality of power transistor cells each having a gate electrode, a drain (or collector) region and a source (or emitter) region. The MOS power transistor comprises further at least one leakage current sense region formed by at least one additional electrical contact deposited in the power semiconductor junction termination region, formed in direct contact with one of the p-doped guard ring structures, preferably the first guard ring structure closer to the active area. A control circuit is provided being coupled to the leakage current sensing region through an external resistor, and to the gate electrodes of the plurality of power transistor cells and being adapted to determine a leakage current through the MOS transistor in off-state mode, and to deactivate the power transistor cells or to generate a warning indication, if the leakage current values exceed a corresponding threshold.

According to a further embodiment, a plurality of such power transistors or power diodes (as respective freewheeling diodes) having monolithically integrated leakage current sense regions could also be assembled as a power module, or can be used as discrete devices.

A method for controlling a power transistor comprising a plurality power transistor cells is also disclosed. In one embodiment the power transistor is switched on periodically for at most a maximum on-time. The maximum on-time is short enough to limit the leakage current reachable by the plurality of power transistor cells during the maximum on-time to a value acceptable for the plurality of power transistor cells.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and on viewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will be explained in more detail in the following text with reference to the attached drawings, in which: FIG. 1: Cross section through a typical vertical power diode (prior art).

FIG. 2: Cross section through a typical vertical power diode indicating the current flow

during off-state conditions (prior art).

FIG. 3: Cross section through a power diode according to the invention, including the additional leakage current sense region.

C\I FIG. 4: Cross section through a power diode according to the invention, showing the CO 15 additional leakage current sense region, and the current flow during off-state conditions FIG. 5: Cross section through a power diode according to the invention, showing the additional leakage current sense region, and the current flow during off-state conditions, as well as the external measurement circuitry.

FIG. 6: Cross section through a power diode according to a second embodiment of the invention, showing the additional leakage current sense region.

FIG. 7: Cross section through a power diode according to a third embodiment of the invention, showing the additional leakage current sense region.

FIG. 8: Top view of a power diode layout according to this invention, showing the additional leakage current contact region.

FIG. 9: Top view of a power diode layout according to an additional embodiment of this invention, showing the additional leakage current contact region.

FIG. 10: Circuit symbol and measurement circuit layout of a power diode with additional leakage current sensor according to the new invention.

FIG. 11: Circuit symbol and measurement circuit layout of an Insulated Gate Bipolar Transistor (IGBT) with additional leakage current sensor according to the new invention.

FIG. 12: Reverse bias characteristics for the main part of a power diode, and the leakage current sensor according to the invention.

The reference symbols used in the figures and their meaning are summarized in the list of reference symbols. The drawings are only schematically and not to scale. Generally, alike or alike-functioning parts are given the same reference symbols. The described embodiments are meant as examples and shall not confine the invention.

MODES FOR CARRYING OUT THE INVENTION

In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope C\I 15 of the present invention. The following detailed description, therefore, is not to be taken in CO a limiting sense, and the scope of the present invention is defined by the appended claims.

Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise.

Unless otherwise defined, all terms (including technical and scientific terms) used herein 30 have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e, g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art. However, should the present disclosure give a specific meaning to a term deviating from a meaning commonly understood by one of ordinary skill, this meaning is to be taken into account in the specific context this definition is given herein It will be understood that when an element is referred to as being connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e. g. "between" versus "directly between", "adjacent" versus "directly adjacent," etc.).

Furthermore, any numerical examples in the following discussion are intended to be non-C 15 limiting, and thus additional numerical values, ranges, and percentages are within the scope CO of the disclosed embodiments.

FIG. 2 shows a cross section through a typical power diode (100) comprising a

CD

semiconductor body (1), an anode electrical contact (30) on the anode side (31) and a cathode electrical contact (20) on the cathode side (21). The device consists of an active region (50) and a junction termination region (40). The anode (3) and the guard rings (4) and (4') are usually made of a p-type doped semiconductor material. For simplicity, only two guard ring structures are depicted, and in reality, the power diode may be formed with multiple guard rings (4') to achieve the required high voltage blocking capability. The guard rings are protected at the surface of the anode side (31) with a passivation layer or layers (5). The device blocking capability is primarily defined by the specification in terms of thickness and resistivity (or doping concentration) of the drift region (1). Finally, the highly doped n-type cathode (2) is situated on the cathode side (21). Under off-state or reverse bias conditions, all the leakage current (60) flows from the cathode (20) to the anode (30). It is worthwhile noting that a large proportion of the leakage current originates in the junction termination region (40), and not in the active region (50), and this leakage current is a highly sensitive indicator of the junction temperature, and of the density of defects in the junction termination area. Such defects can be formed during the device operation, and are represented by example of different electrically charged ionic species which diffuse through the layer (5) under high humidity conditions, and accumulate at the interface between layer (5) and the surface of the substrate As indicated in FIG 3, in order to measure or predict irregularities in the leakage current and especially in the junction termination where most of the defects occur, this invention proposes to form an additional leakage current sense region, defined as the electrical contact (6) in direct contact with the first guard ring (4).

As shown in FIG. 4, by positioning the leakage current sense region in the first guard ring, under reverse bias conditions, a significant percentage (arrow 80) of the total leakage current (60) can flow through the contact (6), while the rest of the leakage current will flow (arrow 70) through the main anode contact (30). It is also determined that the level or magnitude of the current flow (80) is significantly dependent on the highly resistive path C\I 15 formed by the drift region (I) encompassed between the edge of the p-doped anode, and the CO first guard ring structure (4). This resistive path has a value which is strongly dependent on O the doping concentration of the drift region (I), and on the distance (7) from the outer most edge of the p-doped anode region to the first p-doped guard ring structure (4). Typical doping concentrations for the drift region range from 101' /cm' up to 9x10' /cm' (i.e. corresponding to a resistivity from 0.5 Ohm-cm to above 1000 Ohm-cm) depending on the voltage blocking rating of the power semiconductor device. The distance (7) can range from 0.5pm up to 50pm.

It is also possible to form the contact (6) on a second, or third, or any other guard ring structure present in the junction termination area except the first guard ring. The contact (6) can also be formed on multiple guard rings simultaneously (not shown in figures). However, as the position of the contact (6) is made further away from the electrode (30), the portion of the leakage current that will flow through this contact will become smaller. In addition, the impact of defects present in the region of the first guard ring may not show in this portion of the leakage current.

The leakage current sense region can be further connected to the emitter (ground) via a sense resistor, comprising of a high series connected shunt resistance (8) that allows direct measurement of the leakage current as a voltage drop across the resistance, as shown in FIG. 5. This measurement can then be utilised by the control circuitry of the applications for monitoring purposes during continuous device operation, or at given time intervals, and is compared to a reference leakage current level to detect atypical variations.

To access the leakage current sense region (6) at the packaging level, a special pad must be included at chip level for wire bonding purposes. As shown in FIG. 8, the special metal pad (9) can be positioned in the active area of the power diode via a metal connection (6') to the main leakage current sense area (6). In yet another embodiment shown in FIG. 9, the metal pad (9) can be positioned outside the operational semiconductor chip regions (i.e. electrically inactive corners of the dies). In both cases, a proper electrical insulation between the leakage current sense regions (6, 6' and 9) and the adjacent regions (Active or Junction Termination) is required (\J 15 The electrical contact (6), sense pad (9) and the electrically conductive path (6') can be CO introduced in the manufacturing process at the same step as the deposition and formation of the main contact (30), by using a slightly modified lithographic mask.

CD Not all power semiconductor devices employ guard ring structures in the junction termination region. Other designs such as junction termination extension, or bevel /mesa designs are also commonly encountered. The innovative concept is applicable for all design options, as long as a high resistivity path for the leakage current is formed across the distance (7) in the drift region (1) between the highly p-doped region (4) and the main electrical contact (30). FIG. 6 shows a second embodiment of the invention, which applies to ajunction termination design using a lightly p-doped extension region (11). FIG. 7 shows a third embodiment of the invention, which applies to a bevel junction termination region with a p-doped region (12) and mechanically bevelled region (13). This type of juncti on termination is typically encountered in high power and very high current power semiconductor devices such as power thyristors, gate turn-off thyristors or GrOs, and Integrated Gate Commutated Thyristors or IGCTs. Other junction termination designs can also be adapted with the new inventive design.

Furthermore, the new design can be employed for different types of power devices such as IGBTS, MOSFETs, 1GCTs, Thyristors, etc based on Silicon or other semiconductor materials such as SiC or GaN The circuit symbol and layout of the new invention is show in figure (10) for the power diode (100) example. Figure (11) shows a similar arrangement for an IGBT (200).

To validate the applicability of the invention, the reverse bias I-V characteristics for the power diode according to the invention are shown in FIG. 12. The total leakage current (60) through the diode (100), the portion (80) flowing only through the leakage current contact (6) and the reminder portion (70) flowing only through the anode contact (30) are depicted at the same junction temperature. The diode voltage rating is equal to 800V, and a series shunt resistance (8) of 1000 Ohm was connected in series with the leakage contact (6). In simulations, a large voltage drop ranging from 0.1 V up to 2 V was recorded across the shunt C 15 resistor in off-state conditions, and the total leakage current was shared by the two electrical CO contacts (6) and (30). Such voltage levels are high enough to be directly measurable through existing methods.

CD Under on-state/conduction conditions, the contact (6) will play no role due to the high resistive path of the shunt resistor, so all the forward current will be carried out through the contact (30) as expected.

The shunt resistor can be implemented with an external stand-alone component, mounted on the chip, or on the substrate of the packaging module, or can be fully integrated in the semiconductor chip.

An additional embodiment refers to a power module comprising of semiconductor devices having the monolithically integrated leakage current sense regions as explained above. The power semiconductor module includes a heat sink, one or more insulated substrates, each including an electrical-conductor pattern formed thereon, these insulated substrates being arranged like tiles on the heat sink, power transistors and power diodes fixed onto insulated substrates; and output terminals connected electrically to insulated substrates.

The power semiconductor module includes further an insulation housing fixed to the heat sink such that the insulated substrates are contained therein; and connector end sections of output terminals and control terminals arranged on the surface of the housing In one further embodiment, the power semiconductor module can also include one or more control circuit boards, also contained in the insulation housing, the control circuit boards being connected to the control terminals of the power transistors, and to the sense pads of the leakage current sense regions. 1 1

Reference list 1: drift region 2: highly doped n-type layer 20: second main side electrical contact 21: second main side 3: highly doped p-type layer 30: first main side electrical contact 31: first main side 4: first guard ring structure 4': additional guard ring structures 5: insulating layers to protect the junction termination region 6: electrical contact for the leakage current sense region 6': electrical contact from the region (6) to the leakage current sense pad (9) C\I 7 distance between the edge of region (3) and the first guard ring structure (4) CO 15 8 shunt resistor 9: leakage current sense pad for wire bonding 11: lightly doped p-type region as junction termination extension 12: lightly doped p-type region in bevel type junction termination 13: bevel region 40: junction termination region of the semiconductor switch 50: active area of the semiconductor switch 60: leakage current flow across the entire semiconductor switch 70: leakage current flow through the main semiconductor switch contacts 80: leakage current flow through the leakage current sense region 100: power diode according to this invention 200: power transistor (ie. IGBT) according to this invention

Claims

CLAIMS1. A semiconductor device having a vertical semiconductor element, the semiconductor device comprising: a semiconductor substrate of first conductivity type; a first electrical contact on a top surface of the substrate; a second electrical contact on the bottom of the substrate; an active device area for conducting the current in on-state mode, next to a junction termination area for providing the needed voltage blocking capability; a leakage current sense region, formed by a third electrical contact connected to one or more guard ring structures located in the junction termination region adjacent to the active area, wherein the guard ring structures are of second conductivity type, in off-state mode, a leakage current flows between the first and second electrical contacts, C\I the leakage current flows in a lateral direction along the top surface of the substrate, co 15 the leakage current at die level is estimated by detecting a portion of the leakage current flowing though the sense region, the sense resistor is connected to the sense region so that a voltage is produced by the portion of the leakage current at a connection point between the sense resistor and the sense region, and the sense wiring layer is located at a region that is electrically isolated from the active area and junction termination regions in the semiconductor device.
2. A semiconductor device with monolithically integrated leakage current sense region according to claim 1, wherein the third electrode is preferably connected to the first guard ring structure in the junction termination area 3. A semiconductor device with monolithically integrated leakage current sense region according to claim I, wherein the active area consists of a power diode.4. A semiconductor device with monolithically integrated leakage current sense region according to claim 1, wherein the active area consists of MOS transistor cells such a MOSFETs, IGBTs with planar, or trench cell types, with reverse-conducting or reverse-blocking capability, or any combination of characteristics mentioned above 5. A semiconductor device with monolithically integrated leakage current sense region according to claim 1, wherein the active area consists of thyristor cells such a GTO or IGCT 6. A semiconductor device with monolithically integrated leakage current sense region according to claim 1, wherein the junction termination area comprises at least one first guard ring structure, and additionally a junction termination extension region, and/or a mechanically bevelled surface.7. A semiconductor device with monolithically integrated leakage current sense region according to claim 1, wherein the portion of the leakage current flowing through the sense region is proportional to the doping of the semiconductor substrate C\I 15 CO 8. A semiconductor device with monolithically integrated leakage current sense regionCDaccording to claim 1, wherein the portion of the leakage current flowing through the sense o region is proportional with the separation distance between the outermost edge of the active area, and the first guard ring structure in the junction termination area.9. A semiconductor device with monolithically integrated leakage current sense region according to claims 1 and 7, wherein the doping of the semiconductor substrate ranges from 1012 /cm' up to 9x10'5 /cm". (corresponding to substrate resistivity values between 0.5 Ohm-cm to above 1000 Ohm-cm) 10. A semiconductor device with monolithically integrated leakage current sense region according to claims 1 and 8, wherein the separation distance between the outermost edge of the active area and the first guard ring structure in the junction termination area ranges from 0.5iim to 50um.11. A semiconductor device according to claim 1, wherein the leakage current which varies with the junction temperature is detected by a control circuit that delivers a control signal for switching off the power transistor, or a warning signal to the user of the semiconductor device, when a predetermined thermal condition is reached 12. A semiconductor device according to claim 1, further comprising: a sense wiring layer or sense pad located on the top of the semiconductor substrate, the wiring layer configured as a top layer of the semiconductor substrate and including a sense wire; and a sense resistor electrically connected to the first electrical contact that is connected to the third electrical contact, wherein the sense wire is directly electrically connected to each of the third electrical contact and the sense resistor.13 A semiconductor device according to claims 1 and 12, wherein a wiring layer or sense pad for the leakage current sense region is provided on top of the power semiconductor C\I 15 device and insulated from the first electrical contact by an interlayer insulation layer.CO14. A semiconductor device according to claims 1 and 12, wherein a wiring layer or sense o pad for the leakage current sense region is provided adjacent the periphery of the power semiconductor device and insulated from the semiconductor substrate by an interlayer insulation layer.15. A semiconductor device power module comprising: a conductive heat sink; a plurality of power transistor dies mounted in thermal conductive relation with the conductive heat sink; each of said power transistor die having a pair of main power terminals and a control terminal operable to turn its respective die on and off; wherein all, or only groups of dies are connected in parallel; a plurality of power diodes in die form; each of the power diodes thermally coupled to the heat sink and respectively connected in parallel with respective ones of the power transistor dies and acting as respective freewheeling diodes; a further leakage current-sense region as defined in claim 1, and sense wiring layer as defined by claim 12 for each power transistor and diode die; a plurality of insulated (polymer, ceramic) substrates with an electrical conductor pattern formed thereon, wherein one or more of power transistors and respective freewheeling diodes are fixed on this conductor pattern; a further sense resistor for each power transistor and diode die, each sense resistor mounted on the respective die or on the insulating substrates supporting the respective dies; wherein the output generated by the leakage current-sense region is defined as the voltage induced across the sense resistor in off-state mode; an insulation housing connected to the thermally conductive heat sink and enclosing each of the power transistors and power diodes dies, and the insulated substrates; a plurality of external power connection terminals fixed to the exterior surface of the insulation housing and electrically connected to the main power terminals of the power transistor and power diodes dies; a plurality of external control terminals fixed to the exterior C\I 15 surface of the insulation housing and electrically connected to the control terminals of the CO power transistors dies; and a plurality of external sense terminals fixed to the exterior surface of the insulation housing, and electrically connected to the sense wiring layers on each of the power semiconductors and to an external control circuit 16 A semiconductor device power module comprising.a conductive heat sink; a plurality of power transistors (in die form or as discrete package) mounted in thermal conductive relation with the conductive heat sink; each of said power transistors having a pair of main power terminals and a control terminal operable to turn its respective device on and off; wherein all, or only groups of transistors are connected in parallel; a plurality of power diodes (in die form or as discrete package) thermally coupled to the heat sink and respectively connected in parallel with respective ones of the power transistors and acting as respective freewheeling diodes; a further leakage current-sense region as defined in claim 1, and sense wiring layer as defined by claim 12 for each power transistor and diode die; a plurality of insulated (polymer, ceramic) substrates with an electrical conductor pattern formed thereon, wherein one or more of power transistors and respective freewheeling diodes are fixed on this conductor pattern; a further sense resistor for each power transistor and diode die, wherein the output generated by the leakage current-sense region is defined as the voltage induced across the sense resistor in off-state mode, and wherein each sense resistor is mounted on the respective power die, on the insulating substrates supporting the respective dies, or on the control circuit board, one or more control circuit semiconductor devices or boards connected to each sense resistor of each of the power transistor and diode dies; the control circuit having input terminals and output terminals; said output terminals of the control circuits being connected between at least one of the main power terminals and the control terminal of their respective power transistor die, said input terminals of the control circuits being connected to the sense wiring layer of the leakage current sensing regions; C\I 15 an insulation housing connected to the thermally conductive heat sink and enclosing each CO of the power transistors and power diodes dies, the insulated substrates, and the control circuit boards; a plurality of external power connection terminals fixed to the exterior surface of the insulation housing and electrically connected to the main power terminals of the power transistor and power diodes dies; a plurality of external control terminals fixed to the exterior surface of the insulation housing and electrically connected to the control terminals of the power transistors dies and to the control circuit board.17. An inverter circuit comprising: a plurality of top switches according to claims 1 thru 5, or a plurality of power modules according to claims 15 or 16 each of which has the power transistor element and the freewheeling diode; and a plurality of bottom switches according to claims 1 thru 5, or a plurality of power modules according to claims 15 or 16, each of which has the power transistor element and the freewheeling diode, wherein each of the plurality of top switches is connected to a corresponding one of the bottom switches to form a of phase leg for converting the electric current into an alternating current; and the leakage current sense region defined in claim I, and the wiring layer defined in claim 12, provided in each or some of the power transistor elements and freewheeling diodes in the plurality of top switches and the plurality of bottom switches.18. The inverter circuit according to claim 17, further comprising: a control circuit configured to turn ON and OFF the power transistor elements by using a predetermined voltage; a leakage current detector configured to detect the leakage current in off-state through each power transistor and freewheeling diode by detecting the voltage induced across the corresponding sense resistors by the portion of the leakage current flowing through the leakage current sense region; C\I 15 a monitoring detector configured to estimate the junction temperature or the defects CO density in the junction termination region of each power transistor element and freewheeling CD diode in the switches, by detecting a change in the leakage current from the induced voltage in the sense resistor produced when the power semiconductors are in the off-state; wherein, the monitoring detector configures the control circuit to turn ON and OFF the power transistor elements, or to trigger a warning message to the user of the inverter, based on the level of the leakage current detected compared to a set of reference values corresponding to nominal operating conditions.