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GB2581945B - Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor - Google Patents

Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor Download PDF

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Publication number
GB2581945B
GB2581945B GB2009499.1A GB202009499A GB2581945B GB 2581945 B GB2581945 B GB 2581945B GB 202009499 A GB202009499 A GB 202009499A GB 2581945 B GB2581945 B GB 2581945B
Authority
GB
United Kingdom
Prior art keywords
order processor
dependency matrix
summary bits
scalable dependency
scalable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2009499.1A
Other versions
GB2581945A (en
GB202009499D0 (en
Inventor
Silberman Joel
Sinharoy Balaram
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/826,746 external-priority patent/US10564976B2/en
Priority claimed from US15/826,734 external-priority patent/US10929140B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB202009499D0 publication Critical patent/GB202009499D0/en
Publication of GB2581945A publication Critical patent/GB2581945A/en
Application granted granted Critical
Publication of GB2581945B publication Critical patent/GB2581945B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
GB2009499.1A 2017-11-30 2018-11-09 Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor Active GB2581945B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/826,746 US10564976B2 (en) 2017-11-30 2017-11-30 Scalable dependency matrix with multiple summary bits in an out-of-order processor
US15/826,734 US10929140B2 (en) 2017-11-30 2017-11-30 Scalable dependency matrix with a single summary bit in an out-of-order processor
PCT/IB2018/058801 WO2019106462A1 (en) 2017-11-30 2018-11-09 Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor

Publications (3)

Publication Number Publication Date
GB202009499D0 GB202009499D0 (en) 2020-08-05
GB2581945A GB2581945A (en) 2020-09-02
GB2581945B true GB2581945B (en) 2021-01-20

Family

ID=66665478

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2009499.1A Active GB2581945B (en) 2017-11-30 2018-11-09 Scalable dependency matrix with one or a plurality of summary bits in an out-of-order processor

Country Status (5)

Country Link
JP (1) JP7403450B2 (en)
CN (1) CN111226196B (en)
DE (1) DE112018006103B4 (en)
GB (1) GB2581945B (en)
WO (1) WO2019106462A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114327643B (en) * 2022-03-11 2022-06-21 上海聪链信息科技有限公司 Machine instruction preprocessing method, electronic device and computer-readable storage medium

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6463523B1 (en) * 1999-02-01 2002-10-08 Compaq Information Technologies Group, L.P. Method and apparatus for delaying the execution of dependent loads
CN101034345A (en) * 2007-04-16 2007-09-12 中国人民解放军国防科学技术大学 Control method for data stream and instruction stream in stream processor
CN102360309A (en) * 2011-09-29 2012-02-22 中国科学技术大学苏州研究院 Scheduling system and scheduling execution method of multi-core heterogeneous system on chip

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6988183B1 (en) * 1998-06-26 2006-01-17 Derek Chi-Lan Wong Methods for increasing instruction-level parallelism in microprocessors and digital system
US7634591B2 (en) * 2006-01-26 2009-12-15 International Business Machines Corporation Method and apparatus for tracking command order dependencies
US8255671B2 (en) 2008-12-18 2012-08-28 Apple Inc. Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependencies
US8099582B2 (en) * 2009-03-24 2012-01-17 International Business Machines Corporation Tracking deallocated load instructions using a dependence matrix
US20140344554A1 (en) * 2011-11-22 2014-11-20 Soft Machines, Inc. Microprocessor accelerated code optimizer and dependency reordering method
US10235180B2 (en) 2012-12-21 2019-03-19 Intel Corporation Scheduler implementing dependency matrix having restricted entries
JP6520416B2 (en) 2015-06-02 2019-05-29 富士通株式会社 Arithmetic processing apparatus and processing method of arithmetic processing apparatus
US10108417B2 (en) 2015-08-14 2018-10-23 Qualcomm Incorporated Storing narrow produced values for instruction operands directly in a register map in an out-of-order processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6463523B1 (en) * 1999-02-01 2002-10-08 Compaq Information Technologies Group, L.P. Method and apparatus for delaying the execution of dependent loads
CN101034345A (en) * 2007-04-16 2007-09-12 中国人民解放军国防科学技术大学 Control method for data stream and instruction stream in stream processor
CN102360309A (en) * 2011-09-29 2012-02-22 中国科学技术大学苏州研究院 Scheduling system and scheduling execution method of multi-core heterogeneous system on chip

Also Published As

Publication number Publication date
WO2019106462A1 (en) 2019-06-06
DE112018006103T5 (en) 2020-09-17
GB2581945A (en) 2020-09-02
JP7403450B2 (en) 2023-12-22
CN111226196B (en) 2023-12-01
CN111226196A (en) 2020-06-02
GB202009499D0 (en) 2020-08-05
JP2021504791A (en) 2021-02-15
DE112018006103B4 (en) 2022-04-21

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Effective date: 20210209