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GB2578998B - Resource allocation - Google Patents

Resource allocation Download PDF

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Publication number
GB2578998B
GB2578998B GB2001798.4A GB202001798A GB2578998B GB 2578998 B GB2578998 B GB 2578998B GB 202001798 A GB202001798 A GB 202001798A GB 2578998 B GB2578998 B GB 2578998B
Authority
GB
United Kingdom
Prior art keywords
resource allocation
allocation
resource
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB2001798.4A
Other versions
GB2578998A (en
GB202001798D0 (en
Inventor
Iuliano Luca
Nield Simon
Chert Foo Yoong
Mower Ollie
Redshaw Jonathan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imagination Technologies Ltd
Original Assignee
Imagination Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imagination Technologies Ltd filed Critical Imagination Technologies Ltd
Priority to GB2001798.4A priority Critical patent/GB2578998B/en
Priority claimed from GB1901486.9A external-priority patent/GB2572248B/en
Publication of GB202001798D0 publication Critical patent/GB202001798D0/en
Publication of GB2578998A publication Critical patent/GB2578998A/en
Application granted granted Critical
Publication of GB2578998B publication Critical patent/GB2578998B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/109Address translation for multiple virtual address spaces, e.g. segmentation
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284Multiple user address space allocation, e.g. using different base addresses
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10Providing a specific technical effect
    • G06F2212/1016Performance improvement
    • G06F2212/1024Latency reduction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65Details of virtual memory and virtual address translation
    • G06F2212/657Virtual address space management
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
GB2001798.4A 2017-09-15 2017-09-15 Resource allocation Active GB2578998B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB2001798.4A GB2578998B (en) 2017-09-15 2017-09-15 Resource allocation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1901486.9A GB2572248B (en) 2017-09-15 2017-09-15 Resource allocation
GB2001798.4A GB2578998B (en) 2017-09-15 2017-09-15 Resource allocation

Publications (3)

Publication Number Publication Date
GB202001798D0 GB202001798D0 (en) 2020-03-25
GB2578998A GB2578998A (en) 2020-06-03
GB2578998B true GB2578998B (en) 2020-12-23

Family

ID=69897281

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2001798.4A Active GB2578998B (en) 2017-09-15 2017-09-15 Resource allocation

Country Status (1)

Country Link
GB (1) GB2578998B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110055511A1 (en) * 2009-09-03 2011-03-03 Advanced Micro Devices, Inc. Interlocked Increment Memory Allocation and Access
US20110087840A1 (en) * 2009-10-09 2011-04-14 Glasco David B Efficient line and page organization for compression status bit caching
US20140281366A1 (en) * 2013-03-15 2014-09-18 Cognitive Electronics, Inc. Address translation in a system using memory striping

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110055511A1 (en) * 2009-09-03 2011-03-03 Advanced Micro Devices, Inc. Interlocked Increment Memory Allocation and Access
US20110087840A1 (en) * 2009-10-09 2011-04-14 Glasco David B Efficient line and page organization for compression status bit caching
US20140281366A1 (en) * 2013-03-15 2014-09-18 Cognitive Electronics, Inc. Address translation in a system using memory striping

Also Published As

Publication number Publication date
GB2578998A (en) 2020-06-03
GB202001798D0 (en) 2020-03-25

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732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20240822 AND 20240828