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GB2575809A - Power Semiconductor device - Google Patents

Power Semiconductor device Download PDF

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Publication number
GB2575809A
GB2575809A GB1811989.1A GB201811989A GB2575809A GB 2575809 A GB2575809 A GB 2575809A GB 201811989 A GB201811989 A GB 201811989A GB 2575809 A GB2575809 A GB 2575809A
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United Kingdom
Prior art keywords
region
semiconductor device
power semiconductor
conduction path
voltage
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Application number
GB1811989.1A
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GB201811989D0 (en
GB2575809B (en
Inventor
Huang Eddie
Koper Nicolaus
Rozman Matijaz
D Wood Stephen
Zhang Jianfeng
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Ween Semiconductors Co Ltd
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Ween Semiconductors Co Ltd
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Priority to GB1811989.1A priority Critical patent/GB2575809B/en
Priority to GB2215522.0A priority patent/GB2609343B/en
Publication of GB201811989D0 publication Critical patent/GB201811989D0/en
Priority to CN201910666400.9A priority patent/CN110767751B/en
Publication of GB2575809A publication Critical patent/GB2575809A/en
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Publication of GB2575809B publication Critical patent/GB2575809B/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/251—Lateral thyristors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/02—Conversion of AC power input into DC power output without possibility of reversal
    • H02M7/04—Conversion of AC power input into DC power output without possibility of reversal by static converters
    • H02M7/12—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/40—Thyristors with turn-on by field effect 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H10D18/60—Gate-turn-off devices 
    • H10D18/65—Gate-turn-off devices  with turn-off by field effect 
    • H10D18/655—Gate-turn-off devices  with turn-off by field effect  produced by insulated gate structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/36—Unipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/231—Emitter or collector electrodes for bipolar transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Dc-Dc Converters (AREA)
  • Thyristors (AREA)
  • Rectifiers (AREA)

Abstract

Power semiconductor device 100 and method of operation. Device 100 comprises semiconductor substrate. Device 100 comprises unipolar conducting structure which comprises first, second and third regions 1, 2, 3 of first conductive type. Region 2 has less doping than regions 1, 3. Device 100 comprises bipolar conducting structure which comprises P-N junction 11 between region 4 of second conductive type opposite to first type and region 2. Device 100 comprises first and second terminals 10, 20. First conduction path P1 between terminals 10, 20 using regions 1, 2, 3. Second conduction path P2 between terminals 10, 20 using region 4, junction 11 and regions 2, 3. Path P1 switched ON and OFF at first frequency using control signal during ON state of device 100. Path P2 operates in high conductivity mode during off-phase (T1, figure 2) of path P1 and in low conductivity mode during on-phase T2 of path P1.

Description

Power Semiconductor Device
Technical Field
The present disclosure relates to a power semiconductor device. More particularly, but not exclusively, the present disclosure relates to a synchronous rectifier for use in power electronics applications.
Background
A power semiconductor device is a semiconductor device used in power electronics applications. Such a device is also called a power device. In general, a power device has a rated voltage (i.e. the potential difference that the device has to withstand in an OFF state between its main terminals) of over 20V and conducts more than 100mA during its ON state. More commonly the ratings of a power device are above 60V and above 1A. These values make the power devices very different from low voltage devices, which operate with voltages typical below 5V and conduct currents typically under 1 mA and more commonly in the range of pAs or sub pAs. Another differentiation between power devices and other types of devices (such as low voltage or radio frequency (RF) devices) is that power devices mainly operate with large signals and behave like switches. An exception to that is found in high voltage or power amplifiers, which include specialised power transistors mainly used in linear operation. It is not uncommon for a power semiconductor device to carry an electric current of the order of around 10A to 3000A in its ON state and to block a voltage of the order of around 100V to 10000V in its OFF state. Commonly used power semiconductor devices include power diodes, thyristors, bipolar junction transistors (BJTs), power metal-oxidesemiconductor field-effect transistors (MOSFET), and Insulated-gate bipolar transistors (IGBT).
Power semiconductor devices are commonly used as switches or rectifiers in power electronics applications. A rectifier is a device that converts alternating current (AC), which periodically reverses direction, to direct current (DC), which flows in only one direction. To achieve this function, the rectifier generally operates in an ON state when a voltage of a particular polarity is applied across the rectifier, thereby allowing a current to flow through the rectifier in a direction corresponding to the polarity of the voltage, and the rectifier operates in an OFF state when a voltage of an opposite polarity (i.e., reverse-bias voltage) is applied across the rectifier, thereby blocking a current to flow therethrough. The rectifier must have a voltage rating higher than the magnitude of the reverse-bias voltage, such that the rectifier will not break down under the reverse-bias voltage.
PN or Schottky diodes are commonly used rectifiers. The use of MOSFETs as synchronous rectifiers in place of PN or Schottky diodes is commonplace in low voltage DC to DC converters. Synchronous rectification means that the MOSFET is actively turned on to allow current in one direction but actively turned off to block current from flowing in the other direction. PN and Schottky diodes have a knee voltage in their conduction l-V characteristics, giving rise to a minimum voltage drop of about 0.7V for PN diodes or about 0.5V for Schottky diodes. In a low voltage converter where the output voltage is less than 5V, a voltage drop of the level of 0.5V to 0.7V across a PN or Schottky diode which is used as a rectifier represents an unacceptable loss of efficiency. The voltage drop may also be referred to as “on-state voltage” of the rectifier. By contrast, a MOSFET, when used as a synchronous rectifier, has a resistive on-state characteristic with no knee voltage. It is then possible to have the onstate voltage of such a synchronous rectifier as low as desired, if a MOSFET with a low on-resistance (RDs(on)) is chosen for a particular circuit condition. For this reason, MOSFETs are commonly used as synchronous rectifiers in low voltage converters which require high efficiency and low power loss.
For rectification in high voltage power electronics applications, such as AC mains rectification, use of MOSFETs as synchronous rectifiers is not nearly as common. This is because the on-resistance of a MOSFET increases rapidly with the voltage rating. For example, for 250V mains rectification at 10A, in order to achieve an on-state voltage significantly lower than the 0.7V on-state voltage achievable by PN diodes, it would require use of a MOSFET with a 600V-800V voltage rating and an on-resistance significantly lower than 70 mQ. This level of on-resistance is achievable using the socalled super-junction structure or compound semiconductors such as silicon carbide (SiC) and Gallium nitride (GaN). However, SiC and GaN semiconductor devices are very expensive to manufacture. For this reason, use of MOSFETs as synchronous rectifiers for mains rectification or other high voltage power electronics applications is still limited to very specialist applications.
Thus there is a need for a cost effective power semiconductor device which can be used as a rectifier in high voltage power electronics applications and also provides low on-state voltage and high efficiency.
It is an object of the present disclosure, among others, to provide such a cost effective power semiconductor device.
Summary
According to a first aspect of the present disclosure there is provided a power semiconductor device, comprising: a semiconductor substrate comprising: a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a lower doping concentration than the first region and the third region; and a bipolar conducting structure comprising a P-N junction formed between a fourth region of a second conductive type opposite to the first conductive type and the second region; a first terminal; and a second terminal. The unipolar conducting structure is operable to provide a first conduction path between the first terminal and the second terminal using the first, second and third regions. The bipolar conducting structure is operable to provide a second conduction path between the first terminal and the second terminal using the fourth region, the P-N junction, the second region and the third region. The first conduction path is configured to be switched on and off at a first frequency under application of a control signal during an ON state of the power semiconductor device, and the second conduction path is configured to operate in a high conductivity mode during an off-phase of the first conduction path and to operate in a low conductivity mode during an on-phase of the first conduction path.
By providing a bipolar conducting structure and a unipolar conducting structure on the same semiconductor substrate which share a common lowly doped second region designed to achieve a high voltage rating, and by alternating conduction through a first conduction path provided by the unipolar conducting structure and a second conduction path provided by the bipolar conducting structure at a first frequency, the conduction of the bipolar conducting structure during an off-phase of the first conduction path allows the on-state voltage of the unipolar conducting structure to be reduced during the on-phase of the first conduction path. Accordingly, advantageously, the device can achieve an average on-state voltage which is lower than each of the onstate voltage of the bipolar conducting structure and the original on-state voltage of the unipolar conducting structure. Therefore, the device can achieve high efficiency and low power loss.
It will be understood that the term “terminal” may be used interchangeably with “electrode”.
It will be understood that the unipolar conducting structure refers to a semiconductor structure which uses only one type of charge carriers during electrical conduction. For example, a MOSFET and a Schottky diode are unipolar conducting structures. Because the charge carriers involved are the majority carriers, the unipolar conducting structure may also be referred to as a majority carrier conducting structure.
The first conduction path may be an electrically resistive conduction path.
The bipolar conducting structure refers to a semiconductor structure which uses both types of charge carriers (i.e., electrons and holes) during electrical conduction. For example, a bipolar junction transistor (BJT), a thyristor, an IGBT and a PN junction diode are bipolar conducting structures. Because both majority and minority carriers are involved during the conduction of the bipolar conducting structure, the bipolar conducting structure may also be referred to as a minority carrier conducting structure.
The term “low conductivity mode” refers to a situation when a forward bias voltage lower than the forward threshold voltage is applied across the PN junction, and the term “high conductivity mode” refers to a situation when a forward bias voltage higher than the forward threshold voltage is applied across the PN junction. Generally speaking, the current level through the PN junction during the low conductivity mode is much lower than the current level during the high conductivity mode. Therefore, the PN junction may also be considered as being “turned off” during the low conductivity mode.
The second region may be configured to receive conductivity modulation due to carriers injected from the fourth region into the second region when the second conduction path operates in the high conductivity mode.
The first conduction path may be in parallel to the second conduction path.
This parallel arrangement allows the unipolar conducting structure to have the benefit of conductivity modulation due to the conduction of the bipolar conducting structure, yet without introducing a knee voltage of the bipolar conducting structure into the conduction characteristics of the entire ON state of the device.
The power semiconductor device may be operable to have an ON state during which an electric current flows between the first and second terminals using at least one of the first and second conduction paths, and an OFF state during which an electric current does not flow between the first and second terminals.
The power semiconductor device may be a synchronous rectifier. The power semiconductor device may be operable in an ON state upon application of a voltage of a first polarity between said first and second terminals, and may be operable in an OFF state upon application of a voltage of a second polarity between said first and second terminals, the second polarity being opposite to the first polarity.
The control signal may be synchronised with the polarity of a voltage applied between the first and second terminals.
The semiconductor substrate may be a monolithic silicon substrate. The first to fourth regions may be regions of the silicon substrate doped with different types and/or different levels of impurities.
The third region may have a first surface and a second surface opposite to the first surface. The second terminal may be electrically coupled to the second surface of the third region.
The second region may be disposed on the first surface of the third region.
The second region may have a first surface and a second surface which is opposite to the first surface and faces the third region.
The first region may be disposed adjacent to the first surface of the second region.
The fourth region may be disposed within the second region. In an example, the fourth region may be disposed adjacent to the first surface of the second region. Alternatively, the fourth region may be disposed around walls of at least one trench located in the second region.
A time duration of the on-phase of the first conduction path may be configured to be longer than a time duration of the off-phase of the first conduction path during the ON state of the power semiconductor device.
A time duration of the on-phase of the first conduction path within at least one cycle of the control signal may be shorter than a time duration during which a fraction of the injected carriers disappear through recombination with majority carriers of the second region.
The fraction of the injected carriers may be a substantial fraction of the injected carriers. Optionally, the fraction may be of a value between 50% to 95%.
In use, the first and second terminals may be configured to be connected to an AC voltage of a second frequency so as to rectify the AC voltage, and the first frequency may be higher than the second frequency.
The first frequency may be at least two times higher than the second frequency. The first frequency may be between 10KHz to 1 MHz.
The unipolar conducting structure may comprise a metal-oxide-semiconductor (MOS) gate structure. The MOS gate structure may comprise a channel region of the second conductive type disposed between the first region and the second region, and a gate electrode for generating an electric field in the channel region to invert the conductivity type of the channel region so as to form a conducting channel between the first and second regions.
A portion of the fourth region proximate to the P-N junction may have a doping concentration higher than that of the channel region.
The gate electrode may be configured to receive the control signal to switch on and off the conducting channel so as to switch on and off the first conduction path.
The power semiconductor device may further comprise a switch connectable between the first terminal and the first region. The switch may be configured to receive the control signal to switch on and off the first conduction path.
The first region may be in direct contact with the second region. The power semiconductor device may further comprise a switch connectable between the first terminal and the first region. The switch may be configured to receive the control signal to switch on and off the first conduction path.
The power semiconductor device may comprise a first electrode portion electrically connected to the fourth region and a second electrode portion electrically connected to the first region. The term “electrode portion” may be used interchangeably with the term “metallisation contact”. The first electrode portion may be spaced apart from the second electrode portion. The switch may be electrically connected between the first terminal and the second electrode portion. The first electrode portion may be electrically connected to the first terminal.
The switch may be a low-voltage switch. It will be understood that the term “low-voltage switch” means that the switch has a voltage rating (e.g. less than 20V) which is lower than a voltage rating of the power semiconductor device.
The switch may be formed on a further semiconductor substrate separate from the semiconductor substrate. The semiconductor substrate and the further semiconductor substrate may be enclosed in a single package.
The fourth region may comprise a plurality of fourth sub-regions spaced apart from one another. At least some of the fourth sub-regions may be operatively connected to the first terminal and form P-N junctions with the second region.
The fourth sub-regions may be spaced apart from one another at a distance which is configured such that upon application of the voltage of the second polarity to said first and second terminals, depletion regions of the P-N junctions within the second region corresponding to adjacent fourth sub-regions collectively pinch off the first conduction path.
The first region may comprise at least one first sub-region spaced apart from one another, and the at least one first sub-region may be disposed between adjacent ones of the fourth sub-regions. The at least one first sub-region may be spaced apart from the adjacent ones of the fourth sub-regions.
The power semiconductor device may further comprise a trench which is disposed within the second region. At least one of the fourth sub-regions may be disposed adjacent to at least one wall of the trench.
The power semiconductor device may further comprise a metallisation contact electrically connected to the at least one of the fourth sub-regions. The metallisation contact may be operatively connected to the first terminal and at least a part of the metallisation contact may be disposed within the trench.
Alternatively, the first region may comprise at least one first sub-region spaced apart from one another, and the at least one first sub-region may be disposed within one of the fourth sub-regions and has a boundary substantially aligned with a boundary of the one of the fourth sub-regions such that the at least one first sub-region is in direct contact with the second region.
The doping concentration and a thickness of the second region may be configured such that the power semiconductor device is able to support a voltage with an amplitude of, but not limited to, 600V to 800V between the first and second terminal during an OFF state of the power semiconductor device.
According to a second aspect of the present disclosure there is provided a method of operating a power semiconductor device, the power semiconductor device comprising: a semiconductor substrate comprising: a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a doping concentration lower than that of the first region and the third region; and a bipolar conducting structure comprising a P-N junction formed between a fourth region of a second conductive type opposite to the first conductive type and the second region; a first terminal; and a second terminal; the method comprising: providing a first conduction path between the first and second terminals using the first, second and third regions; applying a control signal to switch on and off the first conduction path at a first frequency during an ON state of the power semiconductor device; and providing a second conduction path between the first and second terminals using the fourth region, the P-N junction, the second region and the third region; wherein the second conduction path operates in a high conductivity mode during an off-phase of the first conduction path and operates in a low conductivity mode during an on-phase of the first conduction path during the ON state of the power semiconductor device.
Where appropriate any of the optional features described above in relation to one of the aspects of the present disclosure may be applied to another one of the aspects of the disclosure.
It will be appreciated that the power semiconductor device of the present disclosure is applicable in various power electronics applications, not limited to the use in power rectification as a synchronous rectifier.
Brief Description of the Drawings
In order that the disclosure may be more fully understood, a number of embodiments of the disclosure will now be described, by way of example, with reference to the accompanying drawings, in which:
Fig. 1 is a schematic representation of a cross-section of a power semiconductor device according to a first embodiment of the present disclosure;
Fig. 2 is a schematic representation of input and output waveforms during the ON state of the power semiconductor device of Fig. 1;
Fig. 3 is a schematic representation of a cross-section of a power semiconductor device according to a second embodiment of the present disclosure;
Fig. 4 is a schematic representation of a cross-section of a power semiconductor device according to a third embodiment of the present disclosure;
Fig. 5 is a schematic representation of a partial cross-section of a power semiconductor device which is alternative to a partial cross-section of the third embodiment of the present disclosure;
Fig. 6 is a schematic representation of a cross-section of a power semiconductor device according to a fourth embodiment of the present disclosure;
In the drawings, like parts are denoted by like reference numerals. Further, in each drawing, a part denoted by a reference numeral in the format of N-i has equivalent characteristics to another part denoted by a reference numeral N.
It will be appreciated that the drawings are for illustration purposes only and are not drawn to scale.
Detailed Description of the Preferred Embodiments
Fig. 1 schematically illustrates a cross-section of a power semiconductor device 100 according to a first embodiment of the present disclosure. The device 100 includes an N+ silicon substrate 3. An electrode 20 is electrically coupled to the bottom surface of the substrate 3. A lowly doped N- drift region 2 (e.g. with a doping concentration of about 1013 cm-3 to 1015 cm'3) having a thickness t2 is disposed on the top surface of the substrate 3. The N- drift region 2 may be an epitaxial layer. The thickness t2 may, for example, be of the order of tens of micrometres (pm). It will be appreciated that the particular value of the thickness t2 depends upon the voltage rating of the device 100.
A P+ well 4 is provided in the N- drift region 2 adjacent to a top surface of the N- drift region 2. A N+ region 1 is provided in the P+ well 4 and is also adjacent to the top surface of the N- drift region 2. The “top surface” and the “bottom surface” used above may also be referred to as “a first surface” and “a second surface” which is opposite to the first surface, respectively. The P+ well 4 and the N+ region 1 may be formed by double diffusion processes. The N- drift region 2 has a lower doping concentration than the substrate 3 and the N+ region 1. An electrode 10 is electrically coupled to both of the N+ region 1 and the P+ well 4.
The N+ region 1, the N- drift region 2, the substrate 3 and the P+ well 4 may also be referred to as the “first region”, the “second region”, the “third region” and the “fourth region” of the device 100, respectively. These regions are formed by doping respective impurities into silicon. The electrodes 10 and 20 may be referred to as the “first electrode” and the “second electrode” of the device 100, respectively, or the “first terminal” and the “second terminal” of the device 100, respectively.
The device 100 further includes a MOS gate structure, which includes an insulated gate 6, a channel region 5 along a top surface of the P+ well 4 between the N+ region 1 and the N- drift region 2 and a gate oxide layer 7 between the gate 6 and the channel region 5. A gate electrode 30 is electrically coupled to the gate 6. When a positive voltage is applied between the gate electrode 30 and the first electrode 10 (i.e., the potential at the gate electrode 30 is higher than the potential at the first electrode 10), the electric field generated by the voltage penetrates through the oxide layer 7 and inverts the conductivity type of the channel region 5 so as to create an N-type inversion layer (i.e., an N channel) at the interface between the P+ well 4 and the oxide layer 7. The inversion layer provides a conductive channel through which a current can flow between the N+ region 1 and the N- drift region 2.
Therefore, when a positive voltage is applied between the gate electrode 30 and the first electrode 10, there is provided a first conduction path P1 between the first electrode 10 and the second electrode 20, via the N+ region 1, the inverted channel region 5, the N- drift region 2 and the N+ substrate 3.
Similar to a typical MOSFET, the first conduction path P1 uses only one type of charge carriers, i.e., electrons, for the electrical conduction. Electrons are the majority carriers of the N+ region 1, the inverted channel region 5, the N- drift region 2 and the N+ substrate 3. Therefore, the first conduction path P1 may also be referred to as a unipolar conduction path or a majority carrier conduction path. Accordingly, the N+ region 1, the N- drift region 2, the N+ substrate 3, the channel region 5, and the MOS gate structure collectively form a unipolar conducting structure.
As the first conduction path P1 is resistive, the on-state characteristic of the unipolar conducting structure has no knee voltage. The first conduction path P1 works equally well with current flowing from the first electrode 10 to the second electrode 20 or from the second electrode 20 to the first electrode 10. The on-resistance (RDs(on)) of the unipolar conducting structure includes the resistance of the N+ region 1, the resistance of the inverted channel region 5, the resistance of the N- drift region 2, and the resistance of the N+ substrate 3, which are connected in series with each other.
A relatively thick and lowly doped N- drift region 2 is necessary for the unipolar conducting structure to block a high voltage applied between the electrodes 10 and 20. Such a lowly doped region therefore has high resistivity. The series resistance in the Ndrift region 2 increases with the voltage rating of the device 100 and typically represents the biggest contribution to the total on-resistance of the first conduction path P1. Meanwhile, the presence of the lowly doped N- drift region 2 is necessary in order for the device 100 to achieve a high voltage rating, and it is not feasible to embed (e.g., by diffusion process) more impurities (e.g., Phosphorus) into the drift region 2 to increase its doping concentration. Therefore, the lowly doped N- drift region 2 poses as a challenge for reducing the voltage drop across the unipolar conducting structure during the conduction of the path P1.
As shown in Fig. 1, a PN junction 11 is formed along the interface between the P+ well 4 and the N- drift region 2. Therefore, there also exists a second conduction path P2 between the first electrode 10 and the second electrode 20, via the P+ well 4, the PN junction 11 and the N- drift region 2. The first conduction path P1 and the second conduction path P2 are connected in parallel between the electrodes 10 and 20.
The second conduction path can be switched on by applying a positive voltage between the first electrode 10 and the second electrode 20 (i.e., the potential at the first electrode 10 is higher than the potential at the second electrode 20) to forward bias the PN junction 11. Because diffusion of both electrons and holes are involved during the conduction of the second conduction path P2, the second conduction path P2 may also be referred to as a bipolar conduction path or a minority carrier conduction path. Accordingly, the P+ well 4, the PN junction 11 and the N- drift region 2 collectively form a bipolar conducting structure. Due to the PN junction 11, there exists a knee voltage of around 0.7V in the conduction l-V characteristics of the bipolar conducting structure. The knee voltage is determined by the nature of the bipolar conducting structure and cannot be eliminated.
The device 100 may be used as a synchronous rectifier having an ON state and an OFF state.
The OFF state takes place when the device 100 is reverse-biased (e.g., the potential at the first electrode 10 is lower than the potential at the second electrode 20). In order to achieve the OFF state, both the paths P1 and P2 must be kept off. The path P1 can be turned off by applying a low voltage (including 0V) to the gate electrode 30 such that the voltage difference between the gate electrode 30 and the first electrode 10 become lower than the threshold voltage for making the N channel within the channel region 5 (which means the path P1 cannot be established in the OFF state). The PN junction 11 of the path P2 is naturally reverse-biased when the potential at the first electrode 10 is lower than the potential at the second electrode 20, and therefore the path P2 cannot conduct current as well. Accordingly, a current cannot flow from the second electrode 20 to the first electrode 10 and the device operates in the OFF state.
The ON state takes place when a positive voltage is applied between the first electrode 10 and the second electrode 20. In order to achieve the ON state, at least one of the paths P1 and P2 is generally turned on. The path P1 can be turned on by applying a relatively high voltage to the gate electrode 30 such that the voltage difference between the gate electrode 30 and the first electrode 10 become higher than the threshold voltage for making the N channel. Further, the PN junction 11 of the path P2 is naturally forward-biased when the potential at the first electrode 10 is higher than the potential at the second electrode 20. In this way, a current can flow from the first electrode 10 to the second electrode 20 via one or both of the paths P1 and P2.
The voltage applied to the gate electrode 30 is generally synchronised with the polarity of a voltage applied between the first electrode 10 and the second electrode 20. Therefore, the ON/OFF state of the device 100 can change in accordance with the change in the polarity of a voltage applied between the first electrode 10 and the second electrode 20.
As described above, the voltage drop along the path P1 may be substantial due to the highly resistive N- drift region 2, and the path P2 suffers from a knee voltage of around 0.7V which cannot be eliminated. In order to reduce the on-state voltage of the device 100 (i.e., the voltage drop between the first electrode 10 and the second electrode 20 during the ON state), the device 100 is controlled to dynamically increase the charge carrier concentration of the N- drift region 2, thereby decreasing the resistance of the
N- drift region 2 (without actually embedding or diffusing more impurities into the region 2) during the ON state of the device 100. This is described in more detail below.
Fig. 2 illustrates waveforms of a voltage VGS applied between the gate electrode 30 and the first electrode 10, and the resulting on-state voltage V0N between the first electrode 10 and the second electrode 20, during the ON state of the device 100. For illustration purposes only, the time period of the ON state is shown as t0NAs shown in Fig. 2, instead of having the gate 6 biased positive constantly to induce the presence of the N channel during the whole period toN of the ON state, a fast switching on-off pulse VGS is applied to the gate electrode 30 to periodically switch on and off the N channel within the channel region 5, thereby periodically switching on and off the first conduction path P1. The frequency of VGS may be, for example, between 10 kHz and 10 MHz. The on/off frequency of the N channel and the first conduction path P1 is substantially the same as the frequency of VGS.
The period of VGS is T, which includes an off-phase T1 during which the N channel is switched off and an on-phase T2 during which the N channel is switched on.
During the off-phase T1, the first conduction path P1 is switched off, but the second conduction path P2 is still on since the first electrode 10 has a higher potential than the second electrode. Therefore, current will flow along the second conduction path P2 through the bipolar conducting structure. Due to the existence of the PN junction 11, the on-state characteristics has a knee voltage and therefore the on-state voltage V0N during off-phase T1 is around 0.7V.
Conduction via the bipolar conducting structure during the off-phase T1 injects minority carriers (i.e., holes in the device 100) into the N- drift region 2, enhancing the conductivity of the N- drift region 2. Due to the quasi-charge neutrality constraint, the injected minority carriers will also lead to an increase in majority carriers (i.e., electrons) in the N- drift region 2 during the subsequent on-phase T2 as explained below. In this way, the effective doping of the N- drift region 2 is temporarily increased to a much higher level than the actual doping concentration of the N- drift region 2, thereby lowering the resistance of the N- drift region 2. This effect is referred to as conductivity modulation of the N- drift region 2.
When the N channel is turned on during the on-phase T2, both the first conduction path P1 and the second conduction path P2 are conducting at the beginning of the on-phase T2. It will be appreciated that current will tend to flow through a path having a lower resistance. Due to conductivity modulation received by the N- drift region 2 during the off-phase T1, the instantaneous on-resistance of the first conduction path P1 has been greatly reduced from its normal level, since the biggest contributor to this resistance the N- drift region 2 - has its effective resistance reduced by the presence of injected minority carriers. Therefore, current tends to flow through the first conduction path P1 and the instantaneous on-state voltage of the path R1 drops to a level which is much lower than the knee voltage of the path P2. The level of V0N is illustrated as being about 0.1V in Fig. 2 as an example, but may vary depending on the configuration of the unipolar conducting structure and the current density flowing through the path P1.
Because the instantaneous on-state voltage of the path P1 is lower than the forward threshold voltage (around 0.7V) of the PN junction 11 of the path P2, conduction via the path P2 will cease or enter a very low conductivity mode. It will be appreciated that if a forward bias voltage lower than the forward threshold voltage is applied between the PN junction, the PN junction is still able to conduct a small current (which may be around or lower than several mA) and is not strictly off. Therefore, the term “low conductivity mode” refers to a situation when a forward bias voltage lower than the forward threshold voltage is applied across the PN junction 11, and the term “high conductivity mode” refers to a situation when a forward bias voltage higher than the forward threshold voltage is applied across the PN junction 11. Generally speaking, the current level through the PN junction 11 during the low conductivity mode is much lower than the current level during the high conductivity mode. Therefore, the PN junction may also be considered as being turned off during the on-phase T2, and being turned on during the off-phase T1.
With the on-phase T2 continuing, the minority carriers injected into the N- drift region 2 begin to disappear through recombination with the majority carriers within the N- drift region 2. Therefore, the effective resistance of the N- drift region 2 increases during the on-phase T2 as shown in Fig. 2, causing the on-state voltage of the device 100 to gradually increase over time.
Typically, the minority carrier lifetime in the N- drift region 2 is such that the recombination process occurs over several microseconds. In an example, the recombination process may take at least around 10 microseconds. It will be appreciated that preferably the time duration of the on-phase T2 is shorter than the lifetime of the injected minority carriers. In a further example, the time duration of the on-phase T2 may be shorter than a time duration during which a fraction of the injected carriers disappear through recombination. The fraction may be a substantial fraction and may have a value, for example, between 50% to 95%.
By switching the N channel and the first conduction path R1 on and off at a suitably high frequency, the minority carriers injected into the N- drift region 2 during the offphase T1 may be mostly present for the whole of the on-phase T2, thereby causing the on-state voltage of the path P1 to stay low throughout the entire on-phase T2. As shown in Fig. 2, the on-state voltage gradually rises as the injected carriers recombine during the on-phase T2, but before the on-state voltage has significantly increased the N channel is turned off again causing the second conduction path P2 to turn on, thereby “replenishing” the injected carriers of the N- drift region 2. Further, during the on-phase T2, the dominant conduction path (i.e., the first conduction path P1) is purely resistive, and does not have any PN junction and therefore has no knee voltage.
Fig. 2 shows that the on-phase T2 has a longer time duration than the off-phase T1. The exact ratio of the off-phase T1 and the on-phase T2 can be optimised to obtain the maximum benefit. In general, optimum performance may be obtained by having the offphase T1 as short as possible but long enough to have established a high level of conductivity modulation in the N- drift region 2, and by having the on-phase T2 as long as possible without letting the on-state voltage rise too much from its initial low value. In this way, the average on-state voltage of the device 100 is much lower than the typical 0.7V knee voltage of a PN junction. The device 100 therefore can achieve a performance comparable with the performance achieved by super-junction structures or compound semiconductors, but can be manufactured in a more cost-effective manner than super-junction structures or compound semiconductors.
It will be appreciated that the N- drift region 2 is preferably made of a semiconductor material with a relatively high minority carrier lifetime. This allows the time duration of the on-phase T2 to be extended with respect to the time duration of the off-phase T1.
Accordingly, the average on-state voltage of the device 100 can be further reduced to a lower level, due to the very low on-state voltage provided by the path P1 during the onphase T2.
High minority carrier lifetime within the N- drift region 2 may be achieved by using a low defect-density silicon structure as the material of the N- drift region 2. In an example, a back-diffused homogeneous wafer is used as the starting material for making the device 100, in which the N- drift region 2 is already provided by the wafer and would not be an epitaxial layer made by an epitaxial process on the substrate 3. The N- drift region 2 made in this way has a low defect density, and thus the minority carrier lifetime in the N- drift region 2 is relatively high. In a further example, the N- drift region 2 is an epitaxial layer made by an epitaxial process, and an annealing process is performed to reduce the structural defects in the epitaxial layer.
For example, the time duration of the off-phase T1 may be from several nanoseconds to several microseconds. It has been found that there exists a minimum time duration of the off-phase T1 in order to allow the PN junction 11 to conduct so as to fully modulate the conductivity of the N- drift region 2. Further, it has been found that prolonging the minimum time duration may not necessarily further enhance the conductivity of the N- drift region 2. The minimum time duration varies with the particular doping and thickness configurations of the device 100, the current density flowing through the device 100, the operating temperature, and other external conditions, and may typically be within the range of 0.5 to 2 microseconds. The time duration of the on-phase T2 may preferably be around 5 to 15 microseconds. The duty cycle of the signal VGS which produces low V0N is generally in the range of 80% to 95%. It will be appreciated that the particular figures of the time periods and the duty cycle described above are examples only, and the practical operation of the device 100 is in no way limited to those figures.
Fig. 2 shows that the time duration t0N of the ON state of the device 100 is more than three times the period T of VGS. It will be appreciated that this is merely for illustration, and that the time duration t0N may be equal to i*T, with i being a number equal to or larger than one.
Conductivity modulation is also used in bipolar power devices (such as thyristors, IGBT). However, the device 100 provides advantages over bipolar power devices in that the device 100 is able to achieve an on-state voltage lower than the knee voltage of a PN junction. As set out above, during the ON state of the device 100, current flowing through the device 100 alternates between the first conduction path P1 and the second conduction path P2 at a high frequency, giving rise to an “average” on-state voltage that is lower than the 0.7V knee voltage of a PN junction. In contrast, bipolar power devices always introduce at least one PN junction into its current conduction path, and the at least one PN junction are connected in series with other conducting element(s). Therefore, the on-state voltage provided by bipolar power devices is generally equal to or higher than the 0.7V knee voltage and it is not easy to reduce the on-state voltage below the knee voltage.
The device 100 may be used in applications where the time duration of the ON state of the device 100 covers many cycles of the “channel on/off” switching period T, such as 50/60 Hz mains rectification or other such low frequency applications. In a conventional mains AC-DC rectifier bridge, all the current flows through two PN diodes (which function as rectifiers) connected in series before reaching an appliance. The voltage drop in the two PN diodes will typically come to at least 1.6V. If the device 100 is used as a synchronous rectifier to replace each of the PN diodes in mains rectification, it is possible to achieve an average on-state voltage of around 0.3V for each device 100, giving 0.6V in two devices connected in series. Accordingly, the voltage drop is reduced by 1V in total, representing approximately 1% improvement in efficiency for 110V mains. With the widespread use of mains rectification in many appliances, the potential savings in electricity consumption and benefits to the environment are huge if the device 100 is employed.
The device 100 can be used in many other power electronics applications. For example, a totem-pole bridgeless power factor correction (PFC) circuit typically uses two low on-resistance high frequency switches such as GaN high-electron-mobility transistor (HEMT) or SiC FET, together with two high voltage super-junction MOSFETs acting as synchronous rectifiers. In this circuit the super-junction synchronous rectifiers are switched on and off at mains frequency 50/60 Hz, and may be replaced with the devices 100 to reduce cost. Since the bridgeless PFC circuits already use complex drive schemes from a control IC, it would be easy to implement in the control scheme the on-off switching of the first conduction path P1 as described above without extra costs.
Apart from power electronics applications which require a rectifier operating at mains frequencies or similar as outlined in the examples above, the device 100 can also be used for rectification at higher frequencies, for example in ordinary PFC circuits where the switching frequency of rectification is typically 70 kHz, or in high frequency switch mode power supply (SMPS) circuits, provided that the ON state of the rectifier in such circuits is long enough to have at least one complete cycle of off-phase T1 and onphase T2. For example, the device 100 may be used as a high voltage synchronous rectifier in a SMPS circuit and the PN junction 11 functions as a free wheel diode. In the SMPS circuit, it may be beneficial to deliberately turn on the N channel of the unipolar structure of the device 100 a little later than normal, increasing the period of the so-called “dead time” during which second conduction path P2 conducts but the first conduction path P1 does not conduct. In this way, the effective resistance of the Ndrift region 2 is lowered when the first conduction path P1 starts to conduct due to conductivity modulation received by the N- drift region 2 during the “dead time”. However, when the device 100 is used in a SMPS circuit, the minority carrier (i.e., holes in the device 100) lifetime shall preferably be controlled such that most of the minority carriers have recombined by the end of the on-phase T2 of the device 100, so as not to compromise the reverse recovery characteristics of the device 100. The reverse recovery characteristics refer to the reverse recovery time of a rectifier, which is a time duration inherently required by a rectifier to stop current flow upon switching.
In addition to the efficiency gains through lower on-state voltage, using the device 100 as a rectifier in the above applications also provides the benefit of lower power dissipation, allowing reduction or even elimination of bulky and expensive heatsinking. The total gains provided by the device 100 to the user and to the environment are therefore enormous.
The voltage rating of the device 100 is a function of the doping concentration and the thickness t2 of the N- drift region 2, while its current rating is a function of the width of the N channel provided in the channel region 5 and the dimension of the PN junction 11. Therefore, the doping concentration and the thickness t2 of the N- drift region 2 may be adjusted to provide required voltage rating. Further, the channel width and the dimension of the PN junction 11 may be adjusted to allow the device 100 to conduct a required amount of current in its ON state. Moreover, to enhance the effect of conductivity modulation, the doping concentration of the P+ well 4 proximate to the PN junction 11 may be increased, for example to 1016 ~ 1018 cm'3. Meanwhile, the doping concentration of the P+ well 4 proximate to the channel region 5 is preferably kept at a low level (e.g., around 1015 ~ 1016 cm'3) to avoid affecting the performance (such as, threshold voltage) of the unipolar conducting structure. This two-level doping concentration of the P+ well 4 may be achieved by controlled ion implantation or other suitable techniques.
The device 100 may include a plurality of cells connected in parallel between the electrodes 10 and 20. The regions 1 to 6, the gate 6 and the oxide layer 7 may form one cell of the device 100. Fig. 1 illustrates a second cell which includes an N+ region 1-2 and a P+ well 4-2 which are electrically connected (not shown) to the first electrode 10. It will be appreciated that the N+ region 1-2 and the P+ well 4-2 work with the Ndrift region 2, the N+ substrate 3, the gate 6 and the oxide layer 7 to provide a further unipolar conducting structure and a further bipolar conducting structure and function in the same way as described above. The device 100 may include thousands of cells in order to achieve a desired current rating. The cells share the N- drift region 2 and the N+ substrate 3. All of the first conduction paths of the cells may be collectively referred to as the “first conduction path” provided by the “unipolar conducting structure” of the device. All of the second conduction paths of the cells may be collectively referred to as the “second conduction path” provided by the “bipolar conducting structure” of the device.
Fig. 3 schematically illustrates a cross-section of a power semiconductor device 200 according to a second embodiment of the present disclosure.
In the device 100, the first conduction path R1 provided by the unipolar conducting structure is switched on and off by applying a drive pulse VGS to the gate electrode 30. The gate drive power consumption increases linearly with the frequency of the drive pulse VGS. Further, if the device 100 has a high voltage rating (e.g., 600V to 800V), the gate electrode 30 may have a large capacitance. It may therefore be difficult to drive the gate electrode 30 at a high frequency due to the large gate capacitance. Further, a large current may be required to drive the gate electrode 30 and therefore the power consumption for driving the gate electrode 30 may be substantial.
The device 200 solves this problem by providing two separate electrodes 8, 9 which are in contact with the P+ well 4 and the N+ region 1, respectively, and by providing a low voltage switch 12 connected in series between the first electrode 10 and the electrode 9. The electrodes 8, 9 are metallisation contacts directly in contact with semiconductor. For example, the electrodes 8, 9 may be made of a material selected from the group of aluminium, copper, gold, titanium or their alloys. The low voltage switch 12 means a switch having a low voltage rating which is at least lower than the voltage rating of the device 200. Other elements of the device 200 are equivalent to the corresponding elements of the device 100 which are labelled using the same reference numerals. The switch 12 can be switched on and off under control of a control signal (not shown).
Similar to the device 100 (of Figure 1), the device 200 may be used as a synchronous rectifier and has an ON state when a positive voltage is applied between the first electrode 10 and the second electrode 20. The gate electrode 30 is biased positive throughout the period of the ON state. That is, a high voltage (i.e., logic T voltage, general equal to the voltage level of a power supply) is constantly applied to the gate electrode 30. Therefore, an N channel is present within the channel region 5 throughout the period of the ON state. The on and off switching of the path P1 between the electrodes 10 and 20 during the ON state is accomplished by turning on and off the switch 12.
In particular, when the switch 12 is turned off, the electrode 9 is disconnected from the first electrode 10. Therefore, although the N channel is present in the channel region 5, no current can flow between the electrodes 10 and 20 via the path P1 and the path P1 is thus turned off by the switch 12. In the meantime, the second conduction path P2 is automatically switched on, injecting minority carriers (i.e., holes for the device 200) into the N- drift region 2.
When the switch 12 is turned on, the electrode 9 is electrically connected to the first electrode 10, and accordingly the first conduction path P1 conducts current between the electrodes 10 and 20. The conductivity of the first conduction path P1 is temporarily enhanced by the injected minority carriers. In the meantime, the second conduction path P2 is automatically switched off or enters the low conductivity mode.
When the device 200 is reverse-biased (i.e., the potential at the first electrode 10 is lower than the potential at the second electrode 20), the control signal applied to the switch 12 may be synchronised to switch off the switch 12 such that the path P1 is turned off. In the meantime, the PN junction 11 of the path P2 is reverse biased and cannot conduct current either. Accordingly, current cannot flow from the second electrode 20 to the first electrode 10 and the device 200 enters the OFF state. During the OFF state, the biasing voltage applied to the gate electrode 30 may be removed.
The electrode 8 is directly connected to the first electrode 10 and thus the connection between the P+ well 4 and the first electrode 10 bypasses the switch 12, thereby allowing current to flow through the second conduction path P2 during the off-phase of the first conduction path P1.
The low voltage switch 12 may be a low voltage CMOS switch. The control signal for turning on and off the switch 12 may be applied to a gate of the switch 12. Such a low voltage CMOS switch has very low gate capacitance and can be turned on and off at a high frequency using a logic signal. There is no need to provide a large current for driving the switch 12. The power consumption for driving the switch 12 may be significantly lower than the power consumption for driving the gate electrode 30 of the device 100.
The switch 12 may be made on the same silicon substrate as the regions 1 to 5 of the device 200. Alternatively, the switch may be made on a separate silicon substrate, which may be further enclosed in a single package together with other parts of the device 200.
Fig. 3 illustrates a second cell of the device 200 which includes an N+ region 1-2 and a P+ well 4-2 which are electrically connected to electrodes 9-2 and 8-2, respectively. It will be appreciated that the electrode 9-2 may be connected to the bottom node of the switch 12, such that the switch 12 can switch on and off the first conduction path of the second cell. The electrode 8-2 of the second cell may be directly connected to the first electrode. The structure of the second cell is symmetric to that of the first cell.
Therefore, it will be appreciated that the N+ region 1-2 and the P+ well 4-2 work with the N- drift region 2, the N+ substrate 3, the gate 16 and the oxide layer 17 to provide a further unipolar conducting structure and a further bipolar conducting structure which operate in the same way as described above.
Each of the devices 100 and 200 uses a gate-driven MOS structure (which includes the gate 6, the oxide layer 7 and the channel region 5) as part of the unipolar conducting structure. It will be appreciated that other types of unipolar conducting structure may be used, as shown in Fig. 4 and Fig. 6.
Fig. 4 schematically illustrates a cross-section of a power semiconductor device 300 according to a third embodiment of the present disclosure.
The device 300 differs from the devices 100, 200 in that the N+ region 1 of the device 300 is disposed outside of the P+ well 4, and the N+ region 1 is in direct contact with the N- drift region 2. Therefore, unless modulated otherwise (as described below), the N+ region 1 is always in electrical connection with the N+ substrate 3 via the N- drift region 2. Because the only charge carriers involved in this electrical connection are the majority carriers (i.e., electrons) of the regions 1 to 3, the N+ region 1, the N- drift region 2, and the N+ substrate 3 form a unipolar conducting structure which provides a first conduction path P1. The device 300 does not have a gate-driven MOS structure.
Similar to the device 200, the P+ well 4 is in contact with an electrode 8, which is directly connected to the first electrode 10, and the N+ region 1 is connected to the first electrode 10 via a series-connected low voltage switch 12. The PN junction 11 formed between the P+ well 4 and the N- drift region 2 provides a second conduction path P2 between the first electrode 10 and the second electrode 20.
As shown in Fig. 4, the device 300 includes a plurality of cells. Each cell includes a N+ region 1-i which is connected to a bottom end of the switch 12, a P+ well 4-i, and an electrode 8-i between the P+ well 4-i and the first electrode 10. The numeral i varies from 2 to N, with N being the total number of the cells. N is equal to 5 in Figure 4 for illustration purposes only. The P+ wells 4, 4-2...4-N are spaced apart from each other. Each of the N+ regions 1, 1-2...1-N is disposed between adjacent P+ wells. All of the cells share the switch 12, the N- drift region 2 and the N+ substrate 3.
Similar to the devices 100, 200, the device 300 may be used as a synchronous rectifier and has an ON state when a positive voltage is applied between the first electrode 10 and the second electrode 20.
During the ON state, the switch 12 is switched on and off at a high frequency. When the switch 12 is switched off, no current can flow between the electrodes 10 and 20 via the path P1, and therefore current flows through the path P2 only, injecting minority carriers (i.e., holes for the device 300) into the N- drift region 2. When the switch 12 is turned on, the first conduction path P1 is accordingly turned on. The conductivity of the first conduction path P1 is temporarily enhanced by the injected minority carriers. In the meantime, the second conduction path P2 is automatically switched off or enters the low conductivity mode because the on-state voltage of the path P1 is lower than the forward threshold voltage of the PN junction 11. In this way, the average on-state voltage of the device 300 is reduced to a level lower than the knee voltage of the PN junction 11. It will be appreciated that the conductivity modulation received by the part of the N- drift region 2 along the path P1 is due to the conduction of the second conduction path in each of the first cell and the second cell which surrounds the path P1.
When the device 300 is reverse-biased (i.e., the potential at the first electrode 10 is lower than the potential at the second electrode 20), the control signal applied to the switch 12 may be synchronised to switch off the switch 12 such that the path P1 is turned off. In the meantime, the PN junctions 11, 11-2 are reverse-biased and also do not conduct current. Therefore, the device 300 enters the OFF state.
Alternatively or in addition, the device 300 may be designed such that it automatically enters the OFF state when the device 300 is reverse-biased, regardless of the control signal applied to the switch 12. In particular, when the device 300 is reverse-biased, depletion regions exist at both sides of the PN junction 11. Because the N- drift region 2 is lowly doped, the depletion region within the N- drift region 2 is much wider than the depletion region within the P+ well 4. Similarly, the PN junction 11-2 between the P+ well 4-2 and the N- drift region 2 also has a wide depletion region within the N- drift region 2. The distance L between adjacent P+ wells 4, 4-2 may be arranged such that the depletion regions within the N- drift region 2 generated by both of the PN junctions
11, 11-2 touch each other. Accordingly, the first conduction path P1 is pinched off by the depletion regions, regardless of the on/off status of the switch 12. Since the reverse-biased PN junction 11 of the path P2 cannot conduct current either, the device 200 enters the OFF state.
Fig. 4 shows that the P+ wells 4, 4-2...4-N are disposed adjacent to the top surface of the N- drift region 2, and that the electrodes 8, 8-2...8-N are in contact with the top surfaces of the P+ wells. In an alternative arrangement as shown in Fig. 5, a trench 13 is provided within the N- drift region 2 adjacent to the top surface of the N- drift region
2. The trench 13 has a width W and may be formed by an etching process. A P+ well 4 is provided around the sidewalls and the bottom wall of the trench 13. The P+ well 4 may be formed by diffusion. An electrode 8 is in contact with the sidewalls and the bottom wall of the P+ well 4. The electrode 8 may be formed by a sputtering process. Similar to Fig. 4, the electrode 8 is in direct contact with the first electrode 10. The arrangement of the trench 13, the P+ well 4 and the electrode 8 as shown in Fig. 5 may be used to replace the P+ well 4, 4-i and the electrode 8, 8-i in at least one cell of the device 300.
As shown in Fig. 4, the cross-sectional shape of an outer boundary 14 of the P+ well 4 generally resembles a square shape. It will be appreciated that in reality, due to the nature of the diffusion process used to make the P+ well 4, the outer boundary 14 of the P+ well 4 has rounded corners at locations 15. By introducing the trench 13, the P+ well 4 of Fig. 5 may be formed by a shallow diffusion process which provides a smaller depth of diffusion than the diffusion process required to make the P+ well 4 of Fig. 4. Accordingly, the outer boundary 14 of the P+ well 4 in Fig. 5 is closer to a square shape than the outer boundary 14 of the P+ well 4 in Fig. 4. The “squarer” shape of the P+ wells 4, 4-i makes it easier for the depletion regions within the N- drift region 2 as described above to join up and pinch off the first conduction path P1. Therefore, by modifying the device 300 using the arrangement as shown in Fig. 5, the device 300 may quickly stop current flow when the device 300 switches from its ON state to its OFF state, and therefore achieves pinch-off of the conduction path P1 at a lower reverse bias. Further, the arrangement as shown in Fig. 5 allows the P+ wells 4, 4-i and the N+ regions 1, 1-i to be densely packed, thereby reducing the overall footprint of the device 300.
Fig. 6 schematically illustrates a cross-section of a power semiconductor device 400 according to a fourth embodiment of the present disclosure.
Similar to the device 300, the device 400 does not have a gate-driven MOS structure. However, the device 400 differs from the device 300 in that the N+ region 1 is disposed within the P+ well 4, and the N+ region 1 has a boundary substantially aligned with the boundary of the P+ well 4 such that the N+ region 1 is in direct contact with the N- drift region 2. It will be appreciated that the boundary N+ region 1 may slightly protrude over the boundary of the P+ well 4, and the device 400 is functional as long as the N+ region 1 is in direct electrical connection with the N+ substrate 3 via the N- drift region 2. There is no P-type channel region (similar to the channel region 5 of Fig.3) formed between the N+ region 1 and the N- drift region 2. Because the only charge carriers involved in the electrical connection are the majority carriers (i.e., electrons) of the regions 1 to 3, the N+ region 1, the N- drift region 2, and the N+ substrate 3 form a unipolar conducting structure which provides a first conduction path P1.
Similar to the device 200, the P+ well 4 of the device 400 is in contact with an electrode 8, which is directly connected to the first electrode 10, and the N+ region 1 is in contact with an electrode 9, which is connected to the first electrode 10 via a series-connected low voltage switch 12. The PN junction 11 formed between the P+ well 4 and the Ndrift region 2 provides a second conduction path P2 between the first electrode 10 and the second electrode 20.
The operation of the device 400 is very similar to the operation of the device 300 as described above. In particular, when the device 400 is reverse-biased, the depletion regions within the N- drift region 2 are able to spread out from the boundary of the P+ wells 4, 4-2 to pinch off the first conduction path P1.
The devices 300 and 400 have the advantage of not requiring a gate-driven MOS structure or a gate connection, so the manufacture of the devices 300, 400 is simpler in that there are only two metallisation contacts (i.e., electrodes 8 and 9) on the top surface of the device, avoiding the need for overlapping electrode contacts.
Further, the description above relating to the advantages provided by the device 100 and the power electronics applications in which the device 100 can be used is equally applicable to the devices 200 to 400.
It will be appreciated that although a planar MOSFET structure having a horizontal channel is used as the unipolar conducting structure in the devices 100, 200, other device structures such as Trench MOS (U-MOS) can also be used. Indeed, it will be appreciated that there are numerous other equivalent device structures that can be used as the unipolar conducting structure, all of which are within the scope of the present disclosure.
Further, the unipolar conducting structure within the devices 100-400 uses electrons to conduct current. It will be appreciated that the unipolar conducting structure may alternatively use holes to conduct current. However, the mobility of holes is lower than that of electrons, and the resistivity of the first conduction path provided by the holebased unipolar conducting structure may be higher than that provided by the electronbased unipolar conducting structure.
It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present disclosure. In the present disclosure, generally the n-type doping polarity is referred as the first conductivity type and the p-type doping polarity is referred as the second conductivity type. However, the skilled person would be able to reverse them to form an appropriate device. The disclosure covers all the devices formed from the reverse doping polarities as well. Further, it will be appreciated that the terminals and the associated contact regions of the devices could be arranged to be out-of-plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present disclosure.
The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’, ‘bottom’, ‘above’, ‘overlap’, ‘under’, ‘lateral’, ‘vertical’, etc. are made with reference to conceptual illustrations of a semiconductor device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a transistor when in an orientation as shown in the accompanying drawings.
Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the 10 disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims (23)

CLAIMS:
1. A power semiconductor device, comprising:
a semiconductor substrate comprising:
a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a lower doping concentration than the first region and the third region; and a bipolar conducting structure comprising a P-N junction formed between a fourth region of a second conductive type opposite to the first conductive type and the second region;
a first terminal; and a second terminal;
wherein the unipolar conducting structure is operable to provide a first conduction path between the first terminal and the second terminal using the first, second and third regions;
wherein the bipolar conducting structure is operable to provide a second conduction path between the first terminal and the second terminal using the fourth region, the P-N junction, the second region and the third region;
wherein the first conduction path is configured to be switched on and off at a first frequency under application of a control signal during an ON state of the power semiconductor device, and the second conduction path is configured to operate in a high conductivity mode during an off-phase of the first conduction path and to operate in a low conductivity mode during an on-phase of the first conduction path.
2. A power semiconductor device according to claim 1, wherein the second region is configured to receive conductivity modulation due to carriers injected from the fourth region into the second region when the second conduction path operates in the high conductivity mode.
3. A power semiconductor device according to claim 1 or 2, wherein the first conduction path is in parallel to the second conduction path.
4. A power semiconductor device according to any preceding claim, wherein the power semiconductor device is operable to have an ON state during which an electric current flows between the first and second terminals using at least one of the first and second conduction paths, and an OFF state during which an electric current does not flow between the first and second terminals.
5. A power semiconductor device according to any preceding claim, wherein:
the power semiconductor device is a synchronous rectifier, the power semiconductor device is operable in an ON state upon application of a voltage of a first polarity between said first and second terminals, and the power semiconductor device is operable in an OFF state upon application of a voltage of a second polarity between said first and second terminals, the second polarity being opposite to the first polarity.
6. A power semiconductor device according to any preceding claim, wherein a time duration of the on-phase of the first conduction path is configured to be longer than a time duration of the off-phase of the first conduction path during the ON state of the power semiconductor device.
7. A power semiconductor device according to claim 2 and any one of claims 3 to 6 as dependent upon claim 2, wherein a time duration of the on-phase of the first conduction path within at least one cycle of the control signal is shorter than a time duration during which a fraction of the injected carriers disappear through recombination with majority carriers of the second region.
8. A power semiconductor device according to any preceding claim, wherein, in use, the first and second terminals are configured to be connected to an AC voltage of a second frequency so as to rectify the AC voltage, and wherein the first frequency is higher than the second frequency.
9. A power semiconductor device according to claim 6, wherein the first frequency is at least two times higher than the second frequency.
10. A power semiconductor device according to any preceding claim, wherein the unipolar conducting structure comprises a metal-oxide-semiconductor (MOS) gate structure, and wherein the MOS gate structure comprises a channel region of the second conductive type disposed between the first region and the second region, and a gate electrode for generating an electric field in the channel region to invert the conductivity type of the channel region so as to form a conducting channel between the first and second regions.
11. A power semiconductor device according to claim 10, wherein a portion of the fourth region proximate to the P-N junction has a doping concentration higher than that of the channel region.
12. A power semiconductor device according to claim 10 or 11, wherein the gate electrode is configured to receive the control signal to switch on and off the conducting channel so as to switch on and off the first conduction path.
13. A power semiconductor device according to claim 10 or 11, further comprising a switch connectable between the first terminal and the first region, and wherein the switch is configured to receive the control signal to switch on and off the first conduction path.
14. A power semiconductor device according to any one of claims 1 to 9, wherein the first region is in direct contact with the second region, and the power semiconductor device further comprises a switch connectable between the first terminal and the first region, and the switch is configured to receive the control signal to switch on and off the first conduction path.
15. A power semiconductor device according to claim 13 or 14, wherein the switch is a low-voltage switch.
16. A power semiconductor device according to any one of claims 13 to 15, wherein the switch is formed on a further semiconductor substrate separate from the semiconductor substrate.
17. A power semiconductor device according to any preceding claim, wherein the fourth region comprises a plurality of fourth sub-regions spaced apart from one another, wherein at least some of the fourth sub-regions are operatively connected to the first terminal and form P-N junctions with the second region.
18. A power semiconductor device according to claim 17 as dependent from claim 5, wherein the fourth sub-regions are spaced apart from one another at a distance which is configured such that upon application of the voltage of the second polarity to said first and second terminals, depletion regions of the P-N junctions within the second region corresponding to adjacent fourth sub-regions collectively pinch off the first conduction path.
19. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from one another, and the at least one first sub-region is disposed between adjacent ones of the fourth subregions.
20. A power semiconductor device according to any one of claims 17 to 19, further comprising a trench disposed within the second region, and wherein at least one of the fourth sub-regions is disposed adjacent to at least one wall of the trench.
21. A power semiconductor device according to claim 20, further comprising a metallisation contact electrically connected to the at least one of the fourth sub-regions, and wherein the metallisation contact is operatively connected to the first terminal and at least a part of the metallisation contact is disposed within the trench.
22. A power semiconductor device according to claim 17 or 18, wherein the first region comprises at least one first sub-region spaced apart from one another, and the at least one first sub-region is disposed within one of the fourth sub-regions and has a boundary substantially aligned with a boundary of the one of the fourth sub-regions such that the at least one first sub-region is in direct contact with the second region.
23. A method of operating a power semiconductor device, the power semiconductor device comprising:
a semiconductor substrate comprising:
a unipolar conducting structure comprising a first region of a first conductive type, a second region of the first conductive type, and a third region of the first conductive type, wherein the second region has a doping concentration lower than that of the first region and the third region; and a bipolar conducting structure comprising a P-N junction formed between a fourth region of a second conductive type opposite to the first conductive type and the second region;
a first terminal; and a second terminal;
the method comprising:
providing a first conduction path between the first and second terminals using the first, second and third regions;
applying a control signal to switch on and off the first conduction path at a first frequency during an ON state of the power semiconductor device; and providing a second conduction path between the first and second terminals using the fourth region, the P-N junction, the second region and the third region; wherein the second conduction path operates in a high conductivity mode during an off-phase of the first conduction path and operates in a low conductivity mode during an on-phase of the first conduction path during the ON state of the power semiconductor device.
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