GB2549032A - Non-planar semiconductor device having doped sub-fin region and method to fabricate same - Google Patents

Abstract

The FinFET device comprises conformal insulating layers 108, formed over silicon fin structures 102 that are used to dope the sidewalls of the semiconductor fins. A boron doped silicon glass layer is used for p-type doping and a phosphorous doped silicon glass layer is used for n-type doping. A nitrogen containing insulating cap layer 114 is formed over the doped insulator layers prior to annealing the device structures to diffuse the dopants into the fin structures. The doped insulating layer and the nitrogen containing capping layer are etched back to expose upper portions of the fin structures that remain undoped. The fabrication of CMOS devices is disclosed.

Description

Non-Plahar Semiconductor Device having Doped Sub·Fin Region and Method to Fabricate Same

TECHNICAL FIELD

[0001 j Embodiments of the invention are in the field of semiconductor devices and processing and, in particular, non-planar seliicondnetor devices having doped sub -fin regions and riiethods of fabricating non-planar semiconductor devices having doped sub-fin regions.

BACKGROUND

[0002] For - he past several decades, the sealing:*#features in integrated circuits has been i driving forCe behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional Units on the limited real estate 6f semiconductor chips. For example, shrinking transistor si/e allows lor the incorporation of an increased number of memory Ur logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-tnore capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

[0Θ03] In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as devieb dimensions continue to scale down. In conventional processes, tri-gate transistors ai® generally fabricated ori either bulk silicon substrates or silieon-on-insulator substrates. In Some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure.

[0004] Seating pulti-gate transistors has not been without consequence, however. As the dimensions of these fundamental building; blocks of microelectronic circuitry are reduced and as the sheer number |f fundamental pudding bloop febrieated in a given region is increased, the ednsffaints on the semiconductor processes Used to fabricate these building blocks have become overwhelming;

BRIEF DiSCilFTION OF TEE DRAWINGS

[0005] Figures: I Λ-1 I illustrate· cross-sectional view Of various operations in a method of fabricating: non-planar sem (conductor devices having doped sub-fin regions, in accordance: with an embodiment of the present: invention, where: [01)06] figure 1Λ illustrates a bulk semiconductor substrate having fins etched therein; [0007] Figure 1B illustrates a P-type solid state dopant source layer S'ormed on the structure of Figure 1 A; [00081 Figure "1G illustrates a patterned mask Firmed over only a portion Of the fins of i igurc IB: [0009] Figure 1D illustrates patterning ofthe P-type solid state dopant source layer 108 to form a patterned P- type solid state dopant sourcedayer; [0010] Figure IF illustrates formation of an insulating: buffer layer or blocking layer conformal to the exposed fins and the patterned P-type solid state dopant sdfiree layer of Figtitb 10; [001.1] Figure IF illustrates formation and planarization of a dielectric fill layer: over the structure of Figure IE to expose the: top surfaces of the fins; [0012] Figure 1G illustrates masking olfiaS dedicated for HMDS device fabrication along with well and/or retrograde implant operations to form N-type doped fins from exposed PMOS-dedicated fins; [0013] Figure 1M illustrates recessing of the dielectric fill layer, the patterned P-type solid state dopant source layer and tire insulating buffer layer or blocking layer to expose: protruding portions of the fins of Figure 1G; and [0014] Figure 1 i illustrates a drive-in anneal to provide doped sub- fin regions of the fins dedicated to NMOS devices.

[0015] Figures 2A-2I illustrate cross-sectional:view of various operations in another method of fabricating non-planar semiconductor devices having doped sub-fin regions, in accordance with an embodiment of the present invention where: [0016] Figure 2A illustrates a bulk semiconductor substrate having fins etched therein; [0017] Figure :2B illustrates a F-type soliditate dopant source layer formed o>n the structure of Figure 2A and formation of an insulating buffer layer or blocking layer conformal She P-type solid state dopant source layer; [0018] Figure 2(| illustrates a patterned mask formed dyer only a portion of the id's of Figure 2B and patterning of the insulating buffer layer or blocking layer and the P-type solid state dopant sobreC layer; [0019 ; Figure 2D ijlustrates^brmaiion of an N-type Solid State dopant Source layer formed on the exposed ins and patterned insulating buffer layer or blocking layer and the patterned P type solid state dopant source layer of Figure 2€; [0028] Figure 2ff illustrates a patterned mask formed over only a portion of the fins of Figure 2Γ) and patterning of the N-lype solid state dopant source layer; [0021] Figure 2F illustrates formation of an insulating buffer layer or blocking layer conformal the N-type solid state dopant source layer; [0022] Figure 2Q illustrates formation a dielectric fill layer over the structure of Figure 2F; [0023] Figure 211 illustrates planarization and recessing of the dielectric fill layer, the patterned P-type solid state dopant source layer, the patterned N-type solid state dopant source layer and thelnsulatingi buffer layers or blocking layers to expose protruding portions of die fins of Figure 2G.; and [0024] Figure 21 illustrates a drive-in anneal to provide doped sub sin regions of the tins dedicated to both NMOS and PMOS devices.

[0025] Figure 3A illustrates a cross-sectional view of a nOn-plapar semiconductor device having fins with doped sub-fin regions, in accordance with an embodiment of the present invention.

[0026] Figure 3B illustrates a plan view taken along the a-a’ axis of the semiconductor device of Figure' 3 A, in accordance with an embodiment of the present invention, [0027] Figure 4A is a simulated 2-D contour plot demonstrating boron dopant confinement to sub-fin regions,: in accordance with an embodiment of die present invention.

[0028] Figure 4B is a simdlated 2-$) contour pit>i demonstfitting phosph|riiS dopant confinement to sub-fin regions, in accordance with an emb&Unient of the present invention.

[0029] Figure 5 is a measured If) SIMS dopant profile demonstrating diffusion of dopants: from a doped insulator layer into a silicon subsirate,: in accordance with an embodiment of the present invention.

[0030] Figure 6 illustrates a computing device in accordance with one implementation of the invention,

DESCRIPTION OF THE EMBODIMENTS

[0031] Non-planar semiconductor devices having doped sub: fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions am described. In the following description, numerous specific details are set forth, such as specific infegritlipn and material regimes, in order to provide & thorough understanding of embodiments of the present invention, it will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are; not described in detail in order to not unnecessarily obscure embodiments of the; present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

[0032] One or more embodiments described herein is directed to a process to selectively dope sub-fin regions of tri-gate or PfnFET transistors fabricated on bulk silicon wafers, e.g., by way of tri-gate doped glass subfin tret-diffusion. For example, described herein is a process to selectively dope a sub-fin region of tri-gate or Ft nFET transistors to mitigate sub-fin leakage while -simultaneously keeping fin doping low, Inetjrporatipn of a solid state doping sources (e.g., p-type and n-tvpe doped oxides, nitrides dr Carbides) into the transistor process flow,: which after being recessed from the fin sidewalls; delivers well doping into the sub-fin region while keeping the fin body relatively undoped; Additionally, in an embodiment, one or mom approaches described herein enables seif-alignment of the bottom of an active portion of a hnik Πη with a doping boundary between the active portion and the remaining bulk portion fe.g., the portion below I he gate-controlled region).

[0033] More generally, it may be desirable so use bulk silicon for fins or •ligate. I iowever, there is a concern that regions (sub·fin) below the active silicon fin portion of the device ic.g., the gate-controlled region, or HSi) is under diminished or no gate control. As stich, if source or drain regions are at or below the HSi point, then leakage pathways may exist through the subfin region. In accordance with an embodiment of the present invention, in order to address the above issues; sufficient doping is provided through subfin doping without necessarily delivering the same level of doping Ur die ifSi portions of the fins.

[0034] ; Embodiments may include one or more of the following features or Considerations: (! ) low doped fins with high doped sub-fin regions; (2) the use of boron doped oxide (e.g., B$G) as a dopant source for NMOS sub-fin regions; (3) the use of phosphorous doped oxide (e.g,, P$Q) or arsenic doped oxide (e,g., AsSGl Is a dopant souree for PMOS sub-fin regions; (4) low-doped NMOS fin/BSG doped subfin plus: standard implanted PMOS fin (e.g., involving a patterning process to removeEot'On doped oxide from PMOS structures, while NMOS well duping is subsequently delivered by a boron doped layer, and PMOS well doping is achieved by conventional implant processes); (5) low-doped PMOS fin/PSG or AsSG doped sub-fin plus standard intplanted NMOS f'in (C.g., involving a patterning process to remove phosphorus or arsenic doped oxide from NMOS structures, while PMOS well doping is subsequently delivered by a phosphorus Or arsenic doped layer, and NMOS well doping is achieved by conventional implant processes); (h) low-doped PMOS and NMOS fins formed on the: same wafer by integration of BSG/(PSG or \s.SG) cU sped sub-ims (e.g., involving a patterning process to integrate:NMOS subfin regions formed by "Β.$ζί. dopant out-diffusion and PMOS sub-fin regions formed by PSG or AsSG dopant out-diffusion: on same wafer), processes described herein may enable low-doped NMOS and PMOS fin fabrication with high sub-fin doping in both NMOS and PMOS devices, h is to be understood; that in place of BSU. PSG or AsSG, more generally, the N-type or P-ivpe solid stare dopant source layer is i dielectric layer incorporating N-type or P-type dopants, respectively, therein such as, but hot limited to, an N-type or P-type doped oxide, nitride or carbide layer.

[0035] To poivide context, conventional approaches to addressing the above issues have involved the use of well implant operations, where the sub-fin region isi heavily doped (dig., much greater than 21:18/001¾. which shuts off sub-fin leafage but leads: unsubstantial doping in dhesfin as; well. The addition of halo implants further increases fin doping such that end of line fins are doped at,a high level (e.g., greater than approximately 1Ε!|/οηι|. By Contrast one or more embodiments described herein provide km doping in the fin which ntay be beneficial since higher Current drive is enabled by improvin| earner mobility, which is: Otherwise degraded by ionized impurity scattering ibf high doped channel devices, Furthermore, since random variation of threshold voltage (Vt) is directly proportional to the squareiroot of doping density, low doped devices also have the advantage of lowering the random mispatch in Vi. This enables products to operate at lower voltages without functional failures. At the same time, the region just below theTin (i.e. the sub-fin) must he highly doped in order to prevent sub-tin source-drain leakage.

Conventional implant steps used to deliver this doping to the sub-fin region also dope the fin region substantially, snaking it impossible to achieve low doped fins and suppress sub-fin leakage at same lime.

[0036] As described more thoroughly below, one Or embodiments described herein may include use of a solid source doping layer (e,g. boron doped oxide) deposited on tins subsequent to fin etch. Later, after trench fill and polish, the doping layer if recessed along with the trench fill material:to define the fin height i ltsi) for the device, The operation removes the doping layer from the fin sidewalls above ilsi. Therefore, the doping layer is present only along d® fin sidewalls in the sub-fin region which ensures precise control of doping placement. After a dri ve-in anneal, high doping is limited to the sub-fin region, quickly transitioning to low doping in the adjacent region of the fin above ilsi (which forms the channel region of the transistor). Dne or more advantages or implementations include: (11 use of sdiid source doping layer; if) patterning to remove doping layer from opposite polarity devices; (3) etch operation Ihabrecesses trench material and doping layer in one operation; (4,) improved dltnkistdr current drive and improved random Vt mismatch; (5) possibility of removing web implants from a device flow akogethes (in such; a case, the? ii-;o of solid doping provide inter··: mmim r isolation and, hence, separate well formation may no longer he necessary;.

[0037] In a .first; example, figures [A-fl Illustrate eross-seetionaliView of various operations in a method of imbricating non-planar semiconductor devices having (lopeef sub -fin regfit|,: in accordance with an embodiment of the present; invention. The first exemplary paves-· bow may lx: described, in oneipeeific embodiment] as a borosiliicivte glass (BSG) N.MQS and itnpianted PMilb fabrication scheme.

[0038] Referring to Figure ΙΔ, a bulk Semiconductor substrate 100, such as a bulk single crystalline silicon substrate is provided having fins 102 etched therein, in an embodiment, the fins are formed directly in the: bulk substrate 100 and, as such, are formed continuous with the bulk substrate :|00, Artifacts remaining from the fabrication of fins 102 may also be present. For example, as depicted in Figure 1 A. a hardmask layer 104, such as a silicon nitride hardmask layer, and a pad oxide layer 106, such as a silicon dioxide layer, rethaut Mip fins'!02, In one embodiment, the hulk substrate 100 and, hence, the fins :102, are undoped or lightly doped at this; stage. For example, in a particular embodiment, the: bulk substrate 100 and. hence, the ins I02>:::have a concentration of less than approximately ilBl 1 atoms/cnV of boron dopant impurity atoms.

[0039] Referring to Figure ί B, a P-type solid state dopantpource layer 108 is formed ort the structure of Figure 1 A. In one embodiment, the P-type solid state dopant Source layer 108 is a dielectric layer incorporating P-type dopants therein such as, but not limited to, a P-type doped oxide, nitride or carbide layer. In a sped fie such embodiment; the P-type solid state dopant source layer 108 is a borosilieate glass layer. TheP-type solid state dopant source layer 1:08 may .be formed by a process suitable to provide a conformal layer on the fins 102, For example, in one embodiment, the P-type solid state dopant source layer 108 is formed by a chemical vapor deposition (CVl): pro·,, ess or other deposition process; (e.g . ALD. PFCVl), PVD. HOP assisted CVD, low temp CVp) as a conformal layer above the entire structure1 of Figure 1 A. In a particular esuhodimens, the P typei solid state; dopant source layer d08 is a BSCS layer having' a boron concentration appfoximktfely in the range of 0.1 - ;3 0 weight vi. In another embodiment, a capping layer can be formed on lire P-type solid state dbpant source: layer 108 as an maitu-lormed capping layer to protect the P-type solid state dopant source layer 108 during subsequent exposure to ambient conditions. In one such embodiment; the capping layer is a nitride, carbide or alumina <ΛΙ>()=.) capping layer, it is to be understood that the capping layer can be patterned in a same patterning operation, if any, as used ior the P-type solid state dopant source layer 108.

[ΘΘ40] lei erring to Figure 1C, a patterned mask is formed over only a portion of the fins 102, As will be described in association with subsequent processing operations, this masking operation Enables distinction between fins for NMOS devices arid furs lor PMOS devices, in one embodiment. the mask is composed of a topographic masking portion 110 and an anti-reflective coating CARO layer 112. In a particular such embodinten!, the topographic masking portion HO is a carbon hard mask (OHMg layer and die anti-reflective coating layer 112 is a silicon ARC? layer. The topographic masking portion 1 ID and the ARC layer 112 may be patterned with conventional lithography and etching process techniques, [ΘΘ4Τ] Referring to figure ID and on, designations of fins 102 as suitable for an NMOS or a PMOS device are indicated from this point on in. the process flow. Referring to Figure I D specifically, the P-type solid state dopant source layer 108 is patterned, fog,, by a plasma, vapor or wet etch process, to form patterned P-type solid state dqpimi source layer 108’. Also depleted is the removal of the anti-reflective coating: layer 112: which may also he performed usingfo plasma, vapor or wet etch process,:; Patterning of the: P·type solid state dopant soured: layer 108 and removal of fh&amp;anti-reflective coating layer 112 may be performed in a same or different processing operation, [0042] Referring to Figure IE, topographic masking portion 1 If) ikremoved which may be performed using a plasma, vapor or wet etch process. Removal of the topographic masking portion 110 may be performed in a same process operation as the removal of the anti-reflective coating layer 112, or in a subsequent process operation. Also depicted in Figure IF. an insulating buffor foyer or blocking layer 114, such as an violation nitride;layer, is formed conformal to the exposed fins 1()2 and the patterned P-iyne solid state dopant Soured1 layer fi)8\ e.g.. to cap the patterned 1type solid state dopant source layer The insulating; hufferMyer of blocking layer 114 may be formed by a process suitable to provide a conformal layer on the exposed t ins 11)2 and me patterned P-type solid state dopant source layCr 108’. For example, in one embodiment, the insulating buffer layer or blocking layer 114 is: formed by a chemical v|por deposition (OVD) process or other deposition process (e.§., Aid'. PECVD, IP Vi), })DP assisted CVD, low temp < 1VDi.

[0043] Referring to Figure I F, a dielectric fill layer 116 is formed over the structure of P-gum 1 i: and subsequently planarized to exp#e the top surfaces Of the fins 102 (e.g,, exposing both NMG$ and FMOS dedicated:fins iffi), in One embodiment, the dielectric fill layer 116 is composed of silicon dioxide, such as Is used in a shallow trench isolation fabrication process, The dielectric fill layer 13hi may be deposited by a chemical vapor deposition (CVD) or other deposition process (e.g., ADD, PfiCVD, PVD, fl:DP assisted CVD, low temp CVD) arid may be planarized by chemical Mechanical polishing (CMP) techniques, l*he planarization also removes portions o! the patterned P-type solid state dopant source layer 1(>8\ and the insulating bufier layer or blocking layer 114 if present, from the top of fms 102, As is"also depicted in Figure I F, any ariiineisrioid fin patterning, such as the hardmask layer 104 and the pad oxide layer 406, may be removed during; the CMP process t| expose fins 102. in an alternative embodiment; a hardmask or oilier dielectric layer may be retained on top of the fink in order td eliminator reduce gate control frphi the top of the fins (p.g;, as in a double gate device versus a tri-gate device).

[0044] deferring to Figure 10, the fins1.02 dedicated for NMOS device fabrication are masked by a masking: layer 118. in one embodiment, the masking layer 118 is composed of a phplq-resist layer, as is known in the art, and may be patterned by conventional lithography and development processes. In a particular embbdimeni, the portions of the photo-resist layer exposed to the light source are removed upon developing the phptp-feSist layer. Thus, patterned ohoto-resist layer is composed of a positive photo-resist materia}, in it Specific embodiments the photo resi n layer is hdritp· -sod of apPSitive photo-resist Material such as, bill not limited to, a .:248 nm iv- s; a 1')mm resist. a ] y nm ms.st, an extreme ultra violet (EUV) resist, an e-heam imprint layer, or a phenolic resin matrix with a dinromiphihoquinone 'cnsiri/er. In another particular embodiment, the portions oi the photo-resist layer exposed to the light source are retained op; >n developing the photo-rexis! layer. Thus. the photo-rosist layer is etsmposed oi' a negative photo resist material.: lira specific embodiment, the photo-resist layer is composed oka negative photoresist material such as, but not limited to, b|n|i:sMn| of poly-eis-isoprene or poly-vinyl-cinnamate, [0045] Additionally, referring again id Figure id, well and/i):r::retrograde implant operations 120 are performed to "form M-i.ype doped fins 122 from the exposed PM(>S-dedicated fins. The doping of the exposed finds may lead to doping within the bulk substrate portion 100, where adjaeentiins 122 share a common doped region 122’ in the hulk substrate 100, in one embodiment, the: N-type doped fins 122, and the common doped region !22’ if' present, are doped to include phosphorous and/or arsenic N-Type dopants having it total concentration qf:2E:f 8 atoms/cro3 or greater, [0046] Referring:to Figure 111. the dielectric fill layer 116 is recesSed to expose protruding portion' of tins 1:02 and 122, Additionally, the: patterned P-type solid state dopant source layer 1082 and the insulating buffer layer or blocking layer 13 4 if present, are recessed to approximately the same level as the dielectric fill layer 116, as depicted in Figure 1H. The recessing of these layers may be performed by a plasma, vapor or wet etch process, In one embodiment, a dry etch process selective to silicon fins is used, the dry etch process based on a plasma generated from gases such as, hut not limited to Nip, Οίΐίρ, ChFg, Mist and (¾ with typically pressures in the range of 3d-1 (K) mltirr and a plasma bias of 50-1 (ΧΙΟ Watts, in an embodiment, the dielectric fill layer 116 and the patterned P-tvpe solid state dopant source layer 108’ are: recessed at the same time at, an approximately 1:1 selectivity. In another embodiment, the dielectric fill layer 116 and the patterned P-type solid state dopant source layer 108’ are recessed sequentially.

[0047] Referring tp Figure 31, it drive-in anneal is performed io provide doped sub-fin regions of the fins dedicate! to NMO$ devices. More particularly, upon heating, dopants from the patterned P-type solid state dopant sourhe layer 108". such as boron dopant atoms, arc diffused into the sub-fin regions (those regions below the recessed dielectric fill layer 116) to form P-type doped sub-tin regions ί 24. 'Hu* diffusion may also lead to doping within the bulk substrate pcirtton 100, where adjacent fins 102 share a common doped region 124' in the hulk: substrate 100. In this manner, the protruding portions of fins 102, Kg;, protruding portions! 102', of the NMO$ devices remain undbped hr lightly doped, e.:g,, essentially retaining the doping pro hie of the original hulk substrate 100 and fins 102 described in association with Figure 1Λ. As a result, an interface 126 exists between the protruding portions 102’ and the P-type doped sub Tin regions 124. In one such embodiment, the interface 126:represents a doping concentration, step dr rapid gradient change where the P-type doped sub-fin regions 124 has® a fetal dopant Concentration of 2F.18 aloms/em’ or greater, while the protruding portions 102’ have a total dopant concentration significantly less than 2B18 atomsAan*, e.g., of approximately 5Fi7 atoms/cm? or less. The transition region can be relatively abrupt, as is described in greater detail below in association with Figures 44 and 4B.

[0048] Referring again to Figure If,, the P-type doped suh-fin regions 124 are1 doped across the entire suh-fin region·. In one such embodtnienf, each On is approximately 10 nanometers wide, and:the dopant drive-in process of Figure 1G requites only a 5 nanometer drive of dopants from each side of the patterned P-type solid state dopant source layer ,168 ·. In an embodiment, drive-in operation is performed at a temperature approximately in the range:of 8(10-1050 degrees,Celsius.

[0049] In general, referring again to Figures ! A-II, in an embodiment, a doping layer of borosiheate glass (RSG) is vised to dope: sub-fin regions of NMOS devices. A layer of B8G is deposited on fins after fin etch. The wafers are patterned such that theiBSG is removed froth the PMOS regions. A hloeMng or a barrier layer may be deposited to form a barrier between the BSO and trench fill (dielectric 116) material to enable robust boron in-diffusion from ibe BSG film into the silicon sub-fin. After trench fill and polish, PMOS fins are doped with standard well implants. The trench fill recess operation remove* BSG from the Bn protrusions on the NMOS fins. Finally, a drive-in anneal operation drives boron doping into the sub-fin while leaving the prOtfhding portion of the fin without significant doping. It is to be understood that, in another embodiment. the conductivity types described m association with Figures 3Λ- ί I ran he reversed. e.g;, bi-typo tor P-type and viice: versa.

[¢050] in another aspect, a Solid state doping source rnay be used to d»pe: subfih regions for both HWOS and P.VIOS device fabrication, Thus, in a second bxahiple, Figures 2As2fbllustr|re cross-sectional view of various operations: in another method of fabricating non-pianar semiconductor devic|$ having doped Sub-Sim regions, in accordance with an ethbbdhnent of die present invention. The Second exemplary process Slow vMy be described, in one sped he embodiment, as a bdrosiheate glass (B$G) NMOS and phosphosilicate glass (PSG) or arsenic-silicate glass (AsSG) PMOS fabrication scheme, [0051] Referring to Figure 2A, a bulk semiconductor substrateJOO, such as a bulk single crystalline silicon substrate is provided having;fins 3Q2: etched therein, in an embodiment, thevfins itrejesrmed directly in the hulk substrate 200 and, as such, are idnricd cr-ntinuo'iis $ph the bulk substrate 200. Artifacts remaining from the fabrication of l ms 202 (e;g„ &amp; silicon nitride hardmask. layer and Underlying pad oxide layer) may already he removed at this stage, as depicted in Figure 2A. Alternatively, a hard mask layer, such as a silicon nitiidd hardm ask layer, and a pad oxide layer, such as a silicon dioxide layer, may remain atop the fens, as was described in association with Figure 1 A. la one embodiments the bulk substrate 200 and, hence, the fins 20f, are undoped hr lightly doped at this stage. For example, in a particular embodiment, the bulk substrate 200 and, hence, the fins 202, have a concentration of less than approximately 5E17 atonis/em* of boron dopant impurity atoms.

[0052] Referring to Figure 2B, a P-type solid state dopant source layer 208 is formed on the structure of Figure 2A. in one embodiment, the P-type solid state dopant source layer 208 is a dielectric layer incorporating P-type dopants therein such as, but not limited to, a P-type doped oxide, nitride or carbide layer. In a specific such embodiment, the P-type solid state dopant source layer 2()8 is: a boros·lieatc glass layer. The P-type solid state dopant source layer 208 may be formed by a process suitable so provide a conformal layer on the tins 202. For example, in one embodiment, the P-type solid state dopant: source layer 208 is formed by a chemical vapor deposition (FVl>"s process dr other deposition process (e.g., ADD, PECVD.. PVD, HDF assisted CVD, lew temp CVITj as a eonfonnal layer above the cm ire structure of Figure 2Λ. lit a particular embodiment the P-iypc solid state dopant source layer 208 is a BSG layer having a boron concentration approximately in the range of 0.1 - 10 weight %. hr another vmbodhuem. a capping layer eats be fbrnied on tire P-type solid state dopant, source layer 208 as an in situ-formed capping layer to protect the p-type solid state dopant source layer 208 during subsequent exposure to: ambient conditions. In omr sueh embodiment, the capping layer is a nbride. carbide or alumina (AFQb) capping layer, it is to be understood that the capping: layer can be patterned in a same patterning operation,, if any, as used for the p-type solid state dopant source layer 208.

[0033] Referring again to Figure 2B. an insulating butter layer or blocking layer 209, such as an isolation nitride layer, is formed ct)nfprma3 to the P-tyne solid state dopant source: layer 208, e.g., to cap the P-type solid state dopgnt source layer 208. The insulating buffer layer or blocking layer 209 may be formed by a process suitable fo ppivide a conformal layer on the P-type solid state dopant source layer 208. For example, in one embodiment, the insulating buffer layer or blocking layer 209 Is formed by a chemical vapor deposition (CVD) process or other deposition process (e.g., ALT), Phi 'VI), PVD, JiDP assisted CVD, Iqw temp CVD).

[0054] Referring: to Figure 2#.and on, dpsignafiorts of fins 202 as suitable for an NMQ.S or a PM0S device are indicated &amp;ont this point on in the process flow. Referring to Figure 2C specifically, a patterned mask is formed Over only a portion of the fins 202. As wifi be described in association with subsequent processing operations, this masking operation enables distinction between Tins for NMOS devices and fins lor FMQS devices, lit one embodiment, the mask is composed of a topographic masking portion 210 and, possibly, an anti-reflective coating (ARC) layer (not shown), in a particular such embodiment, site topographic masking portion 210 is a carbon hafompkiCflM) layer and the anti-refieciive coating layer is a silicon ARC layer. The topographic masking portion 210 and the ARC layer may he patterned with conventional lithography and etching process techniques. Referring again to Figure 2C. the insulating: buffer layer Or blocking layer 209 the:P-type solid state dopant source layer 2C8 are:: patterned, e.g.. by a plasma, vapor or wet etch process, 10 form patterned insulating buffer layer or blocking layer 20V and patterned P-tyne «olid siaie dopani source layer 208', respectively.

[TOSS] Referring to Figure 2D. topographic masking pun ion 2U) is removed which may be performed usi ng a plasma, vapor or wet etch process. Also depicted in Figure 2D, an N-iype solid state dopant source layer 21 2 is formed conformal to the exposed fins and conformal to the patterned insulating buffer layer or blocking layer 209* and patterned P-type solid state dopant source layer 208’. In one embodiment, the Ν-type solid state dopant Sobrce layer 212 is a dielectric layer incorporating Ndype dopants therein such as, but not limited to, an N-type doped oxide, nitride or carbide layer. In a specific· such embodiment, theN-type solid state dopant source layer 212 is a phosphosilicate glass layer or an arsenic silicate glass layer. The N-type solid state dopant source layer 212 may be formed by a process suitable to provide a conformal layer on the exposed fins and the patterned insulating buffer layer or blocking: layer 209* and patterned P-type solid state dopant source layer 2|)8'. bur example, in one embodiment, the N-type solid state dopant source layer 2 Iis formed by a chemical vapor deposition (CVDj process Or other deposition process (e.g., ALD. PECVD, PVD, HDP assisted fVP. low temp CV’D) as a conformal layer above the entire;; structure ofilgureSC (having 210 removed there from). In a particular embodiment, the N-type solid state dopant source layer 212 jy it P.SCi layer or an AsSi 1 layer paving a phosphorous or arsenic, respectively, concentration approximately in the range of 0,1 - 10 weight#, In another embodiment, a capping layer can be formed on the X-type solid state dopant source layer 212 as an in .yim-forthM capping layer to protect the N-type solid state dopant source layer 212 during subsequent exposure: to ambient conditions, in one such embodiment; the capping layer is a nitride, carbide or alumina (ADOd capping layer, If is to be understood that the capping layer can be patterned in a same patterning operation, If any, as used for the N-type solid state dopant source layer o re — 1 " = [0056] kefening to Ipgure 2B, a patterned mask is formed over only a portion of the fins. As will be described in association with subsequent processing operations, tins masking Operation furiher enables distinction between fins for NMOS iteviee.) and fins for PMOS devices. In one embcjditnem, me mask m bpriiposed of a topographic rnaskingiporilQn 214 and, possibly, an anti-reflective coating (ARC) laser (not shown). In a particular such embodiment. ihcstopographic masking portion 214 is a carbon hurdmask (CflM) layer and llffi anii-rCRective coating layer is a silicon ARC,layer. The topographic masking portion 214 and die ARC layer may be patterned· with conventional lithography and etching process techniques. Referring again m Figure 2E the N-type solid state dopant source layer 212 is patterned, e.g., by a plasma, vapor or wet etch process, to form patterned N-type sol id state dopant; source layer 2122 [0057] In an alternative embodiment, the masking operations described in association with Ftgum 2||is eliminated from the picoCcSs iow, reducing the total number of masking Operations needed. Γη one such embodiment, then, the N-type solid state: dopant source layer 212 is not patterned anti is retained in both NMOS and PM OS locations. The patterned insulating buffer layer or blocking layer 209' inhibits dopants from such a non-pattemed N-type solid state dopant source layer 212 from entering sub-fin regions in locations where the patterned P-type solid state dopant source layer 208’ is intended as the doping source.

[0058] Referring to Figure 2F, topographic masking portion 214 is removed which may be performed rising a plasma, vapor or wet etch process. Also depicted in Figure 2F, an insulating buffer layer ψ blocking layer 2151 Such as An isolation nitride layer, is formed conformal to the patterned N-type solid state dopant source layer'll2'·and to the patterned insulating buffer layer or blocking layer 209’, e.g., to cap the patterned N-type solid state dopant source layer 212’. The insulating buffer layer or blocking layer 215 may be formed by a process suitable to provide a conformal layer. For example, in one embodiment, the insulating buffer layer or blocking layer 215 ts formed by a chemical vapor deposition fCVD) process or other deposition process (e.g., ALD, PIT Vi), PVD, ;}|ΟΡ assisted CVD, low temp CVD ; The insulating buffer layer or blocking layer 215 may be deposited whether or aoi the N-iyne solid state dopant source layer 212 is patterned, [0059] Referring to Figure 2(1. a dielectric fill layer 2! b is formed over the structure of Figure 2F. in one embodiment; the dielectric fill layer 216 is composed p| silicon dioxide, such as is used m a shallow trench isolation fabrication process. Fite dielectric Sill layer 21 p may be deposited by a chemical vapor deposition (CV'D) or other deposition process (e.g., API), PH('Vl). I’Vi), I !1.)P assisted t VD. low temp CVD); [0060] ReSerring to Figure 21!. die dielectric fill layer 216 is subsequently planarized to expose the top surfaces of the fins 202 (e.g.. exposing both NMOS and PMQS dedicated fins 202·. The dielectric fill Myer 216 may be planarized by chenueai mechanical polishing (OMR) techniques, The planarization also removes portions of the patterned P-type Solid slate dopant Source layer 208’, the patterned N-typCiSolid state dopant source layer 2 IS], anti line insulating buffer Myers or blocking layers 2095 and 215 if present, froth the tops of fins 202, in an alternative embodiment, a hardmask or other dielectric layer may be retained on top of the fins in order to eliminate or reduce gate control from the top of the fins (e.g., as in a double gate device versus a tri-gate device).

[0061] Referring agaiit to, Figure 2H, the dielectric fill, layer 216 is recessed to expose protruding petitions of fins 202. Additionally, the patterned P-type solid state dopant source layer 2082 the patterned N-type solid state dopant source layer 212', and the insulating butter layers or blocking layers 209’ and 215 if present, arc recessed to approximately the: same level as the dielecmc fill layer 216, as depicted in Figure 211 The recessing of these layers may be performed by a plasma, vapor or wet etch process. In one embodiment, a dry etch process selective to silicon fins is used, the dry etch prociip based on a plasma generated from gases such as, but not limited to NF3, CHfo, Cdf, HBr and Qa with typically pressures in the range of 30-100 m'l orr and a plasma bias of 50-1000 Watts.

[0062] Referring to Figure 21. a drive-in anneal is performed to provide doped sub-tin regions of the: fins dedicated to both NMOS and PMOS devices. Moreparficularly, upon heating, dopants from the patterned P-type solid state dopant source layer 208', such as boron dopant atoms, are diffused into the sub-in regions (those regions below the recessed dielectric fill layer 216) to form P-type dbped sub-fin regions 222. The diffusion may also lead to doping within the bulk substrate portion 200, where adjacent fins 202' share a common doped region ·22|’ in the bulk substrate 200. in this manner, the protruding portions of fins 202’ of ihe NMOS devices remain undoped or lightly doped, e.g., essentially retaining the doping profile of the original bulk substrate 200 and fins 202 described in association with Fighre 2A. AS a result) an interface 223 exists feetw&amp;n the protruding portions 202' and the P-type doped sob-in? regions 222. lit one such embodiment, the interface 222 represents a doping concentration step or rapid gradient change where the p-type doped sub-fin regions 222 have a total dopant concent rat ion of 2F.IK atoms/cm1 or greater, while the protruding portion:·; 202' have a toed dopant concentration significantly less than 21:18 atoms/em’-, e g., oi' approximately 51217 atoms/dnr* or less. The transition region can be relatively abrupt, as is described in greater detail below in association With Figures 4A and 4B, [0063] Additionally, upon the heating, dopants from the patterned N-type solid state dopant source:iayer232’, such as phosphorous or arsenic dopant atoms, are diffused into the sub-fin regions (those regions below the recessed dielectric till layer 216) tosfbrm N-type doped sub-fin regions 224. Tire diffusion may also lead to doping within the bulk substrate portion 200, where adpeent fins 202" share a common doped region 224' in the bulk Substrate 200. in this manner, the protruding portions:of fins 202" of the PMGS devices reman? undoped or lightly doped, e.g., essentially retaining the doping profile: of Ore original hulk substrate 200 and fins 202 described in association with Figure 2A. As a result, an interlace 226 exists between the protruding portions 222" and the N-type doped sub-fin regions 224. In ope such embodiment, the interlace 226 represents a doping concentration step or fapid gradient Change where the N -type doped Sub-fin regions 224 havd a total dopant concentration of 2E18 atoms/cM3 or greater, while the protruding portions 222" have: a total dopant concentration significantly less than 2Έ18 atomS/chr, e.g., of approximately 5E17 atoms/cnr dr less. The transition region can he relatively abrupt, as is described in greater detail below in association with Figures 4A and 4B, [0064] Referring again to Figure 2L the P-type doped sub-fin reasons 222 and the N-type doped sub-fin regions 224 are doped across the respective entire subfin regions, In one siieh embodiment, #aeh fin is approximately 10 nanometers Wide, and the dopant drive-in process Of Figure 2G requires only a 5 nanometer drive of dopants Iron? each side of the respective patterned l5-type solid state dopant source layer 208' or patterned N-type solid state dopant source layer 212'. In an embodiment, fhedrive-in operation is performed as a {e.ni|ieratum approxiiptely in the range of 800-1050 degrees Celsius.

[0065] In general· referring again to Figures 2A-2I,in an embodiment, borosilieate glass (B$Q) Is; implemented for NMQS fin doping, while a phosphosmeftg (PS( ·· or arsenic-silicate glass (AsSG) layer is implemented for PfvlOS fin doping, it is to be understood that, in another embodiment the conductivity types described in association with Figtires 2Λ-21 can be reversed, e.g„ N-type for P-type 'and vice versa, [0066] It is to he understood that the structures resulting froth the above exemplary processing schemes, e.g„ structure-, front Figures II and 21, may be used in a same pr similar form for subsequent processing operations to complete device fabrication, such as PMOS and NMOS device fabrication. As an example of a completed device, Figures 3A and 3B illustrate a cross-sectional view and a plan view (taken along the a-a! axis of the cross-sectional view), respectively, of a non· planar semiconductor device having fins with doped Sub-fin regions, In accordance with an embodiment of the present invention.

[0067] Referring to Figure 3 A. a semiconductor structure or device 300 includes a noil-planar active region (aig« a fin structure including:protruding fin portion 304 and sub-fin region 3.05) formed from substrate 302:, and within isolation, region 306, A gate line 308 is disposed over the protruding portions 304 of the non-planar active regibn as well as over a portion o|the isolation rUgion 306. As shown, gate line 308; includes a gate electrode 350 and a gate dielectric layer 352, In one embodiment, gated!ne 308 may also include, a dielectric cap layer 354. A gate contact 314, and overlying gate contact via 316 are also seen from this perspective, along with an overlying; metal interconnect 360, all, of which are disposed in interlayer dielectric stacks or layers 370. Also seen from the perspective of Figure: 3 a. the gate contact 314 is, in one embodiment, disposed over isolation region 306, but not over the non-planar active regions. As is also depicted in Figure 3 A, an interlace 380 exists between the doping profile of protruding fin portion 304 and sub- Sin region 305. The interface 380 can be a transition region that is relatively abrupt, as is described in greater detail below in association with Figures 4A and

4 B

[0068] Referring to Figure the g.ue hue 308 is shewn as disposed Over: the protruding fin portions 304. Source and drain regions 304A and 304B rifthe protruding On portions 304 can be seen from this; perspective·. in One embodiment, the source and drain regions 304A:::and 304B are doped portions ¢1 original material of thetproirnding fin portions 304. Ifi another embodiment, the material of the prritruding tin portions 304 is removed and replaced with another semiconductor material, e.g., by epitaxial deposition, in either case, the sourCe and drain regions 3()4Λ and 30413 indy extend below the height of dielectric layer 306, lie;, [tub the sub-fin region 305. in accordance with an embodiment of the; present invention, the more heavily doped sub-fin regipins, i.e., the doped porti ons of the fins below interlace 380, inhibits source to drain leakage through this portion of the bulk semiconductor fins; [0069] In an CnibotHnierst, the semiconductor structure or device 300 is a non-planar device such as, but not liriiited to, a fin-PF 1' or a tri-gate device. In such an cuTbtsdiment, a corresponding semiconducting channel region is coriipbsed of or is formed,! n a three-dimensional body. In one such embodiment, the gate, electrode stacks of gate lines 308 Surround at least a top surface and a pair of sidewalls of the three-dimensional body.

[0070] Substrate 302 may be composed of a semiconductor material that can withstand a manufacturing processand in which charge can migrate. In an embodiment, substrate 302 is a bulk substrate composed of a crystalline silicon, silteon/gerhianiUm or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form active region 304. In one embodiment, the concentration of Silicon atoms in hulk substrate 302 is greater than 97%¾. In another embodiment, bulk substrate 302 is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a borpn-doped bulk silicon mono^crystalline substrate. Bulk Substrate 392 may alternatively be cbmppsed of a group III-V material. In an embodiment, bulk substrate 302 is composed of alili-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, mdiutn phbsphide, indium antimomde. indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate 302 is composed of'a Πί-V material and the charge-carrier dopant impurity atoms areones such as, Hut not limned to, embmi. silicon, germanium, oxygen, sulfur, selenium or tellurium.

[0071] isolation region 306 may He composed Of a material suitable if) ultiptaiely electrically isolate, or contribute t.6 the isolation of, portions of a permanent gate structure from an underlyistg:bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embbduitent, tire isoteiiomregion 306 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon - or. -nitride. silicon nitride:, or carbon-doped silicon nitride, [0072] Gate link 308 may be composed of a gate electrode stack: which includes a gate dielectric layer 352 and a gate electrode layer 350. lit an embodiment, the gate electrode of the gatfcteieetrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride. hafnium silicate, lanthanum oxide, xirconiuih oxide, zirconium silicate, tantalum oxide, barium strontium: tiianate, barium tiianate. strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zine niobate. or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top lew layers of the substrate 302. in an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed Of an oxide of a semiconductor material, In one embodiment, the gate dseiectnc layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitnde.

[0073] In one embodiment, the gate eiccirode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal siliciddS, metal aiuminidex, hafnium, zirconium, titanium, tantalum, altndinuffl, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. 1st a..speCjpg. embodiment, the gate electrode is composed of a non-workfunetion-seuing fill material formed above a metal workifunetion-setiing layer.

[0074; Spacers associated with the cum electrode stacks re ay be composed (if a materia! suitable to ultimately electrically isolate, or contribute to the isolation oft:a permanent, gate structure from adjacent conductive contacts,: such as self-aligbed e^nltcis. For example, in one embodiment, the spacers are composed of a dieieeinc i'Mteriai such as, but not limited to, silicon dioxide. |ilicon oxy-nitridc, silicon nitride, or carbon-doped silicon nitride.

[0075] Gate contact 314 and overlying: gate contact via 316 miy be composed of a conductive material, in an embodiment, one or more of the contacts or vias are Composed of a metal species. Hie mesa! species may be a pure metal, Sitch; as tungsten, nickel, or cobalt, or may bean alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g,. such as a silieide material), [0076] In an embodiment (although not shown), providing structure 300 involves formation of a contact pattern which is essentially perfectly aligned to an existing gate pattern while eliminating, the use of a lithographic step with exceedingly tight registration budget, In one such embodiment, this approach enables the use: of intrinsically highly selective wet etching (e.g., versus •Conventionally implemented dry or plasma etching) to generate contact openings.

In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

[0077] Furthermore, the gate stack structure 308 may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as poly-Silicon or silicon nitride pillar material, may he removed and replaced with permanent gate electrode material, in one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In :m emborimnms. dummy gates are removed by a dry etch or wet etch process:. In one embodiment, dummy gates are composed of polycrystalline silicon Or amorphous silicon and are tmnoved with a dry etch process including use (:181¾. in antither embodiment, dummy gates arc composed of pohcrysiailme silicon or amorphous silicon and are removed with a wefetch process including use. of aqueous MFOii Or tetramethylammonium hydroxide. In One embodiment, dummy gates; are composed of silicon nitride and are removed with a we; etch including aqueous phosphoric acid.

[0078] In an embodiment, one or more1 approaches described herein Cbntempiafe essentially a dummy and replacement gate process in coitMttauon with a dummy and replacement contact process to arrive at.structure 3(50. in one such •embodiment, the replacement contact process is perforated after the:replacement gate process to allow high temperature anneal of at least a portion of the permanent, gate stack. For example, in a specific such: embodiment; an anneal oiat least a portion of the permanent gate structures. e.g., after a gate dielectric layer is formed, is performed at a teiftperature greater than approximately 600 degrees Celsius, 'The anneal is performed prior to formation of the pennanent contacts.

[0079] Referring again to Figure 3A, the arrangement of semiconductor structure or device 300 places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use oflayout space, In another embodiment; however., a semiconductor device has contact: structures that: contact portions of a gate electrode formed over an active region, In general, prior to (e.g,, in addition to) forming a gate Contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present invention include first using agate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g.. for integrated circuit fabrication. In an embodiment; a trench contact pattern is formed as aligned to an existing: gate, pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to anexisting gate patient in combination with selective contact etches. For example. a: conventional process may include patterning of a poly (gate) grid with separate' patterning Of |()nt|dt features.

[0080] As described above, one or more embodiments confine, or essenuaiiy confine, dopants front a doping process to a sub-fin region of a semiconductor device. As an example, Figure 4Λ is a simulaied 2-1) contour plot 400 demonstraiing boron dopant confinement to sub· fin regions, in accordance with an embodiment of the present i n vent ion. in another example, figure 4B is a simulated .: I) contour plot 402 demonstrating phosphorus dopant confinement to sub fin regions, in accordance with an elhbodiihent:of the present invention. Referring to FiguresdA and 4R, fhei transition of doping concentration drops quickly from Urn subfin region to the protrudingd'tn region, Tn one such embodiment, the transition is essentially immediate with a dopant concentration of less than approximately 51.17 atoms/cnr for each of the protruding portions and of greater than approximately 2£18 atoms/cmhfqr the corresponding sub-fin regions.

[0081] Additionally, as is also described above, substrate portions below the subfin regions shay be doped, in one senje forming well regions, in order to exemplify the concept of downward diffusion from a solid state doping source into an underlying substrate, Figure s is a measured 1-D SlViS do|)antprofile 500 demonstrating diffusion of dopants front a doped insulator layer into a silicon substrate, in accordance with an embodiment of the present invention.

[0082] It is to be understood that not all aspects oftihe processes described above need be practiced to fall within the spirit and scope of embodiments of the present invention. For example, in one embodiment, dummy gates need not ever be Formed prior to fabricating gam Contacts over active portions of the gate stacks. The gate stacks described above hiay actually be permanent gate stacks as initially formed. Also, the processes described herein may he used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an eihbodiment; the semiconductor devices are a metal-oxide semiconductor (MOS) transistors lor logic Or memory, or are bipolar transistors. Also, ip.an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, or a FIN-fET. One or more embodiment:··; may be. particularly useful for fabricating semiconductor devices as a 10 nanometer (It) nm) or smaller technology node.

[0083] Figure 6 illustrate'· a compurin| deviec i|()0 in accordance With one implementation of the invention. The computing device 600 houses a board 602.

The1 board 602 may indude a number oilebmponenis, including tmtrimdmihed to a processor 604 and a! least on·..· eommimieationchip 606, inc processor 604 is physically and elecmcaily coupled ίο rhe board 6(12. in some implementations the at. least one communication chip 606 is also physically and deeinpally coupled to the board 6(13:. in (under implemenuiumo. the communication chip 606 is pari of the processor 604, [0084] Depending on its applications, computing device 660 may include Other components that may or may pot be physically and electrically coupled to the board 603, These ether components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g,. ROM), (lash memory, a graphics processor, a digital Signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GRS) device, a compass, an accelerometer, a gyroscope, a speaker, a earner;!., and a mass storage device:(such as hard disk drive, compact disk (GD), digital versatile disk1 (DVD), and so :forth).

[0085] The compiunicationehip 606 enables wireless communications (dr the transfer or data to and irons the computing device 600. The term “wirelesT^and its derivatives may be used to describe clouds, devices, systems, methods, techniques, communications channels, etc.,, that may communicate data through the use όί mode need electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. d’he communication chip 606 may implement any of a number of wireless standards Or protocols, including but not limited to WE FiflEEE 802.11 family), WiMAX rii KI AD. 16 family), IEEE 802.20. long term evolution (LTE), Εν DO, HSFA f, HSDl'A-K ilSGEA-h EDGE, GSM, GPRS.

CpM A, TDM A, DECT, Bluetorifh, derivatives thereof, as well as any other wireless protocols that aife designated as 30, 4U. 5G, and beyond. The computing device 600 may include a plurality of coritmtinicaifen chips 606. For instance, a first eoimriunieaiibrs chip 606 may be dedicated to shorter range wireless communications such as Wi-Fi and Blue moth and a Second Mmmimieationchip 606 may be dedicated ίο ledger range wireless eomhnmieadons meh as GPS, EDGE. GPRS, (’DMA, WiMAXX'iS, Ev-DO, and others.

[0086] ’The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In some implementations oi'crnbodiiiuo-is of the invention, the integrated circuit die of the pMeessdr includes one or more devices, sdeh as MOS-EET transistors hulk in accordance with implementations oithe invention. 'Ifie term ‘Droce4SQ:r'" may refer to any device or poruon of a device that processes electronic data 6can registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

[0087] The communication Chip 606 also includes an integrated circuit die packaged within the Coiiuhtirtication chip 606. In accordance with another implemenhltion of the invention, the integrated circuit die of the communication chip includes one or more device^ Such as MOS-FET transistors built in accordance with imnlementations of the invention. Λ· [0088] In further implementations, another component housed within the computing devicesbiK) may contain an integrated circuit die that includes oncer mow devices, such as: MOS-EET transistors bulk in accordance wish implementations of embodiments of the invention.

[0089] In various embodiments, the computing device1600 may he a laptop, a netbook, a notebook, an ultrahook, a smartphone, a tablet, a persona! digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 600 may be any other'electronic device that processes data.

[0090] Thus, embodiments of ihe present invention include non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions.

[0091] In an embodiment, a method of fabricating a semiconductor structure involves pfenning a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate. coniormal with the phmdily ol semiconductor Tins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a ton surface oi the plurality oi semiconductor bps, exposing prottuding portions ofeaeh of the pldraliiy o! Semiconductor fins above sub-fin regions oi each of the plurality of semiconductor ip|. The method also involves driving dopants from the Solid state dopant source layer into the: sub-In· regions of each of the plurality Of semiconductor fins, [0092] In one embodiment, forming the solid state dopant source layer involves forming a horcsilicate glass (BSGl layer.

[0093i In one embodiment, forming the solid state dopant source layer involves forpring a phosphosilieaie glass (PSG) layer or an arsenic silicate glass (AsSG) layer.

[0094] In one embodiment, the method further Involves forming a gate electrode conformal with the protruding portions of each of the plurality of semiconductor fins, and forming source and drain regions in the protruding portions of eaeh of the plurality of semiconductor fins, cm either side of tin- gate electrode.

[0095] In ope embodiment, driving dopants from the solid state jopant sodrCe layer into the sufvfin regions of each of the plurality of semiconductor fins involves iormmg a dopan; concentration interface between each of the protruding portions and corresponding subyfirt regions ofeaeh of the plurality of semiee-nilueior fins.

[Θ096] in one embodiment, forming the plurality of semiconductor fina above the semiconductor substrate involves forming a plurality of single crystalline silicon ftps continuous with a bulk single crystalline: substrate, [0097] In an embodiment, a method of fabricating a semiconductor structure involves forming first and second pluralities of semiconductor fins above a semiconductor Subsifatd, A PAype solid state dopant source layer is formed above the semiconductor substrate, on and conformal with the first plurality of Semiconductor fins, A dielectric layer is i'ormed above the P-type solid stile dopant: sburde layer, Tire dielectric layer and the T-type solid state dopant source layer ire: planarized to expose a top surface of eachdf the first and second pluralities of semiconductor fins. S'-type dopants am implanted into die second plurality of fins, hat: no!: into the first plurality of fins. The dielectric layer and thoP-type solid state dopant source layer are recessed to approximately a same level below the top surface of each of the first and second pluralities ofsemieonduetor ['ins:, exposing protruding portions of each of the first andjecond pluralities of senuconduetor fins above sub-fin regions ff each of the first and second pluralities of semiconductor dins, The method also: involves driving dopants front she P-type spiel shite dopant source layer into the sub-Tin regions of each o! the first plurality of Semiconductor fins but not the second plurality of semiconductor fins, [0098] in one embodiment, forming the P-type solid state dopant source layer involves forming a global P-type solid state dopant source layer on and confdriMlwith the first and second pluralities of semiconductor fins, and removing1 the global P-type sblid state dopant source layer from the second plurality oil semiconductor fins hut not the first plurality Of semiconductor fins.

[8099] In one embodiment, the method further involves, subsequent to removing the global T-typemolid state dopant source layer front the,second plurality of seiJueonductprJiits but not the first plurality of semiconductor fins, forming:a buffer dielectric layer on and conformal with the P-type solid state dopant source layer and on and with the second plurality of semiconductor fins.

[06100] In one eitibOditnenL P>ntiing;the p-type solid state dqparsi: source layer involves forming a bbrosilicate glass fBSCijrJj layer.

[00101] In one embodiment, the method further involves ion nine an N-type gate electrode conformal with the pro; aiding portions of each of the fi rst plurality of semiconductor fins, forming a P-type gate electrode: conformal with the protaiding portions of each of the second plurality of semiconductor fins, and forming source and drain regions in the protruding portions of each of the first and second pluralities of semiconductor fins, on either Side of the corresponding gate electrode. [6O102] in one embodiment, driving dopants froth the [’-type solid state dopant source layer into the sub-fin regions bf each of the first plurality Of semiconductor fins involves forming a dopant concentration interlace between each of the protruding portions and corresponding sub-fin regions of each of the first plurality of semiconductor tins.

[00103] In one embodiment, forming: the first and second pluralities: Of semiconducfppifihs above the semiconductor substrate invfo ves forming first and second pluralities of single crystalline silicon tins continuous with a hulk single crystalline substrate.

[00104] In an eihbodifoeni, a method of fabricating a sentioonducidr Structure involves forming Host and second pluralities of semiconductor fins above a semiconductor substrate. Λ P-i.ype sol id stale dopant source layer is fonned above the semiconductor substrate, on and conformal with the first plurality of semiconductor Tm&amp; An bi-type solid slate dopant source layer informed above the semiconductor substrate, on and conformal with the second plurality of semiconductor fink A dielectric layer is fonned above the fo-type solid state dopant Source layer and above the N-type Solid slate dopant source layer. The dielectric layer, the P-type solid State:dopant source layer and the N-type solid state dopant sou foe layer are recessed to approximately a satire level below a top surface of each of foufifst and second pluralities of sbmmonduefor firs, exposing protruding portions of each of the first and second pluralities, of semiconductor fins above sub-fm regions of each of foe first and Second pluralities:of Semiconductor fins, 'fhe method also involves driving; dopants from the P-type solid state dopant source layer into foe sub-ffo regions of each of foe first plurality of semiconductor fins but not foe second plurality of;Semiconductor fins, and driving dopants front the Pi-type solid state dopant soured: layer into the sufofin regions of each of the second plurality of semiconductor fins but not the first plurality of semiconductor fins.

[00105] In one embodiment, foe driving dopants from the P-type solid state dopant soured layer into the sub-fin regions of each of the first plurality of semiconductor fins and foe driving dopants from the N-type solid state dopant sburcC layer into the sub-ffo regions of each of the second plurality of semiconductor fins are performed in a same process operation.

[00106] In one embodiment, forming foe IMype solid slate dopant source layer involves fonfong a global P-lype solid state dopant Source layer on and conformal with the first and second pluralities of semiconductor fins, and removing the global IMype solid state dopant source layer front the second plurality of seniicondueior bus but not the first plurality of semiconductor fins.

[00107] ίη ono embodiment, the methtjd further i n voices, subsequent to removing the global i’-fype solid state dopant source layer from the second plurality of semiconductor 11ns, forming %JbigPlr dielectric layer on and eon formal with the P-lype Solid state dopant source layer.

[Oft 108] In one embodiment, forming tlm N-type solid State dopant source layer involves Idnning a global N-type Solid state dopant source layer on and conformal with the second plurality of semiconductor fins and above: the: P-type solid state dopant source layer, and removing the global N-type solid state dopant: source layer Irani above the P-type solid state dopant source layer but not from the second plurality of semiconductor fins.

[00109] in one embodiment, the method further involves, subsequent to removing the global N-type solid state dopant source layer front above the P-type solid state dopant source layer,:donning a buffer dielectric layer on and conformal with the N-type solid state dopant source layer and on and conformal with the P-type solid state dopant source layer.

[00.110] in one embodiment, forming the P-tyne solid state;dopant: source layer involves forming a borosdieate glass {BSG) layer, and Idnning the N-type solid static dopant, source layer involves forming a phosphosilieate glass (PSU) layer or an arsenic silicate glass (AsSG) layer.

[00111] In one embodiment, the method fdn-her involves forming an N-type gate electrode conformal with the protruding portions of each of the first plurality of semiconductor fins, forming a P-type gate electrode conformal with the protruding portions of each of the second plurality of Semiconductor fins, and forming source and drain regions in the protruding portions of each of the first and second pluralities of semiconductor fins, on either side of the corresponding gate electrode.

[00112] fn bnC embodiment, driving dopants from the P-type solid stale dopant Source layer into the sub-fin regions of each of the first plurality bf semiconductor fins involves forming a dopant concentration interface between each of the protruding portions and corresponding sub-pit regions of each of the first plurality of semiconductor fins, and driving dopants from the N-type solid state dopanfsource layer into the sub-fin regions of each of the Second plurality of semiconductor fins involves forming a dopant concentration interlace between each of the protruding portions and corresponding .sub-fir· regions oi each of the second plurality of semiconductor ins.

[00113] in one embodiment, forming ihoirst and:seecmd: pluralities of semiconductor fins abpve the seupeonduclor substrate involveslortviing first and second pluralities of single crystalline silicon fins epn|:inU(Mi8 with a hulk single1 crystalline substrate.

[00114] in an embodiment, a semiconductor structure includes a plurality of semiconductor fins disposed above a semiconductor substrate. Λ solid state-dopant source layer is disposed above:die semiconductor substrate, conformal with sub-tin regions pl each of the plurality of semiconductor fins but only to a level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above the sub-fin regions of each of the plurality of semiconductor fins. A dielectric layer is disposed above the solid State dopant source layer, the dielectric layer having a top surface approximately eo-planar with the level below the top surface of the plurality of semiconductor fins: A dopant concentration interface is between each of the protruding portions and corresponding sub-fin regions of each of the plurality of semiconductor fins.

[00:115] In one embodiment, the solid state dopant source layer is a borUsUicaie glass (BSG) layer.

[00110] fn one embodiment, the solid state dopant source layer is a pbosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer, [00117] In one embodiment, the semiconductor structure further includes a gate electrode disposed conformal with the protruding portions of each: of the plurality of semiconductor fins, and source and drain regions disposed in the protruding portions of each of the plurality oi semiconductor fins, on enher ssde of the gate electrode.

[00118] in one embodiment, tire plurality of semiconductor fins disposed above the semiconductor substrate is a plurality of single crystalline silicon fins continuous with a bulk single crystalline Substrate.

[00119] In one embodiment, the dopant concentration interface is art abrupt transition of less than approximately 51517 atoms/cnv' for each of the protruding

mmERHD FEATURES 1. A method of iahncatuig a semiconductor structure, the method comprising: forming a plurality of semiconductor tins above a semiconductor substrate; forming a solid state dopant source layer above the semiconductor substrate, conformal with the plurality of'semiconductor tins: forming a dielectric layer above the solid state dopant source layer; recessing the dielectric layer and die solid state dopant source layer to approximately a same level below a top surface o f the plurality of semiconductor fins, exposing protruding: portions of each of the plurality of semiconductor tins above subfin regions of each of the plurality of semiconductor fins; and driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins, 2. The method of clause i, wherein forming the solid state dopant source layer comprises forming a borosilicate glass (BSG) layer. 3. The method of clause I, wherein forming the solid state dopant source layer comprises forming a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer. 4. The method of clause 1, further comprising; forming a gate electrode conformal with the protruding portions of each of the plurality of semiconductor fins; and forming source and drain regions in the protruding: portions of each of the plurality of semiconductor fins, on either side of the gate electrode. 5. The method of clause 1, wherein driving dopants from the solid state dopant source layer: into thg sub-fin regions of each of the plurality of semiconductor fins comprises forming a dopant concentration: interface between each of the protruding portions and corresponding sub-fin regions of each of the plurality of semiconductor fins. 6. The method of clause 1, wherein forming the plurality of semiconductor fin-s above the semiconductor substrate comprises forming a· plurality of single crystalline silicon fins continuous with a bulk single crystalline sunstrate. 7. A method of fabricating a semiconductor structure, the method comprising: forming first and second pluralities of semiconductor fins above a semiconductor substrate; forming a P-type solid state dopant source layer above the semiconductoi substrate, on and conformal with the first plurality ot semiconductor fins; forming a dielectric layer above the P-type solid state dopant source layer; planarizing the dielectric layer and the;P-type solid state dopant source layer to expose a top surface of each of the first and second pluralities of semiconductor fins; implanting N-type dopants into the second plurality of fins, but not into the first plurality of fins; recessing the dielectric layer and the P-type solid state dopant source layer to approximately a same level below the top surface of each of the first and second pluralities of semiconductor fins, exposing protruding portions of each of the first and second' pluralities of semiconductor fins above sub-tin regions of each of the first ;tnd second pluralities of semiconductor fins; and driving dopants from the P-type solid state dopant source layer info the sub-fin regions of each of the first plurality of semiconductor tins but not the second plurality of semiconductor fins. 8. The method of clause 7, wherein forming the P-type solid state dopant source layer comprises: forming a global P-type solid state dopant source layer on and conformal with the first and second pluralities of semi conductor ii ns; and removing the gloeal P-type solid state dopant source layer from the second plurality of semiconductor tins but not the first plurality of semiconductor fins. 9. The method oi'clause $, further comprising: subsequent to removing the global P-type solid state dopant source layer from the second plurality of semiconductor tins but not the first plurality of semiconductor fins, forming a buffer dielectric layer on and conformal with the P-type solid state dopant source layer and on and with the second plurality of semiconductor tins. 10. The method of clause 7, wherein forming the P-type-sol id state dopant source layer comprises forming a horosilicate glass (BSG) layer. I 1. The method of clause 7, further comprising: forming an N-type gate electrode conformal with the protruding portions of each of the first plurality of semiconductor fins; forming a P-type gate electrode conformal with the protruding portions of each of the second plurality of semiconductor tins; and forming source and drain regions in the protruding portions of each of the first and second pluralities of semiconductor fins, on either side of the corresponding gate electrode. 12. The method of clause 7, wherein driving dopants from the P-type solid state dopant source layer into the sub-fin regions of each of the first plurality of semiconductor fins comprises forming a dopant concentration interface between each of the protruding portions and corresponding sub-tin regions of each of the first plurality of semiconductor fins. 13. The method of clause 7, wherein forming the first and second pluralities of semiconductor fins above the semiconductor substrate comprises terming first and second pluralities of si ngle crystal line silicon fins continuous with a bulk single crystalline substrate. 14. A ihethod οί fabricating a semiconductor structure,: the method comprising-terming first and second pluralities of semiconductor fins above a semiconductor substrate; forming a P-type solid state dopant source layer above the semiconductor substrate, on and conformal with the first plurality of semiconductor fins; tormina; an N-type solid state dopant source layer above the semiconductor substrate, on and conformal with the second plurality of semiconductor fins; forming a dielectric laver above the Retype solid state dopant source layer and above the N-type solid state dopant source layer; scv,essing tue dielectric layer, the P-type solid state dopant source layer and the N-type solid state dopant source layer to approximately a same level below a top surface of each of the first and second pluralities of semiconductor fins, exposing protruding portions of each of the first and second pluralities of semiconductor fins above sub-fin regions of each of the first and second pluralities of semiconductor fins; driving dopants from the P-type solid state dopant source*layer into the sub-fin regions of each of the first plurality of semiconductor fins but not the second plurality of semiconductor fins; and driving dopants from the N-type solid state dopant source layer into the sub-fur regions of each of the second plurality of semiconductor fins but nod the first plurality of semiconductor fins. 15. The method of clause 14, wherein the driving dopants from the P-type solid state dopant source layer into the sub-fin regions of each of the first plurality of semiconductor flits and the driving dopants from the N-type solid state dopant source layer into the sub-tin regions of each of the second plurality of semiconductor fins are performed in a same process operation. 16. The method of clausa, 14, whetreift forming; the P-type solid state dopant source layer comprises: forming a global P-type solid state dopant source layer on and conformal with the first and second pluralities of semiconductor fins; and removing the global P-type solid state dopant source layer Iron·) the second plurality of semiconductor fins but not the first plurality of semiconductor fins. 17. The method of clause 16. further comprising: subsequent to removing the global fi-fype solid state dopant source layer from the second plurality of semiconductor fins, forming a buffer dielectric layer on and conformal with the P-type solid state dopant source layer. 18. The method of clause 14, wherein forming the N-type solid state dopant source layer comprises:

Harming a global N-type solid state dopant source layer on and conformal with tire second plurality of semiconductor fins and above the P-type solid state dopant source layer; and removing the global N-type solid state dopant source layer from above the P-type solid state dopant source layer but not from the second plurality of semiconductor fins. 19. The method of clause 18, further comprising: subsequent to removing the global N-type solid state dopant source layer from above the P-type solid state dopant source layer, forming a buffer dielectric layer on ant! conformal with the N-type solid state dopant source layer anti on arid conformal with the P-type solid state dopant source layer. 20. The method of clause 14, wherein forming the P-type solid stale dopant source layer comprises forming a borosilicate glass (BSG) layer, and wherein forming the N-type solid state dopant source layer comprises forming a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer. 21. The method of clause 14, further comprising: forming an N-type gate electrode conformal with the protruding portions of each of the first plurality of semiconductor fins; forming a P-type gate electrode conformal with the protruding portions of each of the second plurality of semiconductor fins: anti; forming source add drain regions in the protruding portions oi each ot the first and second pluralities of semiconductor fins, on either side ot the corresponding gate electrode. 22. The method of clause 14, wherein driving dopants from the P-type solid state dopant source layer into the sub-fin regions oi each ot the first plurality of semiconductor fins comprises forming a dopant concentration interlace between each of the protruding portions and corresponding sub-tin regions of each ot the first plurality of semiconductor fins, and wherein driving dopants from the N-type solid state dopant source layer into the sub-fin regions or each oi die second plurality of semiconductor fins comprises forming a dopant concentration interface between each of the protruding portions and corresponding sub-fin regions of each of the second plurality of semiconductor fins. 23. The method of clause 14, wherein forming the first and second pluralities of semiconductor fins above the semiconductor substrate comprises forming first and second pluralities of single crystalline silicon fins continuous with a bulk single crystalline substrate. 24. A semiconductor structure, comprising: a plurality of semiconductor fins disposed above a semiconductor substrate;, a solid state dopant source layer disposed above the semiconductor substrate, conformal with sub-fin regions of each of the plurality ot semiconductor fins but only to a level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality ot semiconductor fins above the sub-tin regions of each of tire plurality o f semiconductor fins; a dielectric layer disposed above the solid state dopant source layer, tne dielectric layer having a top surface approximately cotpianar with the level below7 the top surface of the pluraiity of semiconductor fins; and a dopant concentration interlace between each of the protruding portions and corresponding sub-tin regions of each of the plurality of semiconductor fins. 25. The semiconductor structure of clause 24, wherein the solid state dopant source layer is a borosilicate glass (BSG) layer. 26. The semiconductor structure of clause 24. wherein the solid state dopant source layer is a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer. 27. The semiconductor structure of clause 24, further comprising: a gate electrode disposed conformal with the protruding portions of each of the plurality of semiconductor fins; and source and drain regions disposed in the protruding portions of each of the plurality of semiconductor fins, on either side of the gate electrode. 28. The semiconductor structure of clause 24, wherein the plurality of semiconductor fins disposed above the semiconductor substrate is a plurality of single crystalline silicon fins continuous with a bulk single crystalline substrate. 29. The semiconductor structure of clause 24. wherein the dopant concentration interlace is an abrupt transition of less than approximately 5E17 atoms/cnr for each of the protruding portions and of greater than approximately 2Η18 atoms/em ’ for the corresponding sub-fin regions of each of the plurality of semiconductor fins.

Claims (22)

2. 3. Ail: integrated circuit structure, comprising: a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion; a second fin comprising silicon, the second fin having a lower fin portion arid an upper fin portion; a layer comprising a phosphosilicate glass (PSG), the layer comprising the PSG directly onsidewalls of the lower in portion of the first fin; a layer Comprising a borosificate glass (BSCfi, tire layer comprising the BSG directly on; sidewalls of the lower fin portion of the second fin. wherein an end of the layer comprising the BSG is in contact with ap epd of the layer comprising the PSG at a location between the lu st fin and the second fin; a first insulating layer comprising nitrogen, the first insulating layer directly on the layer comprising the BEG directly on the sidewalls of the lower fin portion ofithe second fin; a second insulating layer comprising nitrogen, the second insulating layer directly on the layer comprising the PSG directly on sidewalls of the lower fin portion of the first fin, the second insulating layer over the first insulating layer directly on the layer comprising the BSG directly on the sidewalls of the loWer I'm portion of the second fin; a dielectric fill material directly on the second insilatijfg layer directly on the layer comprising the PSG directly on the sidewalls of thedower fin portion of the first; fin, the dielectric fill material directly on the second insulating layer over the first insulating layer directly on the layer comprising the BSG directly on the sidewalls of the lower fin portion of the second fin, wherein the dielectric fill material comprises silicon and oxygen; a first gate electrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the first fin, the first gate electrode over t|e dielectric fill material; and a second fate elietrode over a top of and laterally adjacent to sidewalls of the upper fin portion of the: second fin, the:1 second gate electrode over the dielectric fil l material.

   2. The integrated circuit structure df claim 1., wherein the end of the layer comprising the BSG is a terminating end. and the end of the layer comprising the/PSG is a terminating end.

   3. The inte|rated circuit structure of claim 2, wherein the terminating end of the: layer comprising the BSG and the term|pat.ing end of the layer comprising the pSG meer ah an approximately vertical interface between the terminating end of the layer comprising the BSG and the terminating end of the layer comprising the/PSG,
3. 4. The integrated circuit structure of claim 1, further comprising: a first gate dielectric layer between the first gate electrode and the upper tin portion of the first fin; and/or a second gate dielectric layer between the second gate electrode and the upper fin portion of the second fin.
4. 5. The integrated circuit structure of claim 4,. wherein the first gate dielectric layer comprises a first high-k dielectric layer, and/or wherein the second gate dielectric layer Comprises a second high-k dielectric layer.
5. 6. The integrated circuit structure of claim 1, wherein the lower fin portion of the first fin has a phosphorous concentration greater than approximately 2E18 atoms/enrh
6. 7. The integrated circuit structure of claim X, wherein the upper fin portion of the first fin has a phosphorous concentration less than approximately 5El7 atoms/enr.
7. 8. The integrated circuit structure of claim 1. wherein the lower fin portion oS me first fin has a phosphoroirt concentration greater than approximately 2fi 18 atoms, cm j and where: n the Upper fin portion of the first fin has a phosphorous conceotrationiess than approximately 5EI7 atoms/'cm3.
8. 9. Ί he integrated circuit structure of claim 1, wherein the lower fin portion of the second fin has a boron concentration greater than approximately 2E18 atoms/cnr’,
9. 10. The integrated circuit structure of claim 1, wherein the upper tip portion of the second fin has a boron concentration less than approximately 5E17 atoms/cm3. 11;, The integrated circuit structure of claim 1, wherein the lower fin portion of the second fin has a boron concentration greater than approximately 2E18 atoms/cm3, and wherein the upper fin portion of the second Jin has a boron concentration less than approximately 51/17 atoms/cmf
10. 12, An integrated circuit structure, comprising: a first fin comprising silicon, the first fin having a lower fin portion and an upper fin portion; a second fin comprising silicon, the second fin having a lower fin portion and an tipper fin portion; a first dielectric layer comprising an N-type dopant, the first dielectric layer directly on sidewalls of the lower tin portion of the first fin; a second dielectric layer comprising a P-type dopant, the second dielectric layer directly on sidewalls of the lower fin portion of the second fin, wherein an end of the second dielectric layer is in contact with an end of the first dielectric layer at a location between the first fin and the second fin; a first insulating layer comprising nitrogen, the first insulating layer directly on the second dielectric layer directly on the sidewalls of the lower fin portion of the second fin; a second insulating layer comprising nitrogen, the second insulating layer directly on the first dielectric layer directly on sidewalls of the lower fin portion of the first fin, the second insulating layer over the first insulating liiyer directly on the second dielectric layer directly on the sidewalls ofthejower fin portion of the second:: fin: άdielectric fill ggmterfal directly on 11½ second insulating layer directly on the first dielectric layer directly on the sidewalls of the lower fin portion of the first for the dielectric fill material directly on the second Insulating layer over the first insulating layer directly on the second dielectric layer directly on the sidewalls of the dower fin portion of the second fin, wherein the dielectric: fill material comprises silicon and oxygen; a ftr&amp;t gate electrode over a top iof and laterally adjacent to sidewalls of the upper fin portion of the first fin, the first gate electrode over the dielectric fill material; and a second gate el ectrode over a top ofiand laterally adjacent to sidewalls of the upper; fin portion of the second fin, the second gate electrode over the dielectric fill mat|rial.
11. 13. The integrated circuit Structure of claim 12, wherein the N-typc dopant is phosphorous.
12. 14. Tfie integrated circuit structure of claim I t? wherein the "N -type dopant is arsenic.
13. 15. The integrated circuit structure ofoiaim 12, wherein the P-type dopant is boron, 16. 1'he integrated circuit structure of claim 12, wherein the end of the second dielectric layer is a terminating end, and the end of tlre first dielectric layer is a terminating end.
14. 17. The integrated circuit struct me of claim 16, wherein: the terminating end of the second dielectric layer and the terminating end of the first dielectric layer meet at an approvima?civ vertical interface between the terminating end of theisecbnd dielectric layer anil; the terminating end of the first dielectric layer.
15. 18. The integrated circuit structure of claim 12, further comprising: a first gate dielectric layer between the first gate electrode and the upper fin portion of the first fin; and/or a second gate dielectric layer between the second gate electrode and the Upper fin portion of the second fin.
16. 19. The integrated circuit structure of claim 18* wherein the first gate dielectric layer comprises a first high-k dielectric iayer, and/or wherein the second gate dielectric layer comprises a second high-k dielectric layer.
17. 20. The integrated circuit structure of claim 12, ’wherein the lower fin portion of the first fin has a concentration of the N-type dopant of greater than approximately 21:: 18 atorns-cm".
18. 21. The integrated circuit structure of claim 12* wherein the upper fin portion of the first fin fias a concentration of the hi-type dopant of less than approximately 5E17 atorns/cnf,
19. 22. The integrated circuit structure of claim 12, wherein the lower fin portion of the first fin has a concentration of the N-type dopant of greater than approximately 2E1.8 atoms/cm3, and wherein the upper fin portion of the first fm has a concentration of the hi-type dopant of less than approximately SE17 atorns/croT
20. 23. The integrated circuit structure of claim 12, wherein the tower fin portion of the second fin has a concentration of the P-type dopant of greater than approximately 2E18 atoms/cmh
21. 24. The integrated circuit structure of claim 12, wherein the upper fin portion of the second fin has a concentration of the P-type dopant of less than approximately 5E) 7 atoms/orrh,
22. 25. The integrated circuit structure of claim 12, wherein the lower fin portion of the second tin has a concentration of the P-type dopant of greater than approximately 2E18 atoms/cm3, and wherein the upper fin portion of the second fin has a concentration of the P-type dopant of less than approximately 5E17 atoms/cm3.