GB2433371A

GB2433371A - Parallel error diffusion processing for hologram image data

Info

Publication number: GB2433371A
Application number: GB0622777A
Authority: GB
Inventors: Edward Buckley
Original assignee: Light Blue Optics Ltd
Current assignee: Light Blue Optics Ltd
Priority date: 2006-11-15
Filing date: 2006-11-15
Publication date: 2007-06-20
Anticipated expiration: 2026-11-15
Also published as: WO2008059292A3; GB2434706B; GB2433371B; WO2008059292A2; GB0708790D0; GB2434706A; GB0622777D0

Abstract

The invention relates to data processing hardware for generating holograms, in particular for image display applications. We describe a hardware error diffusion calculation system for performing an error diffusion quantisation of a hologram. The system comprises address and data buses for a first, hologram memory block 610 storing data representing pixels of said hologram; for a second, error memory block 608 storing an error matrix representing errors in quantising said hologram; for a third, diffusion weights memory block 606 storing a set of diffusion weights for said error diffusion calculation; and a plurality of error diffusion processor blocks 602 a-h each coupled to said address and data buses, each being configured for sequential processing of a spatial region of said hologram. A said processor block includes a pixel address generator to generate a sequence of pixel addresses for a said spatial region for processing by the processor block and an error diffusion calculation block coupled to said pixel address generator and to said address and data buses to perform an error diffusion calculation for a pixel of said hologram identified by a said pixel address. Spatial regions processed by said processor blocks overlap and each of said processor blocks has a different start pixel address such that said processor blocks are able to perform error diffusion calculations with respective error diffusion calculation blocks on different pixels of the hologram in parallel. The error diffusion quantization process may be performed concurrently with hologram data generation by pipelining a first system generating hologram data and a second system quantizing the hologram data using error diffusion as per the invention.

Description

Data Processing Apparatus This invention relates to data processing

hardware for generating holograms, in particular for image display applications.

l'hcrc are a number of techniques which may be employed to generate data for creating a hologram from image data. Tn general, however, such techniques introduce noise into the hologram data, for example resulting from quantisation into binary phase (hr display on a spatial light modulator (SLM), or quantisation into a larger number of binary bits.

Some examples of techniques for generating hologram data from image data are described in the following: M.A. Seldowitz, J.P. Allebach, and D.W. Sweeney. synthesis of digital holograms by direct binary search, " Applied Optics, vol. 26, pp. 2788-. 1987; M.P. I)ames, R.J.

Dowling, P. McKee, and D. Wood "Efficient optical elements to generate intensity weighted spot arrays: design and fabrication," applied Optics, vol. 30, pp. 2688-2691, 1991; and J.R. Fienup, "Iterative method applied to image reconstruction arid to computer-generated holograms," Optical Engineering, vol. 19. pp. 297-305, 1979.

One particularly preferred procedure for calculating hologram data is die OSPR procedure which is described in more detail later.

One technique for noise reduction is called error diffusion (ED). Broadly speaking in such a technique a window is defined and the signal-to-noise (SNR) ratio within the window is improved at the expense of the SNR outside the window by, in eflèet.

moving errors from within the window to outside the window. The error diffusion technique is described in more detail later.

One problem with implementing the error diffusion technique in practice is that it is computationally vcry intensive. One technique to address this problem using software has been described by P.T. Metaxas in "Optimal parallel error-diffusion dithering," in Proceedings of' the 1999 E]eetronic Imaging. SPIlL 1999; and "Parallel digital halftoning by error-diffusion," in Proc. of' the FCRC 2003, Paris, 2003. However this is still computationally intensive and requires a main Frame computer system for its implementation. This effectively precludes the use of the error-diIi'usion technique in practical, real-li Fe applications.

Accordingly there is a need for improved approaches.

In a first aspect of' the invention there is therefore provided a hardware error dif'fusion calculation system for perlhrniing an error diffusion quantisation of a hologram, the system comprising: an address bus and a data bus For a tirst, hologram memory block, said hologram memory block for storing data representing pixels of said hologram; an address bus and a data bus for a second, error memory block, said error memory block for storing an error matrix representing errors in quantising said hologram; an address bus and a data bus for a third, diffusion weights memory block, said diffusion weights memory block for storing a set of diffusion weights fbi said error diffusion calculation: and a plurality of error diFfusion processor blocks each coupled to said address and data buses for each of said first, second and third memory blocks, each of said processor blocks being configured for sequential processing oI'a spatial region of said hologram, a said processor block including a pixel address generator to generate a sequence of pixel addresses for a said spatial region for processing by the processor block and an en'or diffusion calculation block coupled to said pixel address generator and to said address and data buses to perform an error diffusion calculation for a pixel of' said hologram identified by a said pixel address; wherein spatial regions processed by said processor blocks overlap, and wherein each ol' said processor blocks has a different start pixel address, such that said processor blocks are able to perform error diffusion calculations with respective said error diffusion calculation blocks on different pixels of'said hologram in parallel.

In embodiments the multiple error diffusion processor blocks are all in communication with global, shared memory storing the hologram data for error diffusion processing/binarisation, the error matrix, and the diffusion weights (kernel). These data may stored hi separately addressable parts of the same memory or in different memories arid, as the skilled person will understand, the address and data buses may be shared and/or combined. Preferably a single memory block stores loth the continuous hologram data and the quantised hologram data since the quantised hologram data may overwrite the continuous hologram data.

Iie pixel address generator enables the blocks of hologram data processed by each processor block to overlap but nonetheless determines a sequence for the calculations which, in embodiments, preserves the order of the error diffusion calculations so that valid data are available when required. More particularly the sequence of pixel addresses defines a generally diagonal path through a spatial region processed by a processor block. l'he start pixel or point for the different processor blocks is also staggered over the spatial region of the hologram, more particularly in embodiments along one dimension of the hologram.

Preferred embodiments of the system also include a scheduler to generate a control signal for each processor block to control each processor block to start processing in turn. This I hcilitates an ASIC (Application Specific Integrated Circuit) or FPGA (Field Programmable Gate Array) implementation in which the architecture may impose a memory access delay between one memory access and the next.

In preferred embodiments the processor block includes a controller to provide the start pixel address for a processor block. In this way the allocation of processing blocks to overlapping spatial regions of the hologram data is perthrmed locally by a processor block rather than by overall global control. l'he start pixel address may he determined by a hardwired or other non-volatile stored value, for example in embodiments where the hologram size is fixed. (In such embodiments t. he "controller" need only have the function of providing such a fixed address, although the scheduler will nonetheless start up each processor block in order). However in other embodiments the hardware is flexible and allows for a range of different hologram sizes, in which case the controller may determine a start pixel address for a processor block dependent upon a value dependent upon the size of the hologram, iii particular in one dimension (u or v). The start pixel addresses are preferably staggered along the other dimension of the hologram (v or u). In embodiments each processor block has a processor block identifier and the controller is configured to determine a start pixel address using this identifier to stagger the start pixel addresses in this way.

In pref cited embodiments the error diffusion calculation block comprises a multiply accumulate block coupled to the data buses for the error matrix and difihision weights memory blocks, the multiply accumulate block having an output which is Ltsed lhr determining a quantised hologram pixel value, in particular by thresholding the multiply-accumulate block output, for example about zero. Prelérably the error diffusion calculation block also includes a subtraetor to subtract the thresholded data from the (continuous) hologram data to provide updated error data for writing to the error memory block. This suhtractor may either use the continuous hologram data in the hologram memory block or may employ data derived from an output of the multiply-accumulate block, that is changed hologram data, this having been modified by the diffused errors. In this way either "standard" ED or MAE may be implemented.

Optionally the error diffusion calculation block may he configurable to perform either type of error di ilUsion calculation by selecting the input to the subtraetor in response to a value stored in a register associated with the error diffusion processor block.

As previously implied, preferably the quantisation comprises binarisation; the error diffusion system may he employed with amplitude and/or phase data.

In preferred embodiments an error diffusion processor block includes a memory controller coupled to the pixel address generator to provide addresses for the error memory and diffusion weights memory blocks to address an error difilision window over which the error diffusion calculation is performed. Thus the memory controller generates a sequence of addresses [r, sl to cover the error di (fusion window and, in preferred embodiments, also translates [ii, v] to memory addresses 11w the hologram memoiy block. Optionally but preferably the memory controller may also perlhrm validity checking on the generated addresses to ensure that only valid pixel addresses

S

are generated, that is pixel addresses that are within the spatial region defined by the hologram data.

Preferably the hardware error diffusion calculation system is embodied in either an FPGA or an ASIC. Such an implementation may optionally include memory for the hologram and/or error and/or diffusion weights memory blocks.

The invention also provides a holographic image display system including a hardware error diffbsion calculation system as described above, in particular employing an OSPR-type holographic subframe calculation procedure. Where a hardware OSPR engine is employed, preferably the OSPR engine and the error di I fusion calculation system are pipelined so that an error difThsion calculation for one sub frame is performed concurrently with a holographic suhfrarne calculation for the next subframe. However.

this pipelined approach may also he employed in non-OSPR based systems.

Thus in a further aspect the invention provides a holographic image display processing system, the system being configured to provide data to display an image holographically, said image being defined by displayed image data, the system comprising: a first system to generate hologram data from said image data.; a second system to quantise said hologram data for display; and wherein said first aiid second systems are pipelined such that said hologram duta quantisation is performed concurrently with said hologram data generation.

In preferred embodiments the processing system is configured to provide data to disp]ay the iniage using a plurality of holographically generated temporal subframcs, the temporal suhframes being displayed sequentially in time such that they are perceived as a single noise-reduced image, the first system being configured to generate holographic suhframe data, and the first and second systems being pipelined such that the quantisation of this data for one subframc is perlonned substantially concurrently with the generation of holographic subframe data for a subsequent suhirame, in particular the next subfrarnc. 11w invention also provides a holographic image display system incorporating such a processing system.

Thus, broadly speaking in embodiments a first hardware hologram data generation system is coupled to a hardware error diffusion calculation system, in particular as described above, these two systems being pipelined to enable a hologram to be generated and an error diffusion calculation to be performed, in particular with one (sub) frame latency. In some preferred embodiments to econornise on memory the two systems, tl1at is the hologram calculation system and the hardware error diffusion calculation system share common memory for storing the hologram data.

These and other aspects of the invention will now he further described, by way of example only, with reference to the accompanying figures in which: Figure 1 shows an outline block diagram of an embodiment of a hologram calculation hardware accelerator for a holographic image display system; Figure 2 shows an example holographic projection system: Figure 3 shows a block diagram of a system in which an image frame is used to produce one or more holographic sub-frames; Figure 4 shows example energy disfrihutions for an image before and after phase-modulation; Figure 5 shows the variation of replay field noise energy and SNR as a function of error diffusion kernel size; Figure 6a to 6c show a hardware error ditTüsion calculation system according to an embodiment of an aspect of the invention; Figures 7a and 7b show, respectively, a schematic illustration of calculations performed by the system of Figure 6, and time scheduling oF error diffusion processing cores for the hardware ol' Figare 6; Figure 8 shows a graph of processable OSPR subframes against kernel size for a range of numbers of processor cores br the hardware of Figure 6; Figures 9a and 9h show a holographically generated iniage respectively without and with error diffusion processing; and Figures 1 Ga and lOb show, respectively, apipelined hologram data generation system with en-or dililision according to an ciii bodinient of an aspect of the invention, and a timing diagram for the pipeline.

To assist in understanding embodiments of' the invention, and to provide context, we first describe one technique, OSPR, for calculating hologram data with which embodiments ol the invention may be employed (although the skilled person will understand that applications of embodiments of the invention are not limited to hologram data calculated using the OSPR technique).

OSPR

Our preferred procedure for calculating hologram data, for example for display on an SIAM, is what we refer to in broad terms as One Step Phase Retrieval (OSPR). However strictly speaking iii sonic implementations it could be considered that more than one step is employed (as described for exaniple hi G1105 18912.1 and 080601481.5, incorporated by reference, where "noise" in one sub-frame is compensated in a subsequent sub-fi-ame), Thus we have previously described, in WO2005/059660, a method ob displaying a holographically generated video image conipri sing plural video frames, the method comprising providing Ihr each frame period a respective sequential plurality of holograms and displaying the holograms of the plural video frames I br viewing the replay field thereof, whereby the noise variance of each frame is perceived as attenuated by averaging across the plurality of holograms.

Broadly speaking in our preferred method the SLM is modulated with holographic data approximating a hologram of the image to he displayed. However this holographic data is chosen in a special way, the displayed image being made up of a plurality of temporal sub-frames, each generated by modulating the SLM with a respective sub-frame hologram. These sub-frames are displayed successively arid sufficiently fast that in the eye of a (human) observer the sub-frames (each of which have the spatial extent of the displayed image) arc integrated together to create the desired image fin display.

Each of the sub-frame holograms may itself be relatively noisy, for example as a result of quantising the holographic data into two (binary) or more phases, but temporal averaging amongst the sub-frames reduces the perceived level of noise. Embodiments of such a system can provide visually high quality displays even though each sub-frame, were it to he viewed separately, would appear relatively noisy.

A scheme such as this has the advantage of reduced computational requirements compared with schemes which attempt to accurately reproduce a displayed image using a single hologram, and also facilitate the use of a relatively inexpensive SLM. (Here it will be understood that an SLM will, in general, provide phase rather than amplitude modulation, for example a binary device providing relative phase shills of zero and it, +1 and -1 fhr a normaliscd amplitude of wiity).

We have also described, in PCT/GB2006/050 152 (incorporated by reference), a hardware accelerator for a holographic image display system, the image display system being configured to generate a displayed image using a plurality of holographically generated temporal sub-frames, said temporal sub-frames being displayed sequentially in time such that they arc perceived as a single reduced-noise image, each said sub-frame being generated holographically by modulation of a spatial light modulator with holographic data such that replay of a hologram defined by said holographic data defines a said sub-frame, the hardware accelerator comprising: an input buffer to store image data defining said displayed image; an output buffer to store holographic data for a said sub-frame; at least one hardware data processing module coupled to said input data buffer and to said output data buffer to process said image data to generate said holographic data for a said sub-frame: and a controller coupled to said at least one hardware data processing module to control said at least one data processing module to provide holographic data for a plurality of said sub-frames corresponding to image data br a single said displayed image to said output data buffer.

in this preferably a plurality of the hardware data processing modules is included for processing data for a plurality ol the sub-frames in parallel. In preferred embodiments the hardware data processing module comprises a phase modulator coupled to the input data huller and having a phase modulation data input to modulate phases of pixels of the image in response to an input which preferably comprises at least partially random phase data. ibis data may be generated on the fly or provided from a non-volatile data store. The phase modulator preferably includes at least one multiplier to multiply pixel data from the input data buffer by input phase modulation data. In a simple embodiment the multiplier simply changes a sign of the input data.

An output of the phase modulator is provided to a space-frequency transfbni-iation module such as a Fourier transform or inverse Fourier transform module. In the context of the holographic sub-frame generation procedure described later these two operations are substantially equivalent, effectively differing only by a scale factor. in other embodiments other space-frequency transformations may be employed (generally lIequeney referring to spatial frequency data derived from spatial position or pixel image data). In some preferred embodiments the space-frequency transformation module comprises a one-dimensional Fourier transformation module with feedback to perform a two-dimensional Fourier transfbrm of the (spatial distribution of the) phase modulated image data to output holographic sub-frame data. This simplifies the hardware and enables processing of, for example, first rows then columns (or vice versa).

In preferred embodiments the hardware also includes a quantiser coupled to the output of the transformation module to quantise the holographic sub-frame data to provide holographic data for a sub-frame thr the output buffer. The quantiser may quantise into two, four or more (phase) lcvels. In preferred embodiments the quantiser is configured to quantise real and imaginary components of the holographic sub-frame data to generate a pair of sub-frames for the output buffer. thus in general the output of the space-frequency transformation module comprises a plurality of data points over the complex plane and this may he thresholded (quantiseci) at a point on the real axis (say zero) to split the complex plane into two halves and hence generate a first set of binary quantised data. and then quantised at a point on the imaginary axis, say 0/, to divide the complex plane into a further two regions (complex component greater than 0, complex component less than 0). Since the greater the number of sub-frames the less the overall noise this provides further benefits.

Preferably one or both of the input and output buffers conipnse dual-ported memory. In some particularly preferred embodiments the holographic iniage display system comprises a video image display system and the displayed image comprises a video frame.

Figure I, which is modified from PCT/GB2006/050 152, shows a block diagram of an embodiment of such a hardware accelerator. Each buffer preferably comprises dual-port memory such that data is written into the buffer and read out from the buffer simultaneously. The hardware block performs a series of operations on each of the image frames, I, and for each one produces one or more holographic subframes, Ii, under control of the controller unit.

The holographic subfrarne data is sent to the output huller and may be supplied to a display device, such as a SIAM, optionally via a driver chip. However in embodiments of the system we describe the holographic subframe data provides an input to error dil'lhsion calculation hardware, described later. (The skilled person will understand, however, that the error diffusion calculation hardware we describe may also receive input data from a hologram calculation system comprising a combination of software and hardware, or just software it also need not receive hologram data from an OSPR.-based hol ogmni calculation system).

Such subframes are outputted from the aforementioned output buffer and. The control signals by which this process is controlled are supplied from one or more. The control signals preferably ensure that one or more holographic suhirames are produced and sent to the SLM per video frame period. In an embodiment, the control signals transmitted from the controller to both the input and output buffers arc read / write select signals, whilst the signals between the controller and the hardware block eompdse various timing, initialisation and flow-control iii lorrn ati on.

The hardware (and/or software) may implement a version or variant ol' the algorithm given below. The algorithm is a method of generating, for each still or video frame I Jo,, sets of N binary-phase holograms he... h. Statistical analysis of the algorithm has shown that such sets of holograms [birni replay fields that exhibit mutually independent additive noise.

1. Let (*2 J.exp where is uniformly distiibuted between 0 and 2K for 1 Cu = N/2 and I <x. y < rn 2. Let = F"1 [c?] where F" represents the two-dimensional inverse Fourier transform operator, for I <n N/2 3. Let = 9tc:} for 1 =n = N/2 4. Let,:4Nf2) = for I Sn S N/2 5. Let = - where Q(fl = median (4?) 1 if mSe Q(fl) andi =n =N Step 1 fonns N targets (1 equal to the amplitude of the supplied intensity target A, hut with independent identically-distributed (i.i.t.), uniformly- random phase. Step 2 computes the N corresponding Full complex Fourier transform holograms g,'. Steps 3 and 4 compute the real part and imaginary part of the holograms, respectively.

Binarisation of each of the real and imaginary parts oF the holograms is then performed in step 5: thresholding around the median of n4, ensures equal numbers of -I and 1 points are present in the holograms, achieving DC balance (by definition) and also minimal reconstruction error. l'he quantisation may he pei'Ibrmed in a number of ways in an embodiment, the median value of' in? is assumed to be zero. 1'his assumption can be shown to he valid and the eliècts of' making this assumption are minimal with regard to perceived image quality. Further details can be found in the applicant's earlier application (ibid), to which reference may be made.

Figure 2 shows an example holographic projection systeni. further details of which may be found in PCl'/GB2006/050l 58 to which reference may he made. A laser diode 20 (for example, at 532nm), provides substantially collimated light 22 to a spatial light modulator 24 such as a pixellated liquid crystal modulator. the SlIM 24 phase modulates light 22 with a hologram and the phase modulated light is provided to a dcmagnifying optical system 26 which projects a 21) (in this example) image onto screen 14. In the illustrated embodiment, optical system 26 comprises a pair of lenses 28, 30 with respective focal lengths l's, 1, 11cf2, spaced apart at distance fi f2. Optical system 26 (which is not essential) increases the size of the projected holographic image by diverging the light forming the displayed image. as shown. One or more ol the lenses may be encoded in the hologram, as described in IJK patent application GB 0606123.8 filed on 28 March 2006. A filter may be included to filter out unwanted parts of the displayed image, for example a zero order undiffraeted spot. In a illeasurement device, the demagnilying optics may be omitted; alternatively lens 30 (L4) and screen 14 may be replaced by, say, a digital camera.

A hologram calculation system 100 has an input 102 to receive image data from the consumer electronic device defining the image to he displayed. l'he hologram calculation system 100 implements a procedure, for example along the lines described above, to generate phase hologram data, in an OSPR-based display device data for a plurality of holographic sub-frames. Ibis data is provided from an output 104 of' the hologram calculation system 100 to the SLM 24, optionally via a driver integrated circuit if needed. the hologram calculation system 100 drives SLM 24 to project a plurality of phase hologram suh-f'rarnes which combine to give the impression of displayed image 14 in the replay field (RPF). The hologram calculation system 1 00 may comprise dedicated hardware or Flash or other read-only memory storing processor control code to implement an OSPR-type hologram generation procedure in conjunction with a DSP (digital signal processor), or a combination of hardware and software.

In embodiments of the above-described system the SLM may comprise a ferroelectric liquid crystal-based SLM. However in general any type of pixellated microdisplay which is able to phase modulate light may be employed for the SlIM, optionally in association with an appropriate driver chip if needed. Preferred embodiments usc an electrically addressable SlIM. Suitable SLMs include, hut are not limited to, liquid crystal SLMs including I1COS (liquid crystal oil silicon) and DLP (registered TM) (digital light processing) SLMs. A suitable SLM is available from CRL Opto (Forth I)imcnsion Displays Ltd of Scotland, IlK), with part number SXGA-R2-H1 (pixel pitch A1=A1 =l3.62m) Figure 3 shows a block diagram of a system in which an image frame, lu,,, is used to produce one or more holographic sub-frames by means of a set of operations comprising one or more of: a phase modulation stage, a space-frequency transformation stage and a quantisation stage. The purpose of the phase-modulation block is to redistribute the energy of the input frame in the spatial-frequency domain, such that improvements in filial image quality are obtained after performing later operations. The phase-modulation data may comprise a pseudo-random sequence.

The quantisation block of Figure 3 has the purpose of taking complex hologram data.

which is produced as the output of' the preceding space-frequency transform block, and mapping it to a restricted set of values, which correspond to actual phase modulation levels that can be achieved on a target SLM. The number of quantisation levels may be set at two, for example for an SLM producing phase rctardations of 0 or it at each pixel.

Figure 3 shows use of the real part of' the holographic sub-frame data but alternatively real and imaginary components of the holographic sub-frame data may be quantised to generate a pair of sub-frames, each with two phase-retardation levels (for discretely

pi xeJ lated fields these arc uncorrel ated).

Figure 4 shows an example of how the energy of a sample image is distributed before and after a phase-modulation stage in which a random phase distribution is used. It can he seen that modulating an image by such a phase distribution has the effect of redistributing the energy more evenly throughout the spatial-frequency domain. Tt is next helpful in understanding embodiments of the invention to

describe error diffusion.

Error Diffusion Error difihsion techniques applied to the binarisation of continLious hologram patterns have been described in the following background material: M.P. Cliang and O.K.

Ersoy, "Iterative interlacing en-or diffusion for synthesis of computer-generated holograms," Applied Optics, vol. 32. pp. 3122-. 1993: R. Eschbach, "Comparison of en-or dilThsion methods for computergenerated holograms," Applied Optics, vol. 30, pp. 4361-, 1991; R. Eschbach and Z. Fan, "Complex-valued error diIiksion for off-axis computer generated holograms," Applied Optics, vol. 32, pp. 3 130-1993; A. A. Falou, M. Elbouz, and H. Hamam, "Segmented phase-only filter binarised with a new error diffusion approach," Journal of Optics A: Pure and Applied Optics, vo]. 7, 2005; 0. B. Frank Fctthauer, "On the error diffusion algorithm: object dependence of the quantization noise." Optics Communications, vol. 120, 1995; F. Fetthauer and 0.

Biyngdahl, "Use of error ditTusion with space-variant optimized weights to obtain high-quality quantized images and holograms," Optics Letters, vol. 23, pp. 739-741, 1998; L. Ge, M. l)uelli, and R. W. Cohn, "Improved-fidelity error ditTusion through blending with. pseudorandom encoding," J. Opt. Soc. Am. A, vol. 17, pp. 1606-1616, 2000.

An error diffusion procedure covering two variants of the procedure, ED and MAE, is given below. l'he example procedure relates to a PxJ' pixel hologram (although there is no need for u and v both to have ranges [1;P]) with pixel dimensions [ii, vJ within which a window with pixel dimensions fr,sJ is dctined.

1. Let em, = 0 Vu,v [1;P] 2. Let = mm, + I d3e11....yv_ U v [1; fl r,s rs[1;K] ( in, -Ji, MAE algorithm 3. Let em = m, -ED algorithm (_ fC <Q 4. Let em' = liv where Q = median (rn',) I ifrn17 = Q In this procedure rn4, represents continuous hologmrn data (real and/or imaginary component), diffused errors. drs diffusion weights, and h711 a binary phase representation of the hologram. In the techniques we describe later rn,.,, may comprise a real or imaginary component of hologram data from an OSPR procedure. Conveniently Q is a median pixel value but may also be a constant, lhr example zero.

To obtain local SNR improvement in a window Wdefined in the RPF (replay field) RPF noise is optiinised in the region Wby diffusing hologram pixels according to a diffusion kernel of size K where d, is the appropriately bandlimited Fourier transform of the window (Unction W. More particularly the difftision kernel is calculated by calculating the Fourier translbrm (in 2 or more dimensions) of the window function, and (lien truncating the potentially inlinite Fourier series, for example taking a set of' components around zero-spatial frequency. ftc window function may conveniently comprise a function defined over the area of the replay field, with a value of "1" over the window and a value of "0" elsewhere.

In step 2 e11 comprises a matrix which represents errors introduced by the quantisation (binarisation) process, more particularly the error in hinarising one or more previous pixels [u,vJ. The diffusion kernel d,represents a weighting of these errors over a window oldimension [r,s. preferably centred on the currently processed pixel [ui'].

As shown, the error matrix Cm, may initially he set to zero and will gradually accumulate CITOF data as more pixels are processed. An error fbr a currently processed pixel is calculated at step 3. l'here are two main ways in which this error may be determined, although applications of embodiments of the invention arc not limited to these. A Minimum Average Error (MAE) calculation may be employed to determine the difference between a hhiarised pixel value h,,, and a real (and/or imaginary) part of the complex hologram data; or in a standard error diffusion (ED) procedure the diliërence may he between the binarised pixel value and a changed (c) value determined in error diffusion step 2. These two approaches merely differ in the quantisation of the diffused errors e,1 and can he made to behave equivalently by appropriate choice of the diffusion weights d,.. Thus either an ED or an MAE procedure can be implemented by changing the kernel (i.e. the data stored in the diffusion kernel memory) and embodiments of the invention we describe are able to implement both ED and MAE (hut not limited to these).

An example of an error diffusion technique with iterative weight calculation is described in: A. Kirk, K. Powell, and 1. Hall, "A generalisation of' the error diffusion method for binary computer generated hologram design," Optics Communications, vol. 92, 1992.

The binarisation step 4 of the procedure may then performed: thresholding around the median provides substantially equal numbers of -I and I points in the hologram, giving DC balance and also low reconstruction error. ifowever the median value may be assumed to he zero with minimal impact on perceived image quality.

Broadly speaking the error diffusion step 2 diffuses errors over a window of size [r,s] detennining a changed or adjusted value for the real and/or imaginary component of the complex hologram data taking into account these diffijsed errors, that is taking into account the binarisation which is employed (at a later step) for displaying the hologram on an. [he error broadly speaking comprises a difference between a quantised (binarised) pixel and the unquantised, continuous value of the pixel.

The region over which the error difftision is applied depends upon the size of the window, a larger window using a larger diffusion kernel. Broadly speaking the size of the difftision kernel determines the cquality of the difthsion process but a larger kernel, even with hardware, requires greater conipittatioii. Similarly a greater improvement in signal-to-noise ratio (SNR) can be achieved by using a larger diffusion kernel (or a less truncated Fourier series): The window becomes increasingly well-detined, the SNR increases and the signal and noise histograms become increasingly better separated.

Thus there is a trade off between the window size, desired SNR improvement, and the number of hardware error diffusion processors (as described below). In theory the size of the window can approach the size of the replay field but it then becomes harder to remove noise from the window; in practice a smaller window can nonetheless provide useful benefits because the points in the (replay field) window are still effectively at higher resolution, albeit the image area is reduced.

Figure 5 shows the variation of RPF noise energy and SNR as a ifinction of kernel size, showing that the noise energy falls rapidly as K increases, leading to a similarly rapid SNR rise. The figure can be used to detennine a point at which increased computation outweighs the benefit of increased SNR; here at approximately K 15. Therefore this was set as the maximum kernel size for the hardware implementation described below.

Hardware error diffusion calculation system We will describe an error dilii.tsion processor which is designed to act as a co-processor to augment an OSPR computation engine. Tiowever, assuming that the ED and OSPR processors are used in tandem such that one OSPR suh&ame is calculated and the ED binarisation procedure is perfbrmed immediately afterwards, then in order to remove the need for buffering many hologram subframes the liD binarisation of the first suhframe should preferably take place in parallel with the OSPR calculation of the second suhframe. This implies that the ED co-processor should preferably take no longer to complete its operation than the lime it takes to calculate one OSPR suhframe. At, for example. a 60hz video frame rate a system employing eight OSPR subfrarnes per video frame would preferably need to calculate cach suhframe within 2 ms.

Referring to thc error diffusion procedure described above, each pixel of a P x P hologram should be traversed and K x K multiplications and additions perlhniied at each pixel. We will describe an 1'PGA-hascd design which employed a Xilinx Virtex- 4 SX 35 FPGA ([hr which the design was written in Verilog using Xili&ISE tool).

The 1'PGA logic was eon ligured to replicate multiple cores, each of which was capable of simultaneously calculating part of the error diffusion procedure. l'he resulting parallelisation resulted in an approximate N-lhld speed increase, where IV is the number of replicated cores.

Referring to Figure 6a, this shows an embodiment of a hardware error diffusion calculation system 600 according to an aspect of the invention. The system 600 comprises a plurality of error diffusion processor blocks or cores 602a -h, each of which is coupled to a scheduler 604. The system also includes an error diffusion weight (d) memory 606, an error (e) memory 608, and a hologram data (m) memory 610 for storing values drs, c,,1', and respectively as described in the El) procedure and preferably also Each of these memories has an associated data bus and an associated address bus coupled to each of the processor blocks 602 (these connections have been omitted in Figure 6a, Ihr clarity). The memories 606, 608 and 610 may either he internal or external to the lPGA.

Preferably the hologram data memory 610 is dual ported to allow continuous hologram data to he written to this memory and quantised (binarised) hologram data to he read from this memory for output to a display: the input and output lines are not explicitly shown in Figure 6a.

In operation the scheduler 604 provides a value, k, to each of the processor blocks, each of which also has an associated processor block identifier (PROC lID). The timing of the sending of the value of k by the scheduler to a processor block controls the timing of the initiation of the processor block in pertorming its calculations. This timing is shown in Figure 7h, where it can be seen that each processor block is started in succession with a small delay, for example a few memory access cycles, iii between each. (The delay is implementation-memory specific and is chosen to he sufficient to allow stored data to become valid after a memory write).

Referring now to Figure 6b, this shows details of' a processor block or core 602 of Figure 6a. The processor block 602 comprises a controller 612 with a control bus 614 coupled to scheduler 604 of' Figure 6a. to receive a value of It from the scheduler. As described in more detail below, the value of' k depend.s upon the size of the hologram to be processed and determines how the error dililision calculation is allocated amongst the available processor blocks. The controller waits for the value of k to be sent by the scheduler and then provides an RDY (ready) output 614a to a process_pixel block 616, described below, the RDY signal initiating the process_pixel core. l'he controller also provides values of ii and v to a valid pixel block 61 8 which determines whether or not these values of ii and v are valid, if so providing the values on respective buses 620a, b to the process_pixel block 616, in effect to provide x-y addressing of a hologram pixel to be processed. 11w valid_pixel block 61 8 comprises logic to ensure that the indices u, v represent a valid memory location and hence that the boundary conditions of the ED process are met -in other words it determines whether or not the values u and v lie outside the boundary of' the hologram.

The controller 612 provides it and v pixel address data which is controlled to select pixels oI'the hologram data to be processed along a generally diagonal line (in the [a, v] space of the hologram). The general direction of the calculation is shown in Figure 7a; in more detail the pixels are chosen according to a sawtooth pattern along the diagonal as indicated by the open circles in Figure 7a. l'his is described in more detail below.

The u and v values depend upon the value of k from the scheduler (which depends upon the hologram size) and the processor block identifier "and whether values are provided depends upon whether or not the processor block has been "awakened".

ftc process_pixel block 616 has data and address bus connections 622a. h, 624a, h and 626a, b for the d, e and in memories, 606, 608 and 610 respectively. Details of the process_pixel block 616 are shown in Figure 6c Referring to Figure 6c, the v and ii value buses 620a. h provide an input to a memory controller 630 which provides address outputs 622b, 624h, and 626b for the difftision weights, error, and hologram memories 606. 608, 610 respectively. More particularly the memory controller provides addresses which sequence over the dilILision kernel, in effect the indices r, s of step 2 of the example PD procedure described above. The diffusion weights data is received on data bus 622a and the error data is received on data bus 624a, both of these data buses providing an input to a multiply-accumulate block 632 which performs the summation over r and s in step 2 of the above-described procedure. A sumner 634 is coupled to the output of multiply-accumulate block 632 and to an input data bus 626aa from the hologram data memory to fomi the changed hologram data value ni oF step 2 of the procedure. Ibis value is provided to a thresholder 636 to threshold about 0, a constant value or, for example, a median value of the hologram data which may be determined in advance, say by the hologram data calculation system. This thresholder performs step 4 of the above-described procedure to binarisc the hologram data, providing an output /i to output hologram data memory bus 626ab to be written back into the hologram data memory.

A subtraetor is also provided which, in the illustrated embodiment, has a first input from the output of the thresholder 636 (h) and a second input from the hologram data memory bus 626aa (in), providing an error value output (C?) to error memory data bus 624a. This implements the MAE procedure described above (see step 3). Alternatively the second input to subtractor 638 may be taken from the output of the summer 634, that is rn', to implement a standard ED procedure. In a ftirther alternative the second input to subtractor 638 may user selectable or programmable, for example by means of a register (not shown) to enable user selection of programming of MAE or standard ED, optionally whilst running.

1'hus, broadly speaking, the process pixel block 616 operates over a region of the hologram, receiving continuous hologram data on input bus 626aa and outputting hinarised hologram data on output bus 626ah (at the same location), also providing error data on bLis 624a to update the error memory 608.

The skilled person will understand that where reference is made to continuous" hologram data this is continuous to a degree permitted by tile width of the hologram data bus, and is thcreaficr quantised thus reducing the number of bits which are needed to describe this data, iii general, binarised so that the data thr a single pixel of the hologram may be represented by a single hit. The skilled person will also undcrstand that in the arrangement olFigure 6c clock and reset lines will normally be present but in the Figure thesc have been omitted for clarity.

Referring again to Figure 6a and óh, the operation of the scheduler 604 and controller 612 will now be described in more detail, in particular with reference to the pseudo-code shown below.

k = ceil((P-1)/3); for (proclD = k: k-f-Nc) % Everything below represents the operation X of one processor with identity procID 0/ alpha = proclD -k; u = 2; it = 3*alpha + 1; for (t = 1: 2*P+P) if valid_pixel(u, it) process_pixel(u, v++); if valid_pixel(u, v) process_pixel(u, v-s-i-); if valid_pixel(u, it) process_pixel(u±i-, v--); end end The first line of this pseudo code illustrates the operation oithe scheduler 604. The hologram has dimensions F x Q and a value for k is calculated based upon the value oF P. l'hc processor blocks are then initiated in turn using the calculated value of Ic, with a short delay between the initiation of each processor block. Note that one processor block does not have to complete its calculations before the next processor block is initiated. In the pseudo-code, as previously mentioned Nc represents the total number ol' processor blocks.

l'hc rest of the pseudo-code describes the operation of the controller 612 of Figure 6b.

More particularly the controller deteniiines a block or spatial region of the hologram data on which to work by choosing initial value for u and v based upon the processor block identilier and the value of k received from the scheduler. Jt will be seen that in this example pseudo-code a processor block always begins at ii 2 hut that each processor block has a different starting vaJue of v so that the processor blocks are allocated to successive, overlapping regions ol' the hologram data. In the example pseudo-code the value of k is determined by dividing by the P axis into three and a processor block is allocated to start at every third value of v in the Q direction. l'lw controller also, in this example, delines a group of three hologram pixels to be processed (u, v++; u+ +; v--) in a group, the incremental effect of processing these groups olpixels being to carry the calculation in a generally diagonal direction. This is shown schematically in Figure 7a and the skilled person will appreciate that variants on the above-described pseudo-code are possible which also have the effect of' generally diagonal processing.

Ilic scheduler 604 ol' Figure 6a and the controller 612 of Figure 6h are, in embodiments, configured according to the above- described pseudo-code, for example using a hardware design language such as Verilog . The valid_pixel function has previously been described; in embodiments it is configured to determine whether a value of [ii, vj is valid, and should therefbre be processed, by determining whether or not the value is within the boundary of the hologram.

As previously mentioned, preferably the hardware is implemented on an FPGA or ASiC. The skilled person will recognise that although it is often convenient to implement a system which employs the scheduler to determine a value fin k, in a system where the hologram size is fixed (in at least one dimension) a calculation of k is unnecessary. Similarly the starting values of u and v for a particular processor Mock could he hardwired, dispensing with this aspect of the function of thc controller.

As mentioned above, iii preferred applications of the hardware ED calculation system, the system is uscd as a co-processor for an OSPR engine, and it is therefore useful to consider the potential inaxiinuni speed of operation of embodiments of tile hardwarc, since this relates to (potentially limits) the maximum number of OSPR suhframes that may be calculated. The speed of the El) processor is a fhnction of the operation speed (of the FPGA), kernel size and number of replicated cores. Four designs were evaluated using N 4, 16, 64, and 128. using the aforementioned FPGA the maximum clock frequency [hr each of these was determined by [lie Xilinx" tools to be approximately 128MHz, and this was used to determine the execution time as a function of kernel size.

which it was postulated dictates the maximum number of OSPR suhframes that is able to processed by embodiments of the hardware ED system.

Figure 8 shows the results of this procedure, plotting the maximum number of OSPR subframes against the kernel size for different numbers of replicated processor cores, from which it can be seen that with a kernel size of K -15 providing 64 or 128 processor cores enables the computation of 8 or 1 6 OSPR subframes respectively. Each processor core is implemented on the FPGA in a DSP 48 block, and the available number of these DSP 48 blocks in the example Xilinx FPGA ultimately determine the maximum speed/OSPR subframes.

Three different 128-processor designs were implemented, each having a different kernel size, and these were tested by binarising a 512 x 512 pixel continuous hologram resulting from an OSPR algorithm. The results were as follows: FPGA Execution Time (128 cores, 128MH'i) in ms 1 0.004 -______________ 7 0.1 _____ 0.9 ______ It can be seen that with K -15 an execution time of less than 2ms is readily achieved.

The resulting binary holograms corresponding to OPSR (K' I) and ED (K -15) were displayed on an SLM and imaged onto a projection surface using a demagnification lens assembly, as illustrated in Figure 2.

Figure 9a illustrates the K= I replay field, and Figure 9b the K= 15 replay fiel& these were determined to have measured contrast ratios of 25:1 and I 00:1 respectively, showing an SNR increase by approximately a factor of 4.

Referring now to Figure ba, this shows an example of a pipelined holographic data calculation and error diFfusion system 1000 comprising a hologram data calculation system 1002, for example similar for that described above with reference to Figure 1, closely coupled to a hardware error di illision calculation system 1004, also as described above, both under control of a pipeline controller 1006.

The hologram data calculation system 1002 receives image data into an input buffer 1 002a from which the data is provided to a hologram data calculation module I 002b which outputs the calculated hologram data to a hologram data memory I 002c.

Preferably the hologram data memory 1002e is shared with the error diffusion calculation system 1 004 as schematically shown in Figure lOu.

The error diffusion calculation system 1004 comprises a set of error diffusion processors 602 coupled to error diffusion kernel memory 606, diffused error memory 608. and under control oft scheduler 604, as well as being a coupled to the hologram data memory 1002c (which corresponds to memory 610 described above). Hologram data may he read out from the hologram data memory l 002c and provided, for example, to an SLM as illustrated in Figure 2.

The operation of the system of Figure lOa is illustrated in Figure lOb in which the successive integers refer to successive OSPR suhlianies. As can be seen once the pipeline has started (under control of pipeline controller 1006) one subframe is output for each pipeline state, with a latency of one subframc. More particularly the error ditiüsion engine 1004 performs an en-or diffusion calculation one OSPR sublrame whilst the OSPR engine 1002 calculates continuous hologram data for a subsequent subframe.

l'he skilled person will understand that the above described techniques may he employed with either monochrome or colour holographic image display systems, iii the latter case applying the technique to each colour plane or the input/holographic image.

Applications br the above described system include, but are not limited to, the following: mobile phone; PDA: laptop; digital camera; digital video camera; games console; in-car cinema; personal navigation systems (in-car or wristwatch UPS); head-up/helmet-mounted displays for automobiles or aviation; watch; personal media player (e.g. MP3 player, personal video player); dashboard mounted display: laser light show box; personal video projector (a "video iPod (RTM)"); advertising and signage systems; computer (including desktop); and a remote control unit.

We have described embodiments of the invention in the particular context of holographic image display systems. However the skilled person will understand that embodiments of the invention are not limited in this way and have application to hologram data used for other purposes, for example in optical metrology systems and opLieal sensors as described in our co-pending UK patent application GBO6 12882.1 filed 29 June 2006.

No doubt many other effective alternatives will occur to the skilled person. It will be understood that the invention is not limited to the described embodiments and encompasses modifications apparent to those skilled in the art lying within the spirit and scope of the claims appended hereto.

Claims

CLAIMS: 1. A hardware error diffusion calculation system for performing

an error diffusion quantisation of a hologram, the system comprising: an address bus and a data bus for a first, hologram memory block, said hologram memory block for storing data representing pixels of said hologram; an address bus and a data bus for a second, error memory block, said error memory block for storing an error matrix representing errors in quantising said hologram; an address bus and a data bus for a third, diffusion weights memory block, said diffusion weights memory block for storing a set of diffusion weights for said error diffusion calculation; and a plurality of error diffusion processor blocks each coupled to said address and data buses for each of said first, second and third memory blocks, each of said processor blocks being configured for sequential processing of a spatial region of said hologram, a said processor block including a pixel address generator to generate a sequence of pixel addresses for a said spatial region fur processing by the processor block and an error diffusion calculation block coupled to said pixel address generator and to said address and data buses to perform an error diffusion calculation for a pixel of said hologram identified by a said pixel address; wherein spatial regions processed by said processor blocks overlap, and wherein each of said processor blocks has a different start pixel address, such that said processor blocks are able to perform error diffusion calculations with respective said error diffusion calculation blocks on different pixels of said hologram in parallel.

2. A hardware error diffusion calculation system as claimed in claim 1 further comprising a scheduler to generate a control signal for each processor block to control each said processor block to start processing in turn.

3. A hardware error diffusion calculation system as claimed in claim 1 or 2 wherein a said processor block further comprises a controller to provide said start pixel address.

4. A hardware error diffusion calculation system as claimed in claim 3 when dependent on claim 2 wherein said scheduler is configured to generate a value (k) dependent on a size of said hologram in pixels in one dimension (P;u), and wherein said controller is configured to determine said start pixel address from said value (k).

5. A hardware error diffusion calculation system as claimed in claim 4 wherein each said processor block has a processor block identifier, and wherein a said controller is configured to determine said start pixel addresses using said processor block identifier such that said spatial regions are distributed along a direction (v) orthogonal to a direction of said first dimension.

6. A hardware error diffusion calculation system as claimed in any preceding claim wherein said sequence of pixel addresses defines a generally diagonal path through a said spatial region processed by a said processor block.

7. A hardware error diffusion calculation system as claimed in any preceding claim wherein a said error diffusion calculation performed by a said error diffusion calculation block is performed over an error diffusion window, and wherein a said error diffusion calculation block comprises a memory controller coupled to said pixel address generator and to said address buses for at least said second to third memory blocks to provide a set of addresses for said second and third memory blocks to cover error diffUsion window.

8. A hardware error diffusion calculation system as claimed in claim 7 wherein a said error diffusion calculation block further comprises a multiply accumulate block coupled to said data buses for said second and third memory blocks and having an output for determining a quantised hologram pixel value for writing to said hologram memory block.

9. A hardware error diffusion calculation system as claimed in claim 8 wherein said quantisation comprises binarisation, and wherein said error diffusion calculation block further comprises a threshold block to threshold data derived from said output of said multiply accumulate block.

10. A hardware error diffusion calculation system as claimed in any claim 8 or 9 wherein said error diffusion calculation block further comprises circuitry to update said error memory block with a quantisation error value determined using said quantised hologram pixel value.

11. A hardware error diffusion calculation system as claimed in any preceding claim including said first, second and third memory blocks.

12. A hardware error diffusion calculation system as claimed in any preceding claim embodied in an FPGA or ASIC.

13. A holographic image display system including the hardware error diffusion calculation system of any preceding claim.

14. A holographic image display system as claimed in claim 13 wherein a displayed image is formed from a sequence of holographically generated spatially overlapping temporal subframes.

15. A holographic image display system as claimed in claim 14 further comprising a holographic subfraine calculation system coupled to said error diffusion calculation system such that said error diffusion quantisation for one subframe is performed concurrently with hologram calculation for a subsequent subframe.

16. A holographic image display processing system, the system being configured to provide data to display an image holographically, said image being defined by displayed image data, the system comprising: a first system to generate hologram data from said image data; a second system to quantise said hologram data for display; and wherein said first and second systems are pipelined such that said hologram data quantisation is performed concurrently with said hologram data generation.

17. A holographic image display processing system configured to provide data to display said image using a plurality of holographically generated temporal subframes, said temporal subframes being displayed sequentially in time such that they are perceived as a single noise-reduced image, wherein said first system is configured to generate hologram data for a said subframe from said image data, and wherein said first and second systems are pipelined such that said hologram data quantisation for one subframe is performed concurrently with said hologram data generation for a subsequent subframe.

18. A holographic image display system as claimed in claim 16 or 17 wherein said second system comprises a hardware error diffusion calculation system.

19. A holographic image display system as claimed in any one of claims 16 to 18 wherein said first system comprises a hardware system to generate said hologram data.

20. A holographic image display system as claimed in any one of claims 16 to 19 wherein said first system comprises an OSPR engine.

21. A holographic image display system including a holographic image display processing system as claimed in any one of claims 16 to 20.

Amendments to the claims have been filed as follows I. A hardware error diffusion calculation system for performing an error diffusion quantisation of a hologram, the system comprising: an address bus and a data bus for a first, hologram memory block, said hologram memory block for storing data representing pixels of said hologram; an address bus and a data bus for a second, error memory block, said error memory block for stonng an error matrix representing errors in quantising said hologram; an address bus and a data bus for a third, diffusion weights memory block, said diffusion weights memory block for storing a set of diffusion weights for said error diffusion calculation; and a plurality of error diffusion processor blocks each coupled to said address and data buses for each of said first, second and third memory blocks, each of said processor blocks being configured for sequential processing of a spatial region of said hologram, a said processor block including a pixel address generator to generate a sequence of pixel addresses for a said spatial region for processing by the processor block and an error diffusion calculation block coupled to said pixel address generator and to said address and data buses to perform an error diffusion calculation for a pixel of said hologram identified by a said pixel address; wherein spatial regions processed by said processor blocks overlap, and wherein each of said processor blocks has a different start pixel address, such that said processor blocks are able to perform error diffusion calculations with respective said error diffusion calculation blocks on different pixels of said hologram in parallel.

2. A hardware error diffusion calculation system as claimed in claim 1 further comprising a scheduler to generate a control signal for each processor block to control each said processor block to start processing in turn.

3. A hardware error diffusion calculation system as claimed in claim 1 or 2 wherein a said processor block further comprises a controller to provide said start pixel address.

4. A hardware error diffusion calculation system as claimed in claim 3 when dependent on claim 2 wherein said scheduler is configured to generate a value (k) dependent on a size of said hologram in pixels in one dimension (P;u), and wherein said controller is configured to determine said start pixel address from said value (k).

5. A hardware error diffusion calculation system as claimed in claim 4 wherein each said processor block has a processor block identifier, and wherein a said controller is configured to determine said start pixel addresses using said processor block identifier such that said spatial regions are distributed along a direction (v) orthogonal to a direction of said first dimension.

6. A hardware error diffusion calculation system as claimed in any preceding claim wherein said sequence of pixel addresses defines a generally diagonal path through a said spatial region processed by a said processor block.

7. A hardware error diffusion calculation system as claimed in any preceding claim wherein a said error diffusion calculation performed by a said error diffusion calculation block is performed over an error diffusion window, and wherein a said error diffusion calculation block comprises a memory controller coupled to said pixel address generator and to said address buses for at least said second to third memory blocks to provide a set of addresses for said second and third memory blocks to cover said error diffusion window.

8. A hardware error diffusion calculation system as claimed in claim 7 wherein a said error diffusion calculation block further comprises a multiply accumulate block coupled to said data buses for said second and third memory blocks and having an output for determining a quantised hologram pixel value for writing to said hologram memory block.

9. A hardware error diffusion calculation system as claimed in claim 8 wherein said quantisation comprises binarisation, and wherein said error diffusion calculation block further comprises a threshold block to threshold data derived from said output of said multiply accumulate block.

10. A hardware error diffusion calculation system as claimed in any claim 8 or 9 wherein said error diffusion calculation block further comprises circuitry to update said error memory block with a quantisation error value detennined using said quantised hologram pixel value.

11. A hardware error diffusion calculation system as claimed in any preceding claim including said first, second and third memory blocks.

12. A hardware error diffusion calculation system as claimed in any preceding claim embodied in an FPGA or ASIC.

13. A holographic image display system including the hardware error diffusion calculation system of any preceding claim.

14. A holographic image display system as claimed in claim 13 wherein a displayed image is formed from a sequence of holographically generated spatially overlapping temporal subframes.

15. A holographic image display system as claimed in claim 14 further comprising a holographic subframe calculation system coupled to said error diffusion calculation system such that said error diffusion quantisation for one subframe is performed concurrently with hologram calculation for a subsequent subframe.