GB2409119A

GB2409119A - A charge-sharing window comparator

Info

Publication number: GB2409119A
Application number: GB0426472A
Authority: GB
Inventors: Frank Ohnhaeuser; Mikael Badenius
Original assignee: Texas Instruments Deutschland GmbH
Current assignee: Texas Instruments Deutschland GmbH
Priority date: 2003-12-03
Filing date: 2004-12-03
Publication date: 2005-06-15
Anticipated expiration: 2024-12-03
Also published as: GB2409119B; DE10356453B4; GB0426472D0; DE10356453A1

Abstract

The input signals Vinn and Vinp are sampled by C1p and C1n. In a first measurement phase the charge sharing network 14, C1p, C2p, C1p, C2n provides potentials at input nodes Cp and Cn of the comparator which permit the comparator 12 to determine if the differential input voltage between 20 and 22 is greater than one half of the reference voltage 16. In the second measuring phase the potential at node Cp is changed by an amount equal to the reference voltage so that the comparator 12 can determine if the differential input voltage is less than minus one half of the reference voltage 16. The unit 18 responds to the successive outputs form the comparator 12 to provide a window comparator output 34. There is no requirement for a level shifter, an inverting amplifier, or multiple comparators, each of which can exhibit offset and gain error. Hysteresis may be implemented by additional capacitors (figure 5).

Description

24091 1 9 Window Comparator And Method Of Providing A Window Comparator

Function The present invention relates to a method of providing a window comparator function with a single comparator unit and to a window comparator comprising a single comparator circuit.

A window comparator monitors an input voltage and provides a digital output which indicates whether the input voltage is within or without a predefined voltage window. For reasons of compatibility, the input voltage is normally a differential input voltage. The window comparator is quite difficult to implement in a standard analog circuitry. The differential input voltage has to be converted to a single ended signal using an instrumentation amplifier. The single ended signal needs to be compared with the reference voltage that sets the window width and also with the inverted reference voltage. This means an inverting amplifier and two comparators are also necessary to implement the window comparator. So, the conventional approach requires at least four units, i.e. level shifter, inverting amplifier, and two comparators, each of these units having an offset and a gain error. Because of the amount of involved circuitry, trimming or calibration is required to achieve the demanded accuracy.

The total sum of these errors causes a very loose specification for offset and hysteresis. In order to prevent oscillation at the output of the window comparator when the input voltage exceeds the limits of the predetermined window, a hys teresis must be added. But if a hysteresis is required, things get even more com plicated.

The present invention provides a window comparator function with only a single comparator unit.

Specifically, the invention proposes a method of providing a window comparator function with a single comparator unit that has a positive input, a differen- tial negative input and an output. Limits of a window are defined by a reference voltage and a window condition is defined for a differential voltage between a positive input voltage and a negative input voltage so that the differential voltage is within the limits of the window. The method according to the invention comprises the following steps: providing a common mode voltage; providing a first set of two switched capacitors, each of which has a first electrode connected to the positive input of the comparator unit; providing a second set of two switched capacitors, each of which has a first electrode connected to the negative input of the comparator unit; providing a switching array capable of assuming a plurality of different switching conditions; - switching the second electrode of the capacitors in the first set selectively between the positive input voltage, the reference voltage and zero voltage potential; switching the second electrodes of the capacitors in the second set selec tively between the negative input voltage and zero voltage potential; and - detecting the output of the comparator unit in relation to the switching condition of the switching array.

With this method, since only one comparator is required, the accuracy of the comparator function is significantly improved. The accuracy of the comparator function can be improved by a factor about 10 compared to a common window comparator. Other components which were required for the conventional window comparator are not needed any more with the method according to the invention, allowing a simplified design of a circuit for performing the proposed method.

In a further development of the invention, the plurality of switching conditions comprise a first switching condition wherein the first electrodes of the capacitors in the first set are both connected to the common mode voltage, the second electrodes of the capacitors in the first set are connected to the positive input voltage and to the reference voltage, respectively, and the second electrodes of the capacitors in the second set are connected to the negative input voltage and to zero voltage potential, respectively; a second switching condition wherein the first electrodes of the capacitors in the first set are both disconnected from the common mode voltage, the second electrodes of the capacitors in the first set are both connected to the reference voltage and the second electrodes of the capacitors in the second set are both connected to zero voltage potential; a third switching condition wherein the first electrodes of the capacitors in IS the first set are both disconnected from the common mode voltage, the second electrodes of the capacitors in the first set are both connected to zero voltage potential and the second electrodes of the capacitors in the second set are both connected to zero voltage potential.

With this method, one window comparator result can be received after only three clock cycles.

The invention further provides a window comparator comprising a single comparator circuit that has a positive input, a negative input and an output, wherein limits of a window are defined by a reference voltage and a window condition is defined for a differential voltage between a positive input voltage and a negative input voltage so that the differential voltage is within the limits of the window. The comparator comprises further a common mode voltage source, a first set of two switched capacitors, each of which has a first electrode connected to the positive input of the comparator circuit, and a second set of two switched capacitors, each of which has a first electrode connected to the negative input of the comparator circuit.

A switching array capable of assuming a plurality of different switching conditions and means for switching the second electrodes of the capacitors in the first set selectively between the positive input voltage, the reference voltage and zero voltage potential are also provided, further, means for switching the second elec bodes of the capacitors in the second set selectively between the negative input voltage and zero voltage potential and detecting means for detecting the output of the comparator unit in relation to the switching condition of the switching array. No trimming or calibration is required, therefore, the window comparator can easily be implemented. Since only a single comparator circuit is used, the window com parator can operate very efficiently at only low power. So, this window comparator is particularly suitable for mobile implementations such as automotive use.

Further advantages and features of the invention will become apparent from the following detailed description with reference to the appending drawings. In the drawings: - Figure 1 shows a block diagram of a window comparator according to a first embodiment of the invention; - Figures 2 4 show schematics for illustrating the function of the window com- parator from Figure I in four different states; - Figure 5 shows a block diagram for a window comparator according to a second embodiment of the invention; - Figure 6 shows a diagram illustrating the input and output signals of a win- dow comparator.

The block diagram of Figure I shows a window comparator 10 comprising a comparator circuit 12, a switch array 14, a reference voltage source 16, and a con trol unit 18. The comparator circuit has a positive input cp, a negative input c,, and an output cO,,. The inputs cp and c,, are connected to the switching array 14, the design and function of which will be explained in detail below.

The switching array 14 is also connected to the reference voltage source 16 which provides a reference voltage Vre; defining the width of the comparator window. Alternatively, an external reference voltage source can be used. The switching array 14 is further connected to input terminals 20, 22 for receiving a positive input voltage Vjnp and a negative input voltage Van, respectively, and to a common mode voltage source 24, providing a common mode voltage Veal, e.g. a constant voltage which sets the bias point for the comparator circuit 12.

The control unit 18 is connected to the switching array 14 via a command line for controlling the operation of the switching array 14. The control unit 18 is driven by a clock Cl,K from a clock generator 32. The control unit 18 is also con- nected to the output cO,, of the comparator circuit 12 for detecting the output of the comparator unit 12 in relation to the switching condition of the switching array 14.

The control unit 18 finally has an output 34 connected to an output terminal 36 of the window comparator 10 for providing a resulting output signal res.

The window comparator 10 further comprises a plurality of capacitors, in cluding a first set of two capacitors Cap, C2p, each of which has a first electrode connected to the positive input cp of the comparator circuit 12, and a second set of two capacitors Can, C2n, each of which has a first electrode connected to the nega tive input en of the comparator circuit 12. The capacitors Cap, C2p, Cal have their second electrodes connected to the switching array 14 while capacitor C2n has its second electrode permanently connected to zero voltage potential. Preferably all capacitors are of the same capacity to avoid asymmetries.

Figure 6 shows a typical transfer function of the window comparator. The comparator output res is high if the differential input voltage V6jf is within the limits -Vies; Vied defining the width ofthe comparator window. To prevent the comparator from toggling at high frequency when the input voltage is near one of the limits, a hysteresis Viny can be added.

The operation of the window comparator 10 will now be explained in detail referring to Figures 2 through 4. These Figures show schematically the window comparator 10 with the switching array l 4 being in three different switching con- ditions. These switching conditions relate to three clock cycles of the control unit 18, which are necessary to receive one window comparator result.

Referring now to Figure 2, the switching array 14 is in a first switching condi- lion in which the capacitors Cap and Cal are connected to the differential analog input voltages Vinp and Vi,n, respectively on one side and to a common mode voltage Void on the other side, which side is also connected to the comparator inputs cp and en. In this state, an offset occurring at the comparator output cool can be compensated. Capacitor C2n is always connected to the comparator circuit input on on one side and to a zero voltage potential (OV) on the other side, while capacitor C2p is connected to comparator circuit input cp on one side and to the reference voltage Vref on the other side. So, during the first clock cycle, which will be called the sampling clock cycle, each capacitor is charged by the voltage it is connected to.

Therefore, the charges at the inputs cp and en can be calculated to: IS Qs,cp = Cp(Vnp-Vmid) + C2p(Vref-Void) = C(Vjnp + Vref-2Vmid) for cp and Qs on = Cin(Vinn-Vmid) + C2n( -Vmid) = C(Vinn-2Vmid) for on.

At the beginning of the second clock cycle, which is a first measurement cycle, the charges get frozen when the control unit 18 is driving the switching array 14 into a second switching condition which is shown in Figure 3. In this second switching condition the inputs cp and on of the comparator circuit 12 and the ca- pacitors connected thereto arc disconnected from the common mode voltage Void.

Also, the capacitor Cn, is disconnected from the negative input voltage Vjnn and connected to OV. So, the charge on the negative input c', of the comparator circuit 12 during this first measurement cycle is: Qc( ) en = C n(O-cn) + C2n(0- cn) = C(0-2cn) As the charge is frozen, Qc en is equal to Qscn and therefore: en = Vivid- inn.

The second switching condition of switching array 14 also has the capacitor Cap disconnected from the positive input voltage Vjnp and connected to the reference voltage Viol: Therefore, the charge on the positive node can be calculated to: Qc(),cp = Cp(ref-cp) + C2p(ref-cp) = C(2ref- 2cp) this charge has also been frozen and therefore Qc,cp is equal to Qs,cp Cp(l) = V _ inp rcJ The output cOU, of the comparator circuit 12 will be high (COW! = 1) if call _ on, and therefore: VrCf_ Vinp Vinn which means that the comparator output cO,, is high when the differential input voltage remains below the reference voltage Vial: In the first measurement clock cycle, the control unit 18 can only decide whether the differential input voltage is higher than the positive reference voltage.

But if the differential input voltage is negative, i.e. Vjnp - Vine, < 0, then it can be below the lower limit of the comparator window, which is defined by the inverse of the reference voltage -V,er: Therefore, a second measurement needs to be done during a third clock cycle.

Figure 4 shows the third switching condition of the switching array 14 during this third clock cycle, the second measurement clock cycle. The capacitors Cap and C2p are disconnected from the reference voltage VrCf and connected to OV. There fore7 charges on these capacitors are now referenced to OV, and: g Qc(2),cp = Cp(O-cp) + C2p(0-cp) = C(0-2cp) which is again equal to Qs,cp, so CP(2) Vmil 2 Since the comparator circuit output cow is high if Cp(2) _ n -ref_ Vnp -Van which means that the output of the comparator circuit is high (Coral = 1) if the differential input voltage is lower than the inverted reference voltage V ref.

Based on these measurements during clock cycles 2 and 3, the control unit 18 is able to detect whether the differential input voltage Vjnp - Vnn is within the com lO parator window, which means within the range V ret to Vref, if c0u() = l and COu(2) = O. The clock cycles I through 3 are repeated sequentially, therefore the meas- urement is repeated every three clock cycles. The control unit 18 can be driven by an internal clock from clock generator 32 or alternatively from a clock provided 1 5 externally.

A second embodiment of the invention, which is shown in Figure 5, introduces a hysteresis V'1y to prevent a high frequency toggling of the comparator output 36 should the absolute differential input voltage be equal to the reference voltage. in the switched capacitor approach of this invention, the hysteresis is not essential any more, since the output is digital and updated every three clock cycles, but it is very easy to implement.

To provide a hysteresis, the window comparator l lO of Figure 5 comprises in addition two capacitors C3p and C3,, that have one end connected to the positive input cp and the negative input on of the comparator circuit 112, respectively. The capacity of these hysteresis capacitors C3p and C3, , iS small compared to the other q capacitors. The other end of these capacitors C3p and C3n is toggled by the switching array 1 14 between OV and constant voltage Vcons which defines the hysteresis width.

The toggling of the switching array 1 14 is controlled by the control unit 118 depending on the state of the comparator circuit output coin. If the differential input voltage is within the comparator window, the switches of the array 114 keep the other sides of capacitors C3p and C3n to OV. Therefore, they do not influence the equations given above. If the differential input voltage is not within the comparator window (Vinp-V;nn > Vreror Vjnp - Vjnn < Veer), the capacitors C3p and C3n are lO switched to the constant voltage Vc,ns which defines the hysteresis width. Thus: ref - Vhy _ Vjnp - Vjnn and -(ref-Vhy) _ Vinp-Vinn.

This means that the upper and the lower limits of the comparator window are shifted towards the middle of the window, effectively reducing the width of the comparator window.

Claims

Claims 1. A method of providing a window comparator function with a single

com parator unit that has a positive input (cp), a differential negative input On and an output (cO,,), wherein limits of a window are defined by a reference voltage (Vial) and a window condition is defined for a differential voltage between a positive input voltage (Vjnp) and a negative input voltage (Vjn,') so that the differential voltage is within the limits of the window, comprising the steps of a) providing a common mode voltage (Van); b) providing a first set oftwo switched capacitors (Cap, C2p) each of which has a first electrode connected to the positive input (cp) of the comparator unit; c) providing a second set of two switched capacitors (C'n, C2n) each of which has a first electrode connected to the negative input (en) of the comparator unit; d) providing a switching array capable of assuming a plurality of different switching conditions; e) switching the second electrodes of the capacitors (Cap, C2p) in the first set selectively between the positive input voltage (Vjnp), the reference voltage (Vice) and zero voltage potential (OV); f) switching the second electrodes ofthe capacitors (C'n, C2n) in the second set selectively between the negative input voltage (Vine) and zero voltage (OV); g) detecting the output (c,,) of the comparator unit in relation to the switching condition of the switching array.
2. The method of claim 1, wherein the capacitors in the first and second set are all provided with the same capacitance.
3. The method of claim I or claim 2, wherein the plurality of switching con- ditions comprise - a first switching condition wherein the first electrodes ofthe capacitors (Cap, C2p) in the first set are both connected to the common mode voltage (Vmj)' the second electrodes of the capacitors (Cap, C2p) in the first set are con nected to the positive input voltage (Vjnp) and to the reference voltage (Vies), respectively, and the second electrodes of the capacitors (Can, C2n) in the second set are connected to the negative input voltage (Van) and to zero voltage potential (OV), respectively; - a second switching condition wherein the first electrodes of the capacitors (Cap, C2p) in the first set are both disconnected from the common mode voltage (Van), the second electrodes of the capacitors (Cap, C2p) in the first set are both connected to the reference voltage ref. and the second electrodes of the capacitors (Can, C2n) in the second set are both connected to zero voltage potential (OV); - a third switching condition wherein the first electrodes of the capacitors (Cap, C2p) in the first set are both disconnected from the common mode voltage (Van), the second electrodes of the capacitors (Cap, C2p) in the first set are both connected to zero voltage potential (OV) and the second elec bodes of the capacitors (Can, C2n) in the second set are both connected to zero voltage potential (OV).
4. The method according to claim 3, comprising the step of deciding that the differential input voltage is within the window limits when the output (cou()) of the comparator unit in the second switching condition is in a first condition and the output (co,(2)) of the comparator unit in the third switching condition is in a second condition opposite to the first condition.
5. The method of claim 3 or claim 4, wherein the first through third switching conditions are cycled through continuously. jowl
6. The method of claim 5, wherein a clock signal is used to cycle through the switching conditions.
7. The method according any of the preceding claims, wherein the first and second sets of capacitors each comprise a third capacitor (C3p, C3n) having a first electrode connected to the first electrodes of the capacitors in the same set and a second electrode connected to zero voltage potential (OV) when the differential input voltage is within the window limits and to a constant voltage (VcOns) when the differential input voltage is outside of the window limits.
8. A window comparator ( 10) comprising a single comparator circuit ( 12) that has a positive input (cp), a differential negative input (en) and an output (cOUr)' wherein limits of a window are defined by a reference voltage (Vrer) and a window condition is defined for a differential voltage between a positive input voltage (Vjnp) and a negative input voltage (Van) so that the differential voltage is within the limits of the window, comprising i. a common mode voltage source (24); ii. a first set of two switched capacitors (Cap, C2p) each of which has a first electrode connected to the positive input (cp) of the comparator circuit (12); iii. a second set of two switched capacitors (Can, C2n) each of which has a first electrode connected to the negative input (en) of the comparator circuit (12); iv. a switching array (14) capable of assuming a plurality of different switching conditions; v. means for switching the second electrodes of the capacitors (C p, C2p) in the first set selectively between the positive input voltage (Vjnp), the reference voltage (Vim) and zero voltage potential (OV); vi. means for switching the second electrodes ofthe capacitors (C'n, C2n) in the second set selectively between the negative input voltage (Vine) and zero voltage potential; vii. detecting means (18) for detecting the output (cOU) of the comparator S unit (12) in relation to the switching condition of the switching array.
9. The window comparator of claim 8, comprising a clock generator (32) for controlling the switching array.
10. The window comparator according to claim 8 or claim 9, comprising a constant voltage source (16), wherein the first and second sets of capacitors each lO comprise a third capacitor (C3p, Can) having a first electrode connected to the first electrodes of the capacitors in the same set and a second electrode connected to zero voltage potential (OV) when the differential input voltage is within the window limits and to the constant voltage (VcOns) when the differential input voltage is outside of the window limits.
11. The window comparator of claim 10, wherein the third capacitor (C3p, C3n) in each set has a capacitance which is small in comparison to the capacitance of other capacitors in the same set.