GB2408145A

GB2408145A - Method and system for hermetically sealing packages for optics

Info

Publication number: GB2408145A
Application number: GB0423507A
Authority: GB
Inventors: Xiao Yang
Original assignee: Miradia Inc
Current assignee: Miradia Inc
Priority date: 2003-10-24
Filing date: 2004-10-22
Publication date: 2005-05-18
Anticipated expiration: 2024-10-22
Also published as: KR20050039635A; US20080014682A1; TW200525769A; US8022520B2; CN1638115A; CN101252122A; CN101252122B; US20070072328A1; DE102004051361A1; CN101183675A; US7303645B2; US20110186839A1; CN101183675B; US20050101059A1; JP2005167209A; US20070235852A1; GB0423507D0; CN101202272A; US7671461B2; GB2408145B

Abstract

A method and corresponding system for hermetically sealing devices. The method comprises providing a substrate 310 which includes a plurality of individual chips 315. Each of the chips 315 includes a plurality of devices and the chips 315 are arranged in a spatial manner as a first array (see Fig. 5B). The method also provides a transparent member 320 of a predetermined thickness which includes a plurality of recessed regions 339 arranged in a spatial manner as a second array, and a stand-off region 325. The method also includes aligning the transparent member 320 in a manner to couple each of the recessed regions 339 to a respective one of the chips 315. The method further includes hermetically sealing each of the chips 315 within one of the respective recessed regions 339 by using at least a bonding process to isolate each of the chips 315 within one of the recessed regions 339.

Description

I\lETHOD AND SYSTEM FOR HERMETICAI,LY SEALING PACKAGES F()R OPTIf,S

BACKGROUND OFTHEVENTION

100011 This present invention relates generally to manufacturing objects. More particularly, the invention provides a method and structure for hermetically bonding a transparent cover to a semiconductor substrate. Merely by way of example, the invention has been applied to a transparent glass cover hermetically bonded to a semiconductor wafer containing a micro-mechanical electrical system. The method and structure can be applied to display technology as well as, for example, charge coupled display camera arrays, and infrared arrays.

l0002l The packaging of silicon integrated circuits has reached a high level of maturity.

FIG. I illustrates a sirmplife1 diagram of a conventional silicon integrated circuit package.

Thc silicon integrated circuit die 110 is mounted on a submount 115 featuring a ball grid array 120. Wire bonds 125 are attached to the silicon die 110 to provide electrical connection to the submount 115. Typically, the silicon die 110 and the wire bonds 125 are encapsulated using a plastic encapsulant 130. The resulting package is robust and inexpensive.

10003] The package illustrated in FIG. 1 presents several drawbacks in applications that often require more than electrical operation of the silicon integrated circuit. An example of such an application is optical reflection off an array of micro-mirrors or other MEMS structure. For example, these applications typically require the ability to illuminate the top of the silicon integrated circuit with optical energy and subsequently reflect the optical energy off the top of the silicon integrated circuit with high efficiency. The optical properties of the plastic encapsulant, including lack of transparency, non-unifornaity of the index of refraction, and surface roughness make these packages unsuitable for this application. Additionally, many MEMS often require an open space above the surface of the silicon integrated circuit to enable the micro-electro-mechanical structures to move in the direction parallel to the plane of the MEMS as well as in the direction perpendicular to the plane of the MUMS. The physical contact that the plastic encapsulant makes with the surface of the integrated circuit, therefore, rr!aLc this package unsuitabIc for many MEMS applications.

SUMMARY OF THE INVENTION

10004] This present invention relates generally to manufacturing objects. More particularly, the invention provides a method and structure for hermetically bonding a transparent cover to a semiconductor substrate. Merely by way of example, the invention has been applied to a transparent glass cover hermetically bonded to a semiconductor wafer containing a micro-mechanical electrical system. The method and structure can be applied to display technology as well as, for example, charge coupled display camera arrays, and infrared arrays.

1 SI In a specific embodiment according to the present invention, a method for hermetically sealing devices is provided. The method includes providing a substrate that includes a plurality of individual chips, each of the chips including a plurality of devices. In this specific embodiment according to the present invention, the chips are arranged in a spatial manner as a first array. The array configuration in this embodiment includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips. The second street regions intersect the first street regions to form the array configuration. The method also includes providing a transparent member of a predetermined thickness. The transparent member in this embodiment includes a plurality of recessed regions within the predetermined thickness and arranged in a spatial manner as a second array. Preferably, each of the recessed regions is bordered by a standoff region. In this specific embodiment, the standoff region has a thickness defined by a portion of the predetermined thickness. The method also includes aligning the transparent member in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. The transparent member is aligned such that the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions. The method also includes hermetically sealing each of the chips within one of the respective recessed regions by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions. Preferably, the hermetic sealing uses at least a bonding process to isolate each of the chips within one of the recessed regions.

6] In an alternative specific embodiment, the invention provides a system for hermetically sealing devices. The system comprises a substrate configured to include a plurality of individual chips. Each of the chips includes a plurality of devices. Addtionally, each of the chips are arranged in a spatial manner as a first array. The array configuration includes a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips. The second street regions intersect the first street regions to form the array configuration. The system further comprises a transparent member of a predetermined thickness. The transparent member is configured to include a plurality of recessed regions within the predetermined thickness. The plurality of recessed regions are arranged in a spatial manner as a second array. Furthermore, each of the recessed regions are bordered by a standoff region having a thickness defined by a portion of the predetermined thickness. The substrate and the transparent member arc aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Accordingly, the standoff region is coupled to each of the plurality of first street regions and is coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective recessed regions. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.

100071 These and other objects and features of the present invention and the manner of obtaining them will become apparent to those skilled in the art, and the invention itself will be best understood by reference to the following detailed description read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

10008] FIG. 1 is a simplified diagram of a conventional silicon integrated circuit package.

100091 FIG. 2 is a simplified diagram of a conventional hermetically sealed transparent integrated circuit package.

10010] FIGS. 3A - 3D are simplified diagrams of a wafer-level hermetically sealed package according to an embodiment of the present invention.

100111 FIGS. 4A and 4B are simplified diagrams of a transparent member according to an embodiment of the present invention formed from two transparent components.

100121 FIG. 5A is a simplified top view of a transparent mcmUcr and substrate according to an embodiment of the present invention at the time of hermetic sealing.

100131 FIG. SB is a simplified diagram of four transparent members and a substrate according to an alternative embodiment of the present invention at the time of hermetic sealing.

[00141 FIGS. 6 is a simplified diagram of a single micro-miTTor chip after hermetic sealing according to an embodiment of the present invention.

100151 FIG. 7 is a simplified diagram of a die level package including a hermetically sealed die according to an embodiment of the present invention.

100161 FIG. 8 is a simplified diagram illustrating the operation of a reflective system according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[00171 According to the present invention, techniques for manufacturing objects are provided. More particularly, the invention provides a method and system for hermetically sealing packages for objects. Merely by way of example, the invention has been applied to the hermetic sealing of an optical micro-mirror package. The method and system can be applied to sensor technology as well as other MEMS devices where hermetic packaging is required.

8] FIG. 2 illustrates a simplified diagram of a conventional hermetically sealed transparent integrated circuit package useful for optical illumination of a micro-mirror array.

In FIG. 2, a silicon MEMS die 210 featuring a micro-mirror array 215 is mounted on a submount 220. The die is attached to the submount using die attach procedures that are compatible with hermetically sealed packaging requirements well known to those skilled in the art. Wire bonds 225 are attached to the silicon die and the submount as with the package illustrated in FIG. 1.

9] To provide an open space above the micro-mirror array 215, a solid standoff230 is typically placed near the outer edge of the submount. This standoff is typically shaped as a square annulus and fabricated from cover or other suitable materials. The standoff is often brazed onto the submount at contact points 235. A glass cover plate 240 is typically brazed onto the top of the standoff at contact points 245 to seal the package.

0] The COSt of the package illustrated in FIG. 2 is typically high, in some cases around $70. Additionally, it is usually necessary to assemble the package in a clean room environment to prevent potential handling damage and contamination. Thus, there is a need for an improved method and system for hermetically sealing packages for objects.

[00211 FIGS.3A - 3D are simplified diagrams of a wafer-level hermetically sealed package according to an embodiment of the present invention. These diagrams illustrate examples according to specific embodiments. One of ordinary skill in the art would recognize various modifications, alternatives and variations. Preferably, fonnation of the package occurs prior to separation of the active devices into die fond. FIere, separation often occurs using a dicing and/or scribing and breaking process, among others. Additional details of the present method are provided throughout the present specification and more particularly below.

2] In the embodiment illustrated in FIG.3A, a substrate 310 is processed according to methods to form an array of individual chips 315 on a substrate. In an embodiment according to the present invention, the substrate 310 is a CMOS semiconductor wafer, for example, Si, and the chips 315 are MEMS. An example of one way of forming these MEMS is described in U.S. Patent Application Serial Number 60/390,389, commonly owned, and hereby incorporated by reference for all purposes. In the embodiment illustrated in FIG.3A, the chips include a plurality of devices. Additionally, the CMOS wafer is processed to form integrated circuits 312, metal traces for electrical leads 314, and other CMOS structures. In an embodiment according to the present invention, the devices are micro-mirrors arranged in a multi-dimensional array, e.g., two-dimensional array. In alternative embodiments, the plurality of devices comprise a plurality of charge coupled devices (CCD), a plurality of deflection devices, a plurality of sensing devices, an integrated circuit device, any combination of these, and the like.

l0023l In the embodiment illustrated in FIG. 3B, a transparent member 320 is provided that includes a plurality of recessed regions 325 in the lower surface of the transparent member.

The transparent member has a predetermined thickness 330. In an embodiment according to the present invention, the thickness of the transparent member is 1.2 mm. Alternatively, the thickness ranges from about 0.5 mm to about 3 mm in other embodiments. Of course, the thickness will depend upon the particular applications.

l0024l Preferably, the recessed region is a volume defined within a member. The volume has a depth 322 defined by the distance from the bottom of the transparent member 324 to the top of the recessed region 339. The outer edges of the recessed region are defined by the vertical edges of standoffs 335. In an embodiment according to the present invention, the volume of the recessed regions is uniform across the transparent member.

[00251 According to an embodiment of the present invention, the individual standoffs 335 comprise an annular rectangular ring with height 322 oriented in a plane parallel to the x-y plane. The lower surface of the standoff is prepared, in an embodiment according to the present invention, to mate to the substrate and form a bond sufficient to form a hermetically sealed package, as is discussed in detail below.

6] In embodiments according to the present invention, the depth of the recessed region is a predetermined depth. In the embodiment illustrated in FIG. 3B, the depth 332 of the recessed regions is 0.5 mm. Alternatively, the depth ranges from about 0.1 mm to about I mm in other embodiments. Of course, the depth of the recessed region will depend on the particular applications. Additionally, in embodiments according to the present invention, the area of the individual recessed regions will be a predetermined size. In the embodiment illustrated in FIG. 3B, the area of the individual recessed regions is about 14 mm x 18 mm.

Depending on the specific applications, this area may vary in size.

7] The recessed regions formed in the transparent member are arranged in a spatial manner to form a multi-dimensional array in the x-y plane. In some embodiments according to the present invention, the recessed regions are arranged to form a two-dimensional array in the x-y plane. In the embodiment illustrated in FIGS. 3A - 3D, the depth and the x-y dimensions of the recessed regions 325 are greater than the height and the x-y dimensions of the chips 315. Accordingly, the chips fit within the recessed regions and the edges ofthe recessed regions are separated from the outer edges of the chips in all three dimensions.

Moreover, in the embodiment illustrated in FIGS. 3A and 3B, the center-tocenter spacing of the recessed regions in both the x and y dimensions exceeds the size of the recessed regions 2S in both the x and y dimensions, respectively, providing space for the standoff regions 335 between adjacent chips. The lateral dimension of the standoff regions have a predetermined size. In an embodiment according to the present invention the lateral dimension of the standoff region ranges betwocn 0.5 mm and l.O mm.

10028] In an embodiment according to the present invention, the transparent member is formed from a product sold under the name of Corning Eagle2000 display grade glass substrate manufactured by Corning Incorporated of Corning, New York. The glass substrate is characterized by high optical quality, including, but not limited to, optical power transmittance in the visible region of greater than 90%. The transmittance of light through the member can be increased by the application of anti-reflection (AR) coatings to the optical surfaces of the substrate, as disclosed below. Additionally, Corning Eagle20"0 display grade glass is used in some embodiments according to the present invention because the coefficient of thermal expansion of the glass substrate is close to the coefficecnt of thermal expansion of Si.

[00291 For a material, by definition, the thermal strain at temperature T is the change in length of a member, due to a change in temperature, (TTref), divided by the original length I of that member. Denoting thermal strain at temperature T as eTfT), e.(l)= thc/'llot. (l) 100301 Also, by definition, the coefficient of thermal expansion for a material, denoted as c(T) is, d T (2) 100311 In embodiments according to the present invention in which temperature variation as a function of time is expected, it is useful to match the coefficient of thermal expansion (CTE) of the transparent cover to the CTE of the substrate. The matching of these CTEs limits the amount of warping and stress introduced in the substrate due to temperature variation.

10032] In the embodiment illustrated in FIGS. 3A - 3D, the transparent member is designed and fabricated to reduce optical absorption and thereby increase the transmission of optical energy at the wavelength range of interest. In an embodiment according to the present invention, the wavelength range of interest is the visible spectrum between 400 and 700 nm.

Additionally, in this embodiment, the top surface of the member 337 and the top surface of the recessed regions 339 are polished or finished to provide optical quality surfaces.

Moreover, AR coatings may be applied to the top surface of the transparent member and the top surface of the recessed regions. The AR coatings applied to the top surface of the transparent member will reduce the amount of light reflected off the top of the transparent member as it impinges on the package and thereby increase the amount of light that reaches the micro-mirror array 315. Moreover, AR coatings applied to the top of the recessed regions will reduce the amount of light reflected off the transparent member as it leaves the package.

Overall system throughput will be increased by the use of these AR coatings. Quarter wave (/4) coatings of MgF2 or other suitable dielectric materials can be used to form broadband AR coatings. For example, a X/4 MgF2 coating centered at 550 non (with an index of refraction of 1.38 at 550 nm) deposited on a Corning Eagle2000 display grade glass substrate, results in a power reflectance less than 2% per surface across the visible spectrum (400 - 700 nary).

3] The transparent member can be worked to form the recessed regions in a variety of ways. For example, in one embodiment according to the present invention, the recessed regions can be etched into the transparent member by the use of dry or wet chemical etching, laser machining, acoustic machining, water jet machining, or the like.

100341 In an alternative embodiment according to the present invention, the transparent member is formed by machining a first planar component and subsequently bonding a separate transparent component to the first component as illustrated in FIG. 4. The first planar component 410 is a planar substrate that is machined or otherwise worked to form openings at locations in which recessed regions 415 are to be positioned. Additional openings are formed at positions 417 to form through holes used for attachment of wire bonds to the chip interconnect region, as will be described below. Unmachined areas of the first planar component will form the standoff regions 420. A second, planar transparent component 430 is bonded to the top of the first planar component to form the completed transparent member. In a specific embodiment according to the present invention, the first planar component and the second planar transparent component are both transparent. A side view of the completed transparent member taken along the plane A-A of FIG. 4A is illustrated in FIG. 4B. As illustrated in FIG. 4B, the standoffregions 420 and the top transparent component 430 are illustrated.

10035] One of the benefits provided by this alternative fabrication process is that the optical properties of the two components are not always similar. In fact, for some applications, the optical properties of the first component illustrated in FIGS. 4A and 4B do not impact system performance. For example, depending on the optical path through the package, light may never impinge on the first component. In other embodiments according to the present invention, it is desirable to absorb any light that does impinge on the lower component.

[00361 In an embodiment according to the present invention, the optical properties of the transparent member are predetermined. In a specific embodiment, the transmittance and absorption coefficient of the transparent member are uniform as a function of position in the x-y plane.

7] In an embodiment according to the present invention, the bonding of the two transparent components is accomplished by low temperature glass frit bonding or other methods known to those of skill in the art. Additionally, AR coatings are applied to the top and bottom of the second transparent component prior to bonding to increase optical throughput. As discussed above, in this embodiment according to the present invention, the optical quality of the second transparent member will control the optical quality of light passing through the top of the recessed regions, enabling the use of polishing and coating methods not applicable to embodiments in which the transparent member is formed from a single substrate.

[00381 In an embodiment according to the present invention, hermetically sealed die-level packages are formed by coupling the transparent member to the substrate. FIG.3C is a simplified diagram of the transparent member and the substrate at the time of hermetic sealing. The transparent member is aligned in a manner to position the standoff regions 340 and 342 above the street regions 344 and 346. The individual chips 350 are located below and in communication with an associated recessed region 352 and hermetically sealed by the transparent cover 354 at contact points 356 located at the base of the standoff regions 342.

Through holes 354 provide access to bond pads 358 located on the CMOS wafer.

[00391 Hermetic sealing of the transparent member to the substrate is performed according to several methods well known to those skilled in the art. For example, in an embodiment according to the present invention, hermetic sealing is performed by plasma activated covalent wafer bonding (PACWB). PACWB is performed at room temperature after the substrate and transparent member have been cleaned, for example, in SC1 (NH3:H2O2:H2O, 1:4:20) at 60 C, rinsed in de-ionized (DI) water, dipped in 2% HE for 20 seconds, rinsed in DI water and dried with N2 or air. The substrate and transparent member are then exposed, for example, to an oxygen plasma in a reactive ion etcher at a chamber pressure of about 35 mTorr. In an alternative embodiment according to the present invention, the substrate and transparent member are exposed to an argon plasma. After plasma treatment, the surface of the silicon oxide is hydrophilic, promoting bonding. The substrate and the transparent member are brought into contact at room temperature in a preselected ambient environment.

In alternative embodiments according to the present invention, other bonding techniques are used, for example, eutectic low temperature bonding and anodic bonding.

0] In an embodiment according to the present invention, the hermetic sealing process S illustrated in FIG. 3C is performed in an environment comprising inert gases. Examples of inert gases are N2 and Ar, among others. The benefits provided by hermetic sealing in an inert environment include, but are not limited to dampening of oscillations present in the devices and the prevention of electrical arcing. For example, if the devices are micro-mirrors arranged in an array, oscillations present during operation and motion of the micro-mirrors are damped and attenuated by the presence of the inert gas. Additionally, the possibility of electrical arcing between the elements of the micro- n1irror array and/or the drive electronics is reduced by the presence of the inert gas.

10041] FIG. SA is a top-view of the device illustrated in FIG. 3C at the time of hennetic sealing. The standoff regions S 10 running in the ydirection are located above the parallel 1 S street regions 512 and the standoff regions S 1 S running in the x- direction are located above the parallel street regions 517. Bond pads 520 are located at the right and led sides of the active devices 522. As illustrated in FIG. 3C, through holes 348 in the transparent member provide access to the bond pads.

10042] In an embodiment according to the present invention, the hermetic sealing process is performed by bonding a single transparent member to a single substrate. In this embodiment, the size of the single transparent member is selected to correspond to the size of the substrate.

For example, a transparent member approximately 30 cm in width and length is bonded to a substrate 30 cm in diameter. Alternatively, the transparent member may be rectangular and larger in size than the substrate. In an alternative embodiment according to the present invention, the size of the transparent substrate is only a fraction of the substrate size. In this alternative embodiment, before hermetic sealing, multiple transparent members are arranged to align with matched areas on the substrate surface. The multiple transparent members are subsequently bonded to the substrate. For example, FIG. 5B illustrates a simplified diagram of four transparent members 552, 554, 556, and 558 arranged in a two-dimensional array above an array of chips 560 located on the substrate. In the alternative embodiment illustrated in FIG. 5B, the transparent members are manufactured so that adjacent transparent members abut each other at planes 570 and 572. However, this is not necessary. Additional alternative embodiments according to the present invention may align the transparent members differently.

!00431 FIG. 3D illustrates; according to an embodiment of the present invention the separation of individual dies after hermetic sealing is completed. In the embodiment illustrated in FIG. 3D, the individual dies 360 are separated along lines running in the y- direction located between adjacent bond pads. In the x-direction, the dies are separated to align the plane of separation with the through holes 362 located in the transparent member outside of the recessed region 364. For comparison, the lines in the y- direction and x- direction are illustrated in FIG. 5A as lines 530 and 535, respectively.

4] In a specific embodiment according to the present invention, the individual dies are separated by cutting the substrate into dies using a diamond saw. In an alternative embodiment, the dies are separated by scribing the substrate using a diamond scribe. In an embodiment of the invention in which the substrate is a silicon wafer, the die separation is performed by sawing the silicon substrate with a rotating circular abrasive saw blade.

[00451 FIG. 6 is a top-view of a single die according to an embodiment of the present invention. The lateral dimensions of the chip and recessed region are predetermined sizes. In the embodiment illustrated in FIG. 6, the lateral dimensions of the chip 610 is about 17 rnrn by 13 mm. The center to center spacing of the chip is about 21 mm in the x-direction and 17 rrun in the y-direction. The chip in this specific embodiment comprises a 1024 x 768 array of micro-mirrors 615. The edges of the micro- mirrors are separated from the standoff regions 620 in the x and y directions by a distance of O.S mm. The standoff regions are 0.5 mm in width. Through holes 625 and 627 to the left and right of the standoff regions, respectively, provide access to bond pads 630 100 lam in size and set on a lSO rim pitch. Alternatively, the center to center spacing of the chip 610 is 16 mm x 12 mm, resulting in a separation between the chip and the standoff regions of 0.25 mm. Of course, these dimensions will depend upon the particular applications.

l0046l In an embodiment according to the present invention, the surface roughness of the standoff regions that come in contact with the substrate is reduced to a predetermined level.

An Atomic Force Microscopy (AFM) is typically used to characterize the surface roughness of the lower surface of the standoff region. For example, a Digital Instruments EnviroScope_ from Veeco Instruments, Inc. can be used. 100471 For example, in a specific embodiment according to the present

invention, the root mean square surface roughness of the lower surface of the standoffregions is less than or equal to 2 A for a 2 Am by 2 Am area. In alternative embodiments according to the present invention, the surface roughness is about 3 A RMS over a 2 rim by 2 Am area.

100481 FIG. 7 is a simplified diagram of a die level package useful for making electrical connection to a hermetically sealed package and mounting the package according to an embodiment of the present invention.

10049] FIG. 7 illustrates an embodiment according to the present invention in which the hermetically sealed package is mounted on a lead frame structure, such as a ball grid array.

The separated CMOS die, chip, and hermetically sealed package previously described are illustrated as 705. In an embodiment according to the present invention, at least one interconnect region is associated with each chip on the substrate. In the embodiment illustrated in FIG. 7, the interconnect region or bonding pads 710 are located, for example, on or near the top surface of the wafer. In an embodiment according to the present invention, the interconnect pads are electrically connected to the plurality of devices to actuate the mechanical devices according to a MEMS algorithm. Thus, electrical signals presented at the interconnect region 710 result in mechanical motion of the devices 715. As disclosed previously, in a specific embodiment according to the present invention, the electrical signals presented at the interconnect region 710 deflect some or all ofthe micro-mirrors present in the micro-mirror array to preferentially reflect light passing through the transparent member 717 and incident on the micro-mirror array.

10050] In order to electrically connect the interconnect region (and thus the devices) to external drivers, wire bonds 720 are connected from the interconnect pads 710 to electrical connections located on the lead frame structure 725. In an embodiment according to the present invention, the wire bonds are made using Au wires about 25 1lm in diameter, which are capable of carrying in excess of 500 MA of current. In the embodiment according to the present invention illustrated in FIG. 7, the wire bonds are encapsulated in encapsulant 730.

The use of cncapsulants, for example, plastic, to protect electrical components from environmental damage is well known to those skilled in the art. The lead frame, in some embodiments, is brazed onto a heat spreader 742 to reduce the thermal load on the hermetically sealed package.

[00511 In FIG. 7, the encapsulant is applied to encapsulate at least a portion of the lead frame, the wire bonds, the interconnect regions, and the sides of the transparent member adjacent the through holes, while maintaining a surface region 735 of the transparent member located above the recessed region free from encapsulant. Thus, the optical properties of the surface region 735 are unaffected by the application of the encapsulant. In the embodiment illustrated in FIG. 7, the total thickness 740 of the die level package is 1.27 mm. Thus, the package illustrated in FIG. 7 combines both a hermetically sealed package useful for optical MEMS and a non-hermetically sealed plastic encapsulated package.

10052] FIG. 8 illustrates the operation of a reflective system employing a specific embodiment of the present invention. In embodiments according to the present invention, it is desirable to spatially filter light incident on and reflected from the package. In the embodiment illustrated in FIG. 8, a beam of light from a light source 810 is incident on the top surface of the transparent member 815. A portion of the light 830 passing through the transparent member is incident on the surface of the plurality of devices, in this embodiment, a micro-mirror array 820. Another portion of the light 835 from the lamp 810 is blocked or filecred by filter mask 825 located at the periphery of the transparent member. Light blocked by the left, top and bottom sides of filter mask 825 is not able to reach the micro-mirror array.

In addition, light reflected off portions of the chip other than the micro-mirror array is blocked by the right side of the filter mask. Thus, by the use of filter mask 825, the reflected light passing to detector 840 is limited to a selected portion of the original beam that is incident on the package.

[00531 In the embodiment illustrated in FIG. 8, the filter mask is located on the upper surface of the transparent member, however, this is not required. In alternative embodiments, the filter mask is located on the lower surface or sides of the transparent member. In an additional embodiment according to the present invention, the use of non-transparent materials in the fabrication of the transparent member can complement the filter mask. In an embodiment according to the present invention, the filter mask comprises a layer of chrome.

In alternative embodiments, the filter mask is made from other reflective or absorptive materials.

100541 In the embodiment illustrated in FIG. 8, the filter mask forms an aperture region that blocks light from impinging on or reflecting from portions of the die other than the micro mirror array. In alternative embodiments, the filter mask is only used to block light on the incident (left) side and not on the exit (right) side of FIG. 8.

100551 While the above is a complete description of specific embodiments of the invention, the above description should not be taken as limiting the scope of the invention as defined by the claims.

Claims

WHAT IS CLAIMED IS: I 1. A method for hermetically sealing devices, the

method comprising: 2 providing a substrate, the substrate including a plurality of individual chips, 3 each of the chips including a plurality of devices, each of the chips being arranged in a spatial 4 manner as a first anray, the array configuration including a plurality of first street regions arranged in strips and a plurality of second street regions arranged in strips, the second street 6 regions intersecting the first street regions to fonm the affray configuration; 7 providing a transparent member of a predetermined thickness, the transparent 8 member including a plurality of recessed regions within the prcdetermiled thickness and 9 arranged in a spatial manner as a second array, each of the recessed regions being bordered by a standoff region, the standoff region having a thickness defined by a portion of the 11 predetermined thickness;

12 aligning the transparent member in a manner to couple each of the plurality of 13 recessed regions to a respective one of said plurality of chips whereupon the standoff region 14 Is coupled to each of the plurality of first street regions and coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective 16 recessed regions; and 17 hermetically sealing each of the chips within one of the respective recessed 18 regions by contacting the standoff region of the transparent member to the plurality of first 19 street regions and second street regions using at least a bonding process to isolate each of the 2() chips within one of the recessed regions.

1 2. The method of claim l wherein each of the first street regions has a 2 first width ranging from about 0.5 mm to 1.0 mm in dimension and each of the second street 3 regions has a second width ranging from about 0.5 mm to 1.0 man in dimension.

1 3. The method of claim I wherein the transparent member has an optical 2 power transmittance of greater than about 99%.

1 4. The method of claim I wherein the transparent member is 2 characterized by a coefficient of thermal expansion aT, the coefficient of thermal expansion 3 is about the same as a coefficient of thermal expansion as of the substrate.

] 5. The method of claim I wherein the transparent member comprises an 2 antiref]ective coating disposed overlying surface regions of each of the recessed regions.

1 6. The method of claim I wherein each of the recessed regions is formed 2 by a process selected from dry or wet etching, laser machining, acoustic machining, and 3 casting.

1 7. The method of claim I wherein the transparent member comprises a 2 first transparent member overlying a standoff layer, the standoff layer including the standoff 3 region.

1 8. The method of claim I wherein the standoff layer comprises a second 2 transparent member.

1 9. The method of claim I wherein the bonding process is selected from at 2 least a plasma activated bonding, eutectic bonding, glue layer or adhesive bonding, welding, 3 anodic bonding, and fusion bonding.

I 10. The method of claim I wherein the transparent member is 2 characterized by a thickness ranging from about 0.1 mm to 1.2 mm.

1 1 1. The method of claim 1 wherein each of the chips is maintained within 2 an inert environment within one of the respective recessed regions.

1 12. The method of claim I I wherein the inert enviromnent is selected from 2 nitrogen, argon, or a mixture of nitrogen and argon.

1 13. The method of claim 12 wherein the inert environment causes a 2 damping process.

1 14. The method of claim 12 wherein the inert environment causes a 2 reduction in electrical breakdown.

I 15. The method of claim 1 wherein each of the chips comprises an 2 interconnect region, the interconnect region being outside of the recessed region.

1 16. The method of claim 15 wherein the interconnect region is exposed 2 through a through hole region on the transparent member.

1 17. The method of claim 16 wherein the interconnect region comprises a 2 plurality of bonding pads.

1 18. The method of claim I wherein the substrate comprises a silicon 2 bearing material.

1 19. The method of claim 18 wherein the substrate is a silicon wafer.

I 20. The method of claim I wherein each of the recessed regions comprises 2 a first surface region coupled to a second surface region, the first surface region and the 3 second surface region characterized to be of optical quality.

1 21. The method of claim 20 wherein the first surface region has a root 2 mean square surface roughness of less than or equal to 2 A for a 2 Am by 2 1lm area.

1 22. The method of claim 1 wherein each of the recessed regions is annular 2 in shape.

1 23. The method of claim 1 wherein each of the recess regions has a depth 2 of about 0.5 mm and less.

1 24. The method of claim 1 wherein the transparent member comprises a 2 first side and a second side, the first side being parallel to the second side, the first side and 3 the second side being coated with an antireflective material.

1 25. The method of claim 24 wherein the coating of antireflective material 2 reduces the reflectance of visible light at the first side and the second side to less than 2% per 3 side.

1 26. The method of claim 24 wherein the antireflective material comprises 2 MgF2.

1 27. The method of claim 1 further comprising: 2 dicing at least one of the chips by scribing a portion of each of the first street 3 regions and by scribing a portion of each of the second street regions; 4 attaching at least one of the chips within one of the respective recessed regions to a lead frame structure; 6 wire bonding a portion of the attached chip to a portion of the lead frame 7 structure; and 8 encapsulating the wire bonded portion of the attached chip and the portion of 9 the lead frame structure while maintaining a surface region of the transparent substrate defiecd on the recessed region free of encapsulant.

1 28. The method of claim I wherein each of the recessed regions has a 2 peripheral region that filters out light.

1 29. The method of claim I wherein each of the recessed regions has a 2 peripheral region that fowls an aperture region overlying a portion of one of the respective 3 chips.

1 30. The method of claim I wherein at least one of the plurality of devices 2 comprises a plurality of charge coupled devices, a plurality of deflection devices, a plurality 3 of sensing devices, and an integrated circuit device.

1 31. A system for hermetically sealing devices, the system comprising: 2 a substrate, the substrate configured to include a plurality of individual chips, 3 wherein each of the chips includes a plurality of devices; 4 wherein each of the chips are arranged in a spatial manner as a first array, the array configuration including a plurality of first street regions arranged in strips and a 6 plurality of second street regions arranged in strips, the second street regions intersecting the 7 first street regions to form the anray configuration; 8 a transparent member of a predetermined thickness, the transparent member 9 configured to include a plurality of recessed regions within the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array, I 1 and wherein each of the recessed regions are bordered by a standoff region having a thickness 12 defined by a portion of the predetermined thickness; 13 wherein the substrate and the transparent member are aligned in a manner to 14 couple each of the plurality of recessed regions to a respective one of said plurality of chips, whereupon the standoff region is coupled to each of the plurality of first street regions and is 16 coupled to each of the plurality of second street regions to enclose each of the chips within 17 one of the respective recessed regions; and 18 wherein each of the chips within one of the respective recessed regions is 19 hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to 21 isolate each of the chips within one of the recessed regions.

] 32. The system of claim 31 wherein each of the first street regions has 2 first width ranghlg from about 0.5 mm to l.O mm in dimension and each of the second street 3 regions has a second width ranging from about 0.5 mm to 1.0 mm in dimension.

1 33. The system of claim 31 wherein the transparent member has an optical 2 power transmittance of greater than about 99%.

1 34. The system of claim 31 wherein the transparent member is 2 characterized by a coefficient of thermal expansion aT, the coefficient of thermal expansion 3 is about the same as a coefficient of thermal expansion as of the substrate.

1 35. The system of claim 31 wherein the transparent member comprises an 2 antireflective coating disposed overlying surface regions of each of the recessed regions.

1 36. The system of claim 31 wherein each of the recessed regions is formed 2 by a process selected from dry or wet etching, laser machining, acoustic machining, and 3 casting.

1 37. The system of claim 31 wherein the transparent member comprises a 2 first transparent member overlying a standoff layer, the standoff layer including the standoff 3 region.

1 38. The system of claim 31 wherein the standoff layer comprises a second 2 transparent member.

1 39. The system of claim 31 wherein the bonding process is selected from 2 at least a plasma activated bonding, eutectic bonding, glue layer or adhesive bonding, 3 welding, anodic bonding, and fusion bonding.

1 40. The system of claim 31 wherein the transparent member is 2 characterized by a thickness ranging from about 0.1 mm to 1.2 mm.

1 41. 'I he system of claim 31 wherein each of the chips is maintained withal 2 an inert environment within one of the respective recessed regions.

1 42. The system of claim 41 wherein the inert environment is selected from 2 nitrogen, argon, or a mixture of nitrogeil and argon.

1 43. The system of claim 42 wherein the inert environment causes a 2 damping process.

1 44. The system of claim 42 wherein the inert environment causes a 2 reduction in electrical breakdown 1 45. The system of claim 31 wherein each of the chips comprises an 2 interconnect region, the intercomect region being outside of the recessed region.

1 46. The system of claim 45 wherein the interconnect region is exposed 2 through a through hole region on the transparent member.

1 47. The system of claim 46 wherein the interconnect region comprises a 2 plurality of bonding pads.

1 48. The system of claim 31 wherein the substrate comprises a silicon 2 bearing material.

1 49. The system of claim 48 wherein the substrate is a silicon wafer.

I SO. The system of claim 31 wherein each of the recessed regions 2 comprises a first surface region coupled to a second surface region, the first surface region 3 and the second surface region characterized to be of optical quality.

1 51. The system of claim SO wherein the first surface region has a root 2 mean square surface roughness of less than or equal to 2 A for a 2 1lm by 2 rim area.

1 52. The system of claim 31 wherein each of the recessed regions is annular 2 in shape.

1 53. The system of claim 31 wherein each of the recess regions has a depth 2 of about 0.5 mm and less.

1 54. The system of claim 31 wherein the transparent member comprises a 2 first side and a second side, the first side being parallel to the second side, the first side and 3 the second side being coated with an antireIlective material.

1 55. The system of claim 54 wherein the coating of antireflective material 2 reduces the reflectance of visible light at the first side and the second side to less than 2% per 3 side.

1 56. The system of claim 54 wherein the antireflective material comprises 2 MgF2.

1 57. The system of claim 31 further comprising: 2 a lead frame structure; 3 wherein at least one of the chips is diced by scribing a portion of each of the 4 first street regions and by scribing a portion of each of the second street regions, wherein at least one of the chips within one of the respective recessed regions 6 is attached to the lead frame structure; 7 wherein a portion of the attached chip is wire bonded to a portion of the lead 8 frame structure; and 9 wherein the wire bonded portion of the attached chip and the portion of the IO lead frame structure is encapsulated while maintaining a surface region of the transparent I I substrate defined on the recessed region free of encapsulant.

1 58. The system of claim 31 wherein each of the recessed regions has a 2 peripheral region that filters out light.

1 59. The system of claim 31 wherein each of the recessed regions has a 2 peripheral region that forms an aperture region overlying a portion of one of the respective 3 chips.

1 60. The system of claim 31 wherein at least one of the plurality of devices 2 comprises a plurality of charge coupled devices, a plurality of deflection devices, a plurality 3 of sensing devices, and an integrated circuit device.

61. A method of herrnetca]ly sealing devices wherein a plurality of chips inchdmg devices arc provided in an array on a substrate with space regions therebetween and wherein a transparent number having a corresponding array of recessed regions bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose each chip within a recessed region.

62. A system of hermetically sealed wherein a plurality of chips including devices are provided In an array on a substrate with space regions therebetween and wherein a transparent number having a corresponding array of recessed regions bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose each chip within a recessed region.

63. A method or system substantially as any one herein described or as illustrated In any of Figures 3 to 8.

Amendments to the claims have been filed as follows: -\11_T 1S i' DENIED i S I I A rnethoc1 for hern;ctcally seals do. ices, the method cotnpnsmg 2 yroN!id!!g slllslratc, tile substrate illcludillg:: p1llla!ity of Illdi. al clllps' 3 each ofthe chips including a pluiahty of devices, each ofthe chips being arranged in a spatial 4 manner as a first array, the array configuration including a plurality of first street regions analiged in strips and a plurality Of second street regions arranged in strips, the second street 6 regions intersecting the first street regions to form the array configuration; / providing a transparent member of a predetermined thickness, the transparent 8 member including a plurality of recessed regions within the predetermined thickness and 9 arranged in a spatial manner as a second array, each of the recessed regions being bordered by a standoff r egiQll, the standoff region having a thickness defined by a portion of the 11 predetermined thickness; 12 aligning the transparent member in a manner to couple each of the plurality of 13 recessed regions to a respective one of said plurality of chips whereupon the standoff region 14 Is coupled to each of the plurality of first street regions and coupled to each of the plurality of second street regions to enclose each of the chips within one of the respective 16 recessed regions; and 17 hermetically sealing each of the chips within one of the respective recessed 1 S regions by contacting the standoff region of the transparent member to the plurality of first 19 street regions and second street regions using at least a bonding process to isolate each of the 2V chips within onc of tile recessed reunions 1 2. The method of claim 1 wherein each of the first street regions has a 2 first width ranging from about 0.5 mrn to 1.0 mm in dimension and each of the second street 3 regions has a second width ranging from about 0.5 mm to 1.0 rums in dimension.

1 3. The method of claim I wherein the transparent member has an optical 2 power transmittance of greater than about 99%.

] 4. The method of claim I wherein the transparent member is 2 characterized by a coefficient of thermal expansion al, the coefficient of thermal expansion 3 Is about the same as a coefficient of thermal expansion as of the substrate I S. The method of claim I wherein the transparent men1ber comprises an 2 antircflectivc coating dsposcd ovcrl:ug surface regions of each of t]ie recessed rcgons. 2z

1 b. he method of claim 1 where n Erich of the recesses, r.ons is formed 2 by a process selected from dry or wet etching, laser machining, acoustic machmug, and 3 casting 1 7. The method of claim 1 wherein the transparent member comprises a 2 first transparent member overlying a standoff layer, the standoff layer including the standoff 3 region.

1 8. he method of claim I wherein the standoff layer comprises a second 2 transparent member.

1 9. T he method of claim 1 wherein the bonding process is selected from at 2 least a plasma activated bonding, eutectic bonding, glue layer or adhesive bonding, welding, 3 anodic bonding, and fusion bonding.

1 10. The method of claim 1 wherein the transparent member is 2 characterized by a thickness ranging from about 0.1 man to 1.2 mm.

1 11. The method of claim 1 wherein each of the chips is maintained within 2 an inert environment within one of the respective recessed regions.

1 12. he method of claim 11 wherein the inert environment is selected from 2 nitrogen, argon, or a mixture of nitrogen and argon.

1 13. The method of claim 12 wherein the inert environment causes a 2 damping process.

1 14. The method of claim 12 wherein the inert environment causes a 2 reduction in electrical breakdown.

1 15. The method of claim I wherein each of the chips comprises an 2 interconnect region, the interconnect region being outside of the recessed region.

I 16. The method of claim 15 wherein the interconnect r egion is exposed 2 through a through hole region on the transparent member.

1 17. The method of claim 16 wherein the intercoiect region comprises a 2 plurality of bonding pads.

I I h he method of claim I w',cren the subside ^.:npse: a s,.lcon 2 bearing matcral 19 The method of clang 18 wherein the substrate is a silicon wafer.

1 20. The method of claim I wherein each of the recessed regions comprises 2 a first surface region coupled to a second surface region, the first surface region and the 3 second surface region characterized lo be of optical quality 1 21 The method of claim 20 wherein the first surface region has a root 2 mean square surface roughness of less than or equal to 2 A for a 2 rim by 2,um area.

1 22. The method of claim 1 wherein each of the recessed regions is annular 2 in shape.

1 23. The method of claim I wherein each of the recess regions has a depth 2 of about 0.5 mm and less.

1 24. The method of claim I wherein the transparent member comprises a 2 first side and a second side, the first side being parallel to the second side, the f rst side and 3 the second side being coated with an antireflectve material.

1 25. The method of claim 24 wherein the coating of antireflective material 2 reduces the reflectance of visible light at the first side and the second side to less than 2% per 3 side.

1 26. The method of claim 24 wherein the antireflective material comprises 2 MgF:.

1 27. The method of claim I further comprising: 2 dicing at least one of the chips by scribing a portion of each of the first street 3 regions and by scribing a portion of eacl of the second street regions; 4 attaching at least one of the chips witlin one of the respective recessed regions to a lead frame structure; 6 wire bonding a portion of the attached chip to a portions of the lead frame 7 stnictiil-e; and 8 cncapsulaullg the Ire bonier portion of the attachf.1 chip ar,d the pod ion Of the lea/l frmc sircctr-e:,ic nant.anng surface regloss ot the transpaient substrate defined on the recessed region free ol encapsulant.

1 28. The method of claim I wherein each of the recessed regions has a 2 peripheral legion that filters out light.

1 29. The method of claim 1 wherein each of the recessed regions has a 2 peripheral region that fonns an aperture region over-lying a portion of one ofthe respective 3 chips.

1 30. The method of claim 1 wherein at least one of the plurality of devices 2 comprises a plurality of charge coupled devices, a plurality of deflection devices, a plurality 3 of sensing devices, and an integrated circuit device.

1 31. A system for hermetically sealing devices, the system comprising: 2 a substrate, the substrate configured to include a plurality of individual chips, 3 wherein each of the chips includes a plurality of devices; 4 wherein each of the chips are arranged in a spatial maimer as a first array, the array configuration including a plurality of first street regions arranged in strips and a 6 plurality of second street regions arranged in strips, the second street regions intersecting the 7 first street regions to form the array configuration; 8 a transparent member of a predetermined thickness, the transparent member 9 configured to include a plurality of recessed regions within the predetermined thickness, wherein the plurality of recessed regions are arranged in a spatial manner as a second array, 11 and wherein each of the recessed regions are bordered by a standoff region having a thickness 12 defined by a portion of the predetermined thickness; 13 wherein the substrate and the transparent member are aligned in a manner to 14 couple each of the plurality of recessed regions to a respective one of said plurality of chips, whereupoil tile standoff r egion is coupled to each of the plurality of first street regions and is 16 coupled to each of the plurality of second street regions to enclose each of the chips within 17 one of the respective recessed regions; and 18 wherein each of the chips within one of the respective recessed regions is 19 hermetically sealed by contacting the standoff region of the transparent member to the Dlirall,y off First stl<-cf regions 1nc1 seC nib SlTPf.' rP<j,nC l( iffy! -',?-t,, A'-'. 'A i,C^ <> 21 isolate Cacti of the chips u'1thnn one of the recessed mgons.

1 32. I'he system of claim 31 '..herein each ofthe first street legions has a 2 first width ranging from about 0.5 mm to 1 0 trim m dimension and each of the second street 3 regions has a second width ranging from about 0.5 mm to 1.0 mm in dimension.

1 33. The system of Claire 3 l wherein the transparent member has an optical 2 power- transmittance of greater than about 99 ,0.

l 34. The system of claim 31 wherein the transparent member is 2 characterized by a coefficient of thermal expansion XT, the coefficient of thermal expansion 3 is about the same as a coefficient of thermal expansion as of the substrate.

I 35. The system of claim 31 wherein the transparent member comprises an 2 antireflective coating disposed overlying surface regions of each of the recessed regions.

1 36. The system of claim 31 wherein each of the recessed regions is formed 2 by a process selected from dry or wet etching, laser machining, acoustic machining, and 3 casting.

1 37. The system of claim 31 wherein the transparent member comprises a 2 first transparent member overlying a standoff layer, the standoff layer including the standoff 3 region.

1 38. The system of claim 31 wherein the standofflayer comprises a second 2 transparent member.

1 39 The system of claim 31 wherein the bonding process is selected fror 2 at least a plasma activated bonding, cutectic bonding, glue layer or adhesive bonding, 3 weldings, anodc bonding, and fusion bonding 1 40 'I'he system of claim 3 l wherein the transparent member is 2 characterized by a thickness ranging fiord about 0.1 mm to 1.2 mm.

1 41 The system of claim 31 wherein each of the chips is maintained within 2 an inert envr-onrr1ent within one of the respective recessed regions.

1 42. i he SvSterm of claim 41 Herein. the inert CnNtiruniEcUt is sciccced fron, 2 nitrogen, argon, or a mixture of ntrogeii and argon 1 43. ]'he system of claim 42 wherein the inert environment causes a 2 damping process.

1 44. 'I'he system of claim 42 wherein the inert environment causes a 2 reduction in electrical breakdown 1 45. The system of claim 31 wherein each of the chips comprises an 2 interconnect region, the interconnect region being outside of the recessed region.

1 46. The system of claim 45 wherein the Interconnect region is exposed 2 through a through hole region on the transparent member.

1 47. The system of claim 46 wherein the interconnect region comprises a 2 plurality of bonding pads.

1 48. The system of claim 31 wherein the substrate comprises a silicon 2 bearing material 1 49. The system of claim 48 wherein the substrate is a silicon wafer.

1 50. The system of claim 31 wherein each of the recessed regions 2 comprises a first surface region coupled to a second surface region, the first surface region 3 and the second surface region characterized to be of optical quality.

1 5] . The system of claim 50 wherein the first surface region has a root 2 mean square surface rouglmess of'less than or equal to 2 for a 2 1lm by 2 Am area.

1 52. Tile system of claim 31 wherein each of the recessed regions is annular 2 in shape.

1 53. The system of claim 31 wherein each of the recess regions has a depth 2 of about O.S mm and less.

1 5 The system Of Claire. 31 he, e.n the transpai Or,. merAl1oer compr!sc. s I. 2 first side and a second side, the first side being parallel to the second side, the first side and 3 the second side being coated with an:ntireflcctve mtccrial 1 55. The system of claim 54 wherein the coating of antireflective material 2 reduces the reflectance of visible light at the first side and the second side to less than 2% per 3 side.

1 56. The system of claim 54 wherein the antireflective material comprises 2 MgF2 ] 57. The system of claim 31 further comprising: 2 a lead frame structure; 3 wherein at least one of the chips is diced by scribing a portion of each of the 4 first street regions and by scribing a portion of each of the second street regions, wherein at least one of the chips within one of the respective recessed regions 6 Is attached to the lead frame structure; 7 wherein a portion of the attached chip is wire bonded to a portion of the lead 8 frame structure; and 9 wherein the wire bonded portion of the attached chip and the portion of the lead frame structure is encapsulated while maintaining a surface region of the transparent 1 I substrate defined on the recessed region free of encapsulant 1 58. The system of claim 31 wherein each of the recessed regions has a 2 peripheral region that filters out light.

1 59. The system of claim 31 wherein each of the recessed regions 1as a 2 peripheral region that forms an aperture region overlying a portion of one of the respective 3 chips.

1 6() The system of claim 31 wherein at least one of the plurality of devices 2 comprises a plurality of charge coupled devices, a plurality of deflection devices, a plurality 3 of sensing devices, and an integrated circuit device. q

61. A method of heretically sealing devices wlleren a plurality of CilipS including devices are provided In an array on a substrate with space regions therebetween and wherein a transparent member having a corresponding ad-ray of recessed r egions bordered by a standoff region is aligned with the substrate and the standoff region bonded to the space regions to enclose each chip within a recessed region.

62. A system of hermetically sealed wherein a plurality of chips including devices are provided in an array on a substrate with space regions therebetween and wherein a transparent member having a corresponding array of recessed regions bordered by a standoff region is aligned with thesubstrate and the standoff region bonded to the space regions to enclose each chip within a recessed region.

63. A method or system substantially as any one herein described or as illustrated In any of Figures 3 to 8.