GB2406984A - Method and arrangement for I-Q balancing and radio receiver incorporating same - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
- H03D3/009—Compensating quadrature phase or amplitude imbalances
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Abstract
A method and arrangement for self-tuning I-Q balancing 200 for an I-Q radio receiver 100 by: performing 210 Discrete Fourier Transform (DFT) of the I and Q orthogonal signals to produce therefrom complex DFT I and Q signals evaluated at a balancing frequency; performing 220 quadrature phase-shifting of one of the complex DFT I and Q signals; performing 230 power measurement of the complex DFT I and Q signals over a plurality of frequencies, and choosing therefrom the balancing frequency; deriving 230 from the complex DFT I and Q signals a balance mismatch signal between the I and Q signals; and applying 240 the balance mismatch signal to the other of the I and Q signals whose complex DFT signal was not phase-shifted during the quadrature phase-shifting step to reduce balance mismatch.
Description
METHOD AND ARRANGEMENT FOR I-Q BALANCING AND RADIO
RECEIVER INCORPORATING SAME
Field of the Invention
This invention relates to I-Q (In-phase, Quadrature- phase) balancing and particularly (though not exclusively) to radio receivers based on I-Q architecture.
Background of the Invention
Radio receivers based on an I-Q architecture often require stringent balancing of the I-Q paths. For example, modern VLIF (Very Low Intermediate Frequency) receivers targeted at the GSM (Groupe Speciale Mobile) protocol require strict orthogonality between the I-Q paths to be achieved. Typically this balancing is achieved off-line during factory calibration, but such off-line calibration increases production cost and suffers from inflexibility since it does not allow for balancing changes that may be required (due to changes in operating conditions such as temperature and voltage variations) during use.
The problem of receiver I-Q balancing is not new and many patents exist in this area. For example, from patent publication WO 0044143 Al "CORRECTION OF AMPLITUDE AND PHASE IMBALANCE IN PSK RECEIVERS", INTERDIGITAL TECHNOLOGY CORPORATION, there is known an I-Q balancing technique using an amplitude detection and correction algorithm to balance the gain paths and a cross correlation algorithm to balance the phase paths. In this known I-Q balancing technique, the balancing is achieved in Polar format (gain-phase); furthermore, the embodiments of this technique proposed in this patent publication are not suited to an on-line autonomous implementation.
Also, for example, from patent publication WO 0191395 Al "DIGITAL COMMUNICATION RECEIVER WITH DIGITAL, IF, I-Q BALANCERS", ICOM, INC., there is known a technique for solving the problem of I-Q balancing using an Equaliser.
Again, the principles governing equalization in this technique are fundamentally different from a Cartesian Frequency based approach (known receivers being invariably Cartesian or I-Q based). In addition such an equalization technique would suffer from requiring the computational power of a DSP to realise the algorithm.
The disadvantages of the above known techniques can therefore be summarized as either: (i) Requiring costly factory phasing, and being unsuited to on-line, autonomous, self-phasing.
(ii) Not using a Cartesian-Frequency based approach (known receivers being invariably Cartesian or I-Q based).
(iii) Requiring DSP resources to implement the algorithm in practice. - 3
A need therefore exists for I-Q balancing for receivers wherein the abovementioned disadvantage(s) may be alleviated.
Statement of Invention
In accordance with a first aspect of the present invention there is provided a method for I-Q balancing as claimed in claim 1.
In accordance with a second aspect of the present invention there is provided a method for I-Q balancing as claimed in claim 3.
In accordance with a third aspect of the present invention there is provided an arrangement for I-Q balancing as claimed in claim 16.
In accordance with a fourth aspect of the present invention there is provided a method for I-Q balancing as claimed in claim 18.
In accordance with a fifth aspect of the present invention there is provided a radio receiver as claimed in claim 24.
Brief Description of the Drawings
One self-tuning balancer for I-Q receivers incorporating the present invention will now be described, by way of example only, with reference to the accompanying drawing(s), in which: FIG. 1 shows a block-schematic diagram illustrating a generalised embodiment of the balancing system in a GSM radio receiver; FIG. 2 shows a graphical representation of the I and Q channel signals in the balancing system of FIG. 1; and FIG. 3 shows a block-schematic diagram illustrating generation of the real component for the I channel in the balancing system of FIG. 1.
Description of Preferred Embodiment
Referring firstly to FIG. 1, a GSM radio receiver 100 includes quadraturephase mixing stage ll0 and analog and digital front end processing stage 120 for deriving I and Q channel signals from a received signal. The receiver also includes a balancing system 200 for balancing the I and Q channel signals.
The balancing system 200 is designed to be phased from an arbitrary received (RX) burst having a radio frequency - 5 (RF) input of the form A()cos{wct+Ft+(t)}' where me is the carrier frequency, OFF is the intermediate frequency, (t) is the PM (phase- modulated) or FM (frequency-modulated) component and A(t) is the AM (amplitude-modulated) component. I-Q mismatch occurs in the mixing down to the IF or baseband and in the analog front end processing.
Self-phasing of the balancer is carried out digitally at the baseband. The balancing is performed at the IF in the case of a DVLIF (Digital Very Low IF) architecture or at baseband in the case of a ZIF (Zero IF) architecture.
Im + it is the digitised mismatched, complex signal, resulting from the RF mixing and analog front end processing and is given by Im + jQm = Io + jQAqei q where lo+ jQ is the perfectly matched complex signal, A4ei Y is the gain and phase imbalance, which without loss of generality is referred to as the Q channel.
A set of balancing equations is formulated based on a single-point Discrete Fourier Transform (DFT) evaluated at the balancing frequency. These are solved to yield the complex gain, a+ jb=Aq'e in, which is the inverse of the complex mismatch gain. This gain is then used to balance the I and Q channels as follows Ib + jQh = Im + jQn,Aq e = Io + jQ (l.O) The self-phasing balancing system 200 consists of: 1. Single-point DFT (210) evaluated at the balancing frequency, lob producing a complex or orthogonal output for the I and Q channels: I(b) and Q(b) respectively.
2. A quadrature phase shifter (220) to shift the () channel by 90 .
3. Power measurement (230) to find the optimal balancing frequency.
4. Balancing Equation Solving (230) to find the inverse of the complex mismatch gain: a + jb = A -'e- irq 5. Complex Multiplier (240) to perform the balancing.
The single-point DFT (210) is evaluated at the balancing frequency and produces the complex output N-! I (aob) = {Im (n) + .iQm (n)} cos 0(n) _ Ire + jIim n=0 oh) {am (n)+ .iQm (n)} sin O(n) _ ore + jQim n=0 N-l N-l Ire = Re{/(ti)h)} = Im(1)cosi9(n) km = Im{I()b)} = Qm()cosO(n) ( 2.0) n=0 n=0 N-l N-l Q = Re {Q(C,)b)} = Im (n) sin 0(n) Qlm = Im {Q(03b)} = At, Qm (tl) sin O(n) (2 1) n=0 n=0 where the complex or orthogonal output components are Ok given by Im(mb)=Ire+jIim and Qm(h) = Qre + jQim 0(n) = N n corresponds to the phase of the balancing frequency, fh, where k = fh N. for a sampling rate of fs and N is the number of samples processed. 7
Phase shifting l(mb) by 90 (220) is equivalent to multiplying its complex representation by j, to give j}T/ I(cob)e /2 = j(Ire + jlim) =- Iim + jIre = X'e + iXim = X(ab) (3 0) Referring now also to FIG. 2, the balancing equations (230) are based on the following considerations. If there were no I-Q mismatches then lo) would be in perfect quadrature to Q(b) and Xj+ jX4 = Qi + jQq However' 0 due to gain and phase mismatch the Q channel vector will be phase shifted by Pq and scaled by Aq relative to the I channel. The balancing objective is to find the complex gain, a+ jb which will scale and rotate Qre+jQim to match it to the 90 phase shifted I channel. The balancing equation can therefore be expressed as if/ Qm ( )h)(a + jb) =I(a)b)e /2 (Qre + jQim)(a + jb) = j(Ire + jlim) = Xre + jXim ( 4. O) The balancing equation (4. O) can be expressed as a linear system of equations as follows Qre Qim 1Ir 1 _ te 1 LQim Qre ULb]-Lximl QO= x (5. O) The solution to equation (5. O) is given by = Q'x - 8 Ore Qim 1 [by Q Q; [Xlm] ( 5.1) Alternatively, using simple complex algebra on (4.0) the balancing gain is Are + pixie' (Xre + Alum)(Qre jQim) ( 5 2) a+Jb= = 2 2 Qre. + iQim Ore + Am The balancing is then completed as in (1.0) above Ih + iQb = Im + jQm (a + jb) Ih = Im-Qmb 0 Qb= Qma (6.0) Power measurement (230) is employed as follows. The success of this balancing scheme depends on an optimum choice of balancing frequency. Simulations confirm that this optimum frequency is where the signal to interference is maximum and of the order lOdB above the
background noise floor. This may be understood by
considering the GSM protocol, where for instance the alternate channel can be up to 41dB above the message.
In the case where the alternate channel power exceeds the message channel power then the balancing is done at the alternate channel and vice versa under the provision that the relevant power level is over lOdB above the noise floor.
A simple technique to select the balancing frequency is therefore to measure the power at the channel centre 9 frequency, adjacent (high and low) channels and both the alternate channels and then select the frequency that yields the highest power. The power at a given frequency can be calculated from Im(a)b)+Q,,,()b) (7.0) In practice, it is sufficient to have a relative measurement of the power which can be obtained by calculating either the power in the I or Q channel. For 0 the case of the Q channel, the power can be calculated from Qm (cob) = Q' + Qq (7.1) The optimum balancing frequency is then chosen as the frequency which yields the highest power measurement f b(opt) = max {Qm (ash) } (7.2) fh It will be appreciated that this is only one possible embodiment of a power measuring algorithm, and that the invention can generally adopt any one of numerous other power measuring algorithms.
The above description of blocks 210-240 can now be
summarised to form the basis for a self-phasing balancing algorithm: 1. Evaluate DFT (2.0) of the I and Q channel at candidate balancing frequencies, table (7.0) during an RX burst.
2. Evaluate power (7.1) at each frequency.
3. Select optimum balancing frequency (7.2). -
4. Formulate and solve balancing equation (5.0).
It will be appreciated that the above-described I-Q balancing system allows the radio to be 'self-tuning', eliminating the need for expensive factory and End-of- Line calibration and allowing increased flexibility in compensating for performance variations due to changes in operating conditions such as temperature and voltage.
This also fits well with the general industrial trend towards 'selftuning' radio transceivers will emerge in coming years.
It will also be appreciated that, although in the above example the invention has been described in the context of a radio receiver which is self-phasing or 'self- tuning, from an arbitrary received (RX) burst in a 'live' transmission employed during normal use of the system 'in the field', the I and Q signals may alternatively be derived from a predetermined or 'training' signal (e.g., "factory-phased") if desired.
It will also be understood that the above-described I-Q balancing system is a Cartesian-Frequency based approach, and provides a solution simple enough to be operated at 'gate level' in an integrated circuit.
It will be appreciated that, although the balancing (1.0) and (6.0) can be performed readily at the intermediate frequency, the performance of the above-described self phasing algorithm when run at IF depends critically on the power of the received signal relative to noise/interference (SNR). It will be understood that if SNR conditions prevent the algorithm from being satisfactorily run at IF, an alternative is to run the phasing algorithm in ZIF or Direct Conversion Receiver (DCR) mode sufficiently regularly to track temperature and Vcc drift. The resultant gain may then be used in normal VLIF mode at IF. This is particularly feasible in a receiver that contains both a VLIF and a ZIF path.
0 It will also be understood that, although in the above example the invention has been described in the context of a radio receiver, the same principle could also be used in a transmitter (not shown), in which a signal processed for transmission could be used to derive an I-Q imbalance signal which could be used to reduce imbalance in the signal for transmission.
In one preferred implementation, the above-described on- line, self-phasing of the balancing system can be achieved with minimum hardware overhead, as follows.
Beginning with the simplest stage, which is the 90 phase shift of the I channel (3.0), i.e., X,e=-I'm and X'm = Xre, it is clear that only a 2's complement inversion is required.
Next, consider the complex multiplication, (6.0), i.e., Ib =Im -Qmb and Qb =Qma. Here a multiplier and 2,s complement adder is required. The hardware to perform the single-point DFT - 12 N-1 N-1 I,e=Re{l(mb)}= Im(n) cos0(n) Jim =Im{I(b)}= Qm(n)coso(n) (2-0) tI=0 tI=() N-l N-l Q = Re{Q(b)} = Im(n)sin0(n) Qim =Im{Q(b)}= Qm(n)sin0(n)(2 l) n=0 n=0 may appear to be expensive, especially the trigonometric function, cosO(n) and sind(n). However, existing DVLIF receivers, may already possess a digital local oscillator (DLO), which can be programmed to generate cosO(n) and sin0(n). Consequently, to complete the transform a multiplier and an accumulator is all the addition hardware required. FIG. 3 illustrates an arrangement 300 for generating the real component for the I channel. As shown in FIG. 3, a DLO 310 receives a programmable word DIF corresponding to the DFT result, which is available when n = N. The DLO 310 generates respective output signals cos0(n) and sin0(n) , of which cos0(n) is mixed in a mixer 320 with the I channel signal Im(n). The output of the mixer 320 is applied to a summation node 330, whose output is applied to a filter 340. The output of the filter 340 is applied to another input of the summation node 320. The output of the filter thus produces the real component for the I channel signal I,e(n).
In the case where computational complexity and time are restricted then fast versions of the single point DFT could be employed, such as a single point FFT. In cases where spectral leakage is problematic, the sequence length N can be chosen to ensure coherent sampling.
Alternatively, windowing techniques could be applied to solve this problem. In short, all the standard DFT - 13 techniques can be employed to ensure the accuracy and efficiency of the single point OFT.
Finally, consider the realization of the balancing equation (5.2) QreXre + QimXim and h= @teXim 2QimXre Q,n Qm From an implementation cost, the division is problematic.
One option would be to write the DFT components up to a 0 baseband processor and solve the equations at the cost of processor capacity. In the likely event of unavailable processor capacity, an alternative approach is to use a recursive algorithm to solve iteratively the balancing equations. One such algorithm is the celebrated Least Mean Square (LMS) algorithm, renowned for its numerical robustness and computational simplicity. The derivation of the LMS in terms of the balancing equation results in the dual recursive equation a(n) = a(n 1) + u{Qrere(n) + Qimim (n)} by) = b(n-1) + ,u {Qrecim (n)-Qim Are (n) } ( 8. O) It will be appreciated that the self-tuning I-Q balancing system described above will typically be fabricated in an integrated circuit (not shown) for use in an I-Q radio receiver. It will also be appreciated that the self- tuning I-Q balancing system described above may alternatively be carried out in software running on a processor (not shown), and that the software may be provided as a computer program element carried on any - 14 suitable data carrier (not shown) such as a magnetic or optical computer disc.
It will be understood that the self-tuning balancing system for I-Q receivers described above provides the following advantages: It allows autonomous, on-line calibration/tuning of the balancer, eliminating the need for expensive factory and End-of-Line calibration.
Its implementation does not require a Digital Signal Processor (DSP), and is simple enough to be implemented at gate level.
In a preferred embodiment it re-uses standard building blocks already available in a typical I-Q based receiver. -
Claims (33)
- Claims 1. A method for balancing I-Q orthogonal signals in a communicationdevice, the method comprising: receiving an arbitrary signal containing I and Q signals and deriving from the received arbitrary signal the I and Q signals; deriving a balance mismatch signal between the I and Q signals; and 0 applying the balance mismatch signal to at least one of the I and Q signals to reduce balance mismatch.
- 2. The I-Q balancing method of claim l wherein the step of deriving a balance mismatch signal comprises: performing Discrete Fourier Transform (DFT) of the I and Q orthogonal signals to produce therefrom complex DFT I and Q signals evaluated at a balancing frequency; performing quadrature phase-shifting of one of the complex DFT I and Q signals; performing power measurement of the complex DFT I and Q signals over a plurality of frequencies, and choosing therefrom the balancing frequency; deriving from the complex DFT I and Q signals a balance mismatch signal between the I and Q signals; and applying the balance mismatch signal to the other of the I and Q signals whose complex DFT signal was not phase- shifted during the quadrature phase-shifting step to reduce balance mismatch. - 16
- 3. A method for balancing I-Q orthogonal signals, the method comprising: performing Discrete Fourier Transform (DFT) of the I and Q orthogonal signals to produce therefrom complex DFT I and Q signals evaluated at a balancing frequency; performing quadrature phase-shifting of one of the complex DFT I and Q signals; performing power measurement of the complex DFT I and Q signals over a plurality of frequencies, and choosing therefrom the balancing frequency; deriving from the complex DFT I and Q signals a balance mismatch signal between the I and Q signals; and applying the balance mismatch signal to the other of the I and Q signals whose complex DFT signal was not phase-shifted during the quadrature phase-shifting step to reduce balance mismatch.
- 4. The I-Q balancing method of claim l, 2 or 3 wherein the step of deriving a balance mismatch signal comprises performing a recursive algorithm.
- 5. The I-Q balancing method of claim 4 wherein the recursive algorithm is a Least Mean Square (LSM)-based algorithm.
- 6. The I-Q balancing method of any one of claims 2-5 wherein the plurality of frequencies includes a predetermined channel frequency, a frequency of an adjacent channel higher than said predetermined channel frequency and a frequency of an adjacent channel lower - 17 than said predetermined channel frequency, and choosing the frequency with substantially the highest measured power as the balancing frequency.
- 7. The I-Q balancing method of any one of claims 2-6 wherein the step of performing DFT comprises: providing a Digital Local Oscillator (DLO) producing first and second orthogonal trigonometric signals; providing a multiplier multiplying one of the 0 orthogonal trigonometric signals with a predetermined signal; and providing an accumulator accumulating the output of the multiplier over a range of values of the orthogonal trigonometric signals.
- 8. The I-Q balancing method of any one of claims 1-7 wherein the method is performed in an integrated circuit.
- 9. The I-Q balancing method of any one of claims 1-8 wherein the method is performed in a radio receiver.
- 10. The I-Q balancing method of claim 9 wherein the radio receiver comprises a VLIF radio receiver.
- 11. The I-Q balancing method of claim 9 wherein the radio receiver comprises a ZIF radio receiver.
- 12. The I-Q balancing method of claim 9, 10 or 11 wherein the radio receiver is a GSM radio receiver. - 18
- 13. The I-Q balancing method of any one of claims 1-8 wherein the method is performed in a radio transmitter.
- 14. The I-Q balancing method of any one of claims 3-13 wherein the I and Q orthogonal signals are derived from an arbitrary signal.
- 15. The I-Q balancing method of any one of claims 3-13 wherein the I and Q orthogonal signals are derived from a predetermined signal.
- 16. An I-Q balancing arrangement for use in a communication device, the arrangement comprising: means for receiving an arbitrary signal containing I and Q signals and deriving from the received arbitrary signal the I and Q signals; means for deriving a balance mismatch signal between the I and Q signals; and means for applying the balance mismatch signal to at least one of the I and Q signals to reduce balance mismatch.
- 17. The I-Q arrangement of claim 16 wherein means for deriving a balance mismatch signal comprises: Discrete Fourier Transform (DFT) means for performing DFT of the I and Q orthogonal signals to produce therefrom complex DFT I and Q signals evaluated at a balancing frequency; quadrature phase-shifting means for quadraturely phase shifting of one of the complex DFT I and Q signals; power measurement means for performing power measurement of the complex DFT I and Q signals over a plurality of frequencies, and choosing therefrom the balancing frequency; balance mismatch signal means for deriving from the complex DFT I and Q signals a balance mismatch signal between the I and Q signals; and balance mismatch reduction means for applying the balance mismatch signal to the other of the I and Q signals whose complex DFT signal was not phase shifted during the quadrature phase-shifting step to reduce balance mismatch. -
- 18. An I-Q balancing arrangement comprising: Discrete Fourier Transform (DFT) means for receiving I and Q orthogonal signals and for producing therefrom complex DFT I and Q signals evaluated at a balancing frequency; quadrature phase-shifting means for quadraturely phase shifting one of the complex DFT I and Q signals; power measurement means for receiving the complex DFT I and Q signals and for measuring power thereof over a plurality of frequencies, and for choosing therefrom the balancing frequency; balance mismatch signal means for deriving from the complex DFT I and Q signals a balance mismatch signal between the I and Q signals; and balance mismatch reduction means for applying the balance mismatch signal to the other of the I and Q signals whose complex DFT signal was not phase shifted by the phase-shifting means to reduce balance mismatch.
- 19. The I-Q balancing arrangement of claim 16, 17 or 18 wherein the balance mismatch signal means comprises means for performing a recursive algorithm.
- 20. The I-Q balancing arrangement of claim 19 wherein the recursive algorithm is a Least Mean Square (LSM) based algorithm.
- 21. The I-Q balancing arrangement any one of claims 17 wherein the plurality of frequencies includes a - 21 predetermined channel frequency, a frequency of an adjacent channel higher than said predetermined channel frequency and a frequency of an adjacent channel lower than said predetermined channel frequency, and means for choosing the frequency with substantially the highest measured power as the balancing frequency.
- 22. The I-Q balancing arrangement of any one of claims 17-21 wherein the DFT means comprises: Digital Local Oscillator (DLO) means for producing first and second orthogonal trigonometric signals; multiplier means for multiplying one of the orthogonal trigonometric signals with a predetermined signal; and accumulator means for accumulating the output of the multiplier means over a range of values of the orthogonal trigonometric signals.
- 23. The I-Q balancing arrangement of any one of claims 16-22 wherein the arrangement is fabricated in integrated circuit form.
- 24. A radio receiver incorporating the I-Q balancing arrangement of any one of claims 16-23.
- 25. The radio receiver of claim 24 wherein the radio receiver comprises a VLIF radio receiver.
- 26. The radio receiver of claim 24 wherein the radio receiver comprises a ZIF radio receiver. - 22
- 27. The radio receiver of claim 24, 25 or 26 wherein the radio receiver is a GSM receiver.
- 28. The I-Q balancing arrangement of any one of claims s 16-24 wherein the arrangement is comprised in a radio transmitter.
- 29. The I-Q balancing arrangement of any one of claims 18-28 wherein the I and Q orthogonal signals are derived from an arbitrary signal.
- 30. The I-Q balancing method of any one of claims 18-28 wherein the I and Q orthogonal signals are derived from a predetermined signal. 23
- 3l. An I-Q balancing arrangement substantially as hereinbefore described with reference to the accompanying drawings.
- 32. An I-Q balancing method substantially as hereinbefore described with reference to the accompanying drawings.
- 33. A radio receiver substantially as hereinbefore described with reference to the accompanying drawings.
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| GB0314202A GB2406984B (en) | 2003-06-18 | 2003-06-18 | Method and arrangement for I-Q balancing and radio receiver incorporating same |
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| Application Number | Priority Date | Filing Date | Title |
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| GB0314202A GB2406984B (en) | 2003-06-18 | 2003-06-18 | Method and arrangement for I-Q balancing and radio receiver incorporating same |
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| GB0314202D0 GB0314202D0 (en) | 2003-07-23 |
| GB2406984A true GB2406984A (en) | 2005-04-13 |
| GB2406984B GB2406984B (en) | 2005-12-21 |
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| GB0314202A Expired - Fee Related GB2406984B (en) | 2003-06-18 | 2003-06-18 | Method and arrangement for I-Q balancing and radio receiver incorporating same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008089841A1 (en) * | 2007-01-22 | 2008-07-31 | Freescale Semiconductor, Inc. | Calibration signal generator |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118794916B (en) * | 2024-09-13 | 2025-01-24 | 中赣通信(集团)有限公司 | On-chip room-temperature terahertz detector imaging system based on signal enhancement function |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2166324A (en) * | 1984-10-25 | 1986-04-30 | Stc Plc | A multi-mode radio transceiver |
| WO2001091395A1 (en) * | 2000-05-22 | 2001-11-29 | Sicom, Inc. | Digital communication receiver with digital, if, i-q balancer |
| US6377620B1 (en) * | 1999-01-19 | 2002-04-23 | Interdigital Technology Corporation | Balancing amplitude and phase |
| US20030072393A1 (en) * | 2001-08-02 | 2003-04-17 | Jian Gu | Quadrature transceiver substantially free of adverse circuitry mismatch effects |
-
2003
- 2003-06-18 GB GB0314202A patent/GB2406984B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2166324A (en) * | 1984-10-25 | 1986-04-30 | Stc Plc | A multi-mode radio transceiver |
| US6377620B1 (en) * | 1999-01-19 | 2002-04-23 | Interdigital Technology Corporation | Balancing amplitude and phase |
| WO2001091395A1 (en) * | 2000-05-22 | 2001-11-29 | Sicom, Inc. | Digital communication receiver with digital, if, i-q balancer |
| US20030072393A1 (en) * | 2001-08-02 | 2003-04-17 | Jian Gu | Quadrature transceiver substantially free of adverse circuitry mismatch effects |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008089841A1 (en) * | 2007-01-22 | 2008-07-31 | Freescale Semiconductor, Inc. | Calibration signal generator |
| US8976849B2 (en) | 2007-01-22 | 2015-03-10 | Freescale Semiconductor, Inc. | Calibration signal generator |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0314202D0 (en) | 2003-07-23 |
| GB2406984B (en) | 2005-12-21 |
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| COOA | Change in applicant's name or ownership of the application |
Owner name: FREESCALE SEMICONDUCTOR INC. Free format text: FORMER APPLICANT(S): MOTOROLA INC |
|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20150618 |