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GB2401967B - Dual cache system - Google Patents

Dual cache system

Info

Publication number
GB2401967B
GB2401967B GB0415701A GB0415701A GB2401967B GB 2401967 B GB2401967 B GB 2401967B GB 0415701 A GB0415701 A GB 0415701A GB 0415701 A GB0415701 A GB 0415701A GB 2401967 B GB2401967 B GB 2401967B
Authority
GB
United Kingdom
Prior art keywords
cache system
dual cache
dual
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0415701A
Other versions
GB2401967A (en
GB0415701D0 (en
Inventor
Zeev Sperber
Jack D Doweck
Nicolas Kacevas
Roy Nesher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/474,782 external-priority patent/US6397297B1/en
Application filed by Intel Corp filed Critical Intel Corp
Publication of GB0415701D0 publication Critical patent/GB0415701D0/en
Publication of GB2401967A publication Critical patent/GB2401967A/en
Application granted granted Critical
Publication of GB2401967B publication Critical patent/GB2401967B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
GB0415701A 1999-12-30 2000-11-07 Dual cache system Expired - Fee Related GB2401967B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/474,782 US6397297B1 (en) 1999-12-30 1999-12-30 Dual cache with multiple interconnection operation modes
GB0213515A GB2372858B (en) 1999-12-30 2000-11-07 Dual cache with multiple interconnection operation modes

Publications (3)

Publication Number Publication Date
GB0415701D0 GB0415701D0 (en) 2004-08-18
GB2401967A GB2401967A (en) 2004-11-24
GB2401967B true GB2401967B (en) 2005-01-05

Family

ID=33312355

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0415701A Expired - Fee Related GB2401967B (en) 1999-12-30 2000-11-07 Dual cache system

Country Status (1)

Country Link
GB (1) GB2401967B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0437712A2 (en) * 1990-01-18 1991-07-24 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. Tandem cache memory
US5285323A (en) * 1990-10-05 1994-02-08 Digital Equipment Corporation Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
US5974511A (en) * 1997-03-31 1999-10-26 Sun Microsystems, Inc. Cache subsystem with pseudo-packet switch
EP1109102A2 (en) * 1994-11-09 2001-06-20 Sony Electronics Inc. Memory system comprising multiple memory devices and memory access method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
EP0437712A2 (en) * 1990-01-18 1991-07-24 BULL HN INFORMATION SYSTEMS ITALIA S.p.A. Tandem cache memory
US5285323A (en) * 1990-10-05 1994-02-08 Digital Equipment Corporation Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
EP1109102A2 (en) * 1994-11-09 2001-06-20 Sony Electronics Inc. Memory system comprising multiple memory devices and memory access method
US5974511A (en) * 1997-03-31 1999-10-26 Sun Microsystems, Inc. Cache subsystem with pseudo-packet switch

Also Published As

Publication number Publication date
GB2401967A (en) 2004-11-24
GB0415701D0 (en) 2004-08-18

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20151107