GB2472565A

GB2472565A - Increasing the speed of measurements in an instrument

Info

Publication number: GB2472565A
Application number: GB0910222A
Authority: GB
Inventors: Gery Verhaegen; Tom Vandeplas
Original assignee: Agilent Technologies Inc
Current assignee: Agilent Technologies Inc
Priority date: 2009-06-13
Filing date: 2009-06-13
Publication date: 2011-02-16
Anticipated expiration: 2029-06-13
Also published as: GB2472565B; GB0910222D0

Abstract

A system and method for increasing the speed of measurements in an instrument, such as a high speed oscilloscope. Measurement speed is increased by provide a dedicated co-processor, such as a Graphics Processing Unit (GPU) 38, to handle measurement algorithms. As a result the host processor (CPU) 36, which takes care of the user interface 37, does not have to treat large amounts of raw measurement data and only needs to display the results of calculations performed by the co-processor. Raw data is also only transferred over a wider data bus.

Description

SYSTEM ND METHOD FOR INCREASING THE SPEED OF MEASUREMENTS

IN N INSTRUMENT

Field of the invention

(0001] The present invention relates to a system which increases the speed of measurements within an instrument. Furthermore, the present invention relates to a method which increases the speed of measurement within an instrument.

State of the art (0002] As shown in figure 1, current instruments such as an oscilloscope, capture analog waveforms 1 by means of a high-speed analogue-to-digital converter (ADC) 2 running at several Giga-samples per second. The memory controller 3 distributes the data stream from the ADC over several memory chips 4 trading sample speed for bus width because the memory cannot run at the same frequency as the ADC but it can handle the same throughput at a lower frequency using a wider data bus. The digital representation of the signal is then stored in a high-speed memory 4. When the instrument finishes capturing the signal, either when the memory is full or a preset memory limit has been reached, the data is read from memory 4 by the controller 3. Via the bus switch 5 the data is transferred to the host processor 6, which performs measurements on the signal and displays the results and waveforms on a screen 7. The transfer to the host processor occurs at a small fraction of the capture speed, thus forming a bottleneck which slows down the whole measurement process. The speed decrease occurs when controller 3 reads from the memory 4 and interfaces through the bus switch 5 to the host processor 6.

Furthermore, in a typical instrument the measurement will be performed by a traditional CISC or RISC processor, which is also running an operating system and a graphical user interface. As this host processor must take care of the measurements, the display, and the user interface, its speed is adversely affected. In addition, with increasing sample rates and capture memory depths, the amount of data that needs to be handled is becoming so large that the operation of current instruments is becoming prohibitively slow.

Aims of the invention (0003] The above mentioned technical problems are addresses by the present invention by providing a system and method for increasing the speed of the measurement process in a high-speed data acquisition system.

Furthermore, the present invention aims to remove the bottlenecks that exist between the acquisition unit and the host processor (Cpu), as well as free up the host processor from its measurement tasks.

Summary of the invention

[0004] The present invention provides a system and method for increasing measurement speed as set forth in the claims that follow.

By executing measurement algorithms on a dedicated co-processor, such as a Graphics Processing unit (GPU), which is used as general purpose measurement processor, measurement speed is increased. As a result the host processor (CPU) that takes care of the user interface does not have to treat large amounts of raw measurement data and only needs to display the results of calculations performed by the co-processor (GPU).

Furthermore, by passing the raw data directly to the co-processor (GPU), the bottlenecks that existed between the acquisition unit and the host processor (CPU) is eliminated.

Short description of the drawings

While the principle advantages and features of the invention have been described above, a greater understanding and appreciation of the invention may be obtained by referring to the drawings and detailed description of various embodiments of the present the invention, presented by way of example only, in which; Figure 2 represents a block diagram an embodiment of the present invention showing architecture of a data acquisition system, such as an oscilloscope with higher data throughput; and Figure 3 represents a block diagram of a further embodiment of the present invention.

Detailed description of the invention

[0005] Figure 2 shows the architecture of a data acquisition system, such as an oscilloscope with higher data throughput, according to the present invention. In this embodiment the signal flow is identical that shown and described in the known architecture shown in figure 1 up to the point where data is read from the acquisition memory 4.

However, according to the present invention, the acquired data is read out over a wider bus than in figure 1, thus speeding up the read path. Furthermore, this data is not transferred to the host processor 26 but rather to the local memory 29 of a GPU 28, which contains >100 parallel processing units. The bus width matches the throughput that the GPU can handle over its external interface bus (e.g. 16 lanes PCI Express) . The measurements are performed by the GPU an order of magnitude faster than what is possible on the CPU. To take full advantage of the parallel architecture the measurement algorithms need to be implemented with this parallelism in mind. Once the GPU finishes the measurements, only the waveform image and the measurement results will be transferred to the host processor 26 for display. This transfer can happen on a lower speed bus since the amount of data is vastly reduced.

For signal measurements only the measurement results are transferred to the host processor rather than the entire sample memory content. For visualization only the number of samples that can be represented on the screen 27 needs to be transferred to the host processor since all pre-processing already occurred in the GPU.

Advantageously, the measurement throughput of an acquisition system according to the present is increased by performing most of the measurement algorithms on a GPU rather than on the traditional Windows or Linux host processor. The GPU is used as a math-intensive co-processor, freeing the host processor (CPU) from measurement calculations on large data sets. The GPU gets access to the acquired data through a point-to-point link without intervention from the CPU, other than setting up the transfer. The data moves from the memory 4 through the controller 3 and reaches the GPU 28 through the bus switch 25. This reduces the time to transfer the data. The GPU then performs the requested measurements on the signal and subsequently transfers the results to the host CPU. The amount of data to be moved to the host CPU is thereby reduced by an order of magnitude. The rate at which data can be transferred in and out of the GPU memory is limited by the available I/O bandwidth of the GPU.

[0006] Figure 3 shows a block diagram of an alternative embodiment of the present invention. In this embodiment the signal flow is identical that shown and described in the known architecture shown in figure 1 up to the point where data is transferred from the controller 3 to the acquisition memory 34. This embodiment advantageously removes a bottleneck which still exists in the embodiment shown in figure 2. Here the acquisition memory 34 is shared between the memory controller 3 and the GPU 38. While the signal is being captured, the controller takes ownership of the memory forcing the GPU to release it hence the GPU cannot access it while a data acquisition takes place. After the acquisition is done the memory is under control of the GPU and data can be accessed an order of magnitude faster than what would be possible over the GPU I/O bus. This is typically a PCI-Express bus connecting the GPU 38 to the bus switch 35. The PCI-Express bus can still be made available for external access 39 in case customers want to apply proprietary algorithms on the raw acquisition data. The number of lanes on this PCI-Express connection can be tailored to the needs and the cost of the instrument.

A further advantage of the embodiment shown in figure 3 is that the acquisition memory 34 is shared between the memory controller 3 and the GPU 38. This avoids transferring the data over a slower link, such as in figure 2, from the acquisition memory 4 via memory controller 3 and the bus switch 25 to the GPU 28 into the memory 29. In figure 3 the memories 4 and 29 of figure 2 have been combined into one memory 34.

By sharing the acquisition memory with the GPU, the GPU I/O bottleneck is effectively eliminating, thus taking full advantage of the GPU memory bandwidth.

A further advantage is realized in that by reducing the transfer time between acquisition memory and the processing unit the time between successive triggers becomes smaller.

The effective time that the system will be ready to accept triggers will increase by an order of magnitude. This advantage occurs in both the embodiments discussed above, with and without dual port shared memory. However, the system with dual-port shared memory will show the fastest response time.

Examples of the types of measurements performed by such data acquisitions systems as shown in figures 2 and 3 are: FFTs, histograms, filtering, averaging and jitter measurements.

The present invention is particularly advantageous for modern high-speed oscilloscopes where data sets are often large (>1 Giga samples) It is not intended that the present invention be limited to the above embodiments and other modifications and variations are envisaged within the scope of the claims.

Claims

CLAIMS1. A system for increasing measurement speed in an instrument comprising means for receiving a signal and converting the signal to a digital format, a means for storing the converted signal, a first processor arranged to manipulate the converted signal and output a result to a second processor, the second processor arranged to display the result.
2. A system as claimed in claim 1, wherein the first processor is further arranged to perform measurements on the converted signal, the signal having a data set with > 1 Giga samples.
3. A system as claimed in claim 2, wherein the first processor is further arranged to perform jitter measurements on the converted signal.
4. A system as claimed in any preceding claim, wherein the second processor is further arranged to run an instrument operating system.
5. A system as claimed in any preceding claim, wherein the first process is a graphic processing unit.
6. A system as claimed in any preceding claim, wherein the second processor is central processing unit.
7. A system as claimed in any preceding claim, wherein the means for storing the converted signal is further coupled to both a memory controller and the first processor in order to further enhance the speed of the system.
8. A system as claimed in any preceding claim, wherein the means for storing the converted signal is further coupled to the second processor in order to facilitate displaying of the results.
9. An integrated circuit comprising a system as claimed in any preceding claim.
10. An instrument comprising an integrated circuit as claimed in claim 9.
11. An instrument as claimed in claim 10 wherein the instrument is a high speed oscilloscope.
12. A method for increasing the measurement speed in an instrument, the method comprising the steps of: receiving a signal, converting the signal to a digital format, storing the converted signal in a storage means, arranging a first processor to manipulate the converted signal and output the manipulated signal as a result to a second processor, and arranging said second processor to display the result.
13. A method as claimed in claim 12 comprising the further step of arranging the storage means to communicate with both a memory controller and the first processor, thereby further enhancing the measurement speed of the instrument.
14. A method as claimed in claim 12 comprising the further step of arranging the storage means to communicate with both the first processor and the second processor, thereby facilitating displaying of the result.