GB2471833B - Under land routing - Google Patents
Under land routingInfo
- Publication number
- GB2471833B GB2471833B GB0911767.2A GB0911767A GB2471833B GB 2471833 B GB2471833 B GB 2471833B GB 0911767 A GB0911767 A GB 0911767A GB 2471833 B GB2471833 B GB 2471833B
- Authority
- GB
- United Kingdom
- Prior art keywords
- rdl
- layers
- ubm
- tracks
- routing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H10W20/40—
-
- H10W20/49—
-
- H10W70/60—
-
- H10W70/635—
-
- H10W72/00—
-
- H10W70/65—
-
- H10W70/654—
-
- H10W70/656—
-
- H10W70/69—
-
- H10W72/01223—
-
- H10W72/01225—
-
- H10W72/252—
-
- H10W72/29—
-
- H10W72/9223—
-
- H10W72/923—
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
An electronic component of a Wafer Level Chip Scale Package (WLCSP) comprises an integrated device and a plurality of packaging layers in which routing between bond pad locations on the device (fig 1; 105) and solder ball lands 300 on the surface of the component in an under ball metallization layer (UBM) is provided by tracks 305 in an intermediate metallic redistribution layer (RDL) 310, 311. Vias allow electrical connection between the UBM and RDL layers, and the RDL and device bond pad layers. The RDL tracks may be routed below the extent of a solder ball land by providing a channel 304 through both the via 302, 303 and redistribution layer 310, 311 underneath the land.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0911767.2A GB2471833B (en) | 2009-07-07 | 2009-07-07 | Under land routing |
| TW098124713A TWI487078B (en) | 2009-07-07 | 2009-07-22 | Arrangement routing technology below the connection area |
| US12/829,745 US8368224B2 (en) | 2009-07-07 | 2010-07-02 | Under land routing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0911767.2A GB2471833B (en) | 2009-07-07 | 2009-07-07 | Under land routing |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0911767D0 GB0911767D0 (en) | 2009-08-19 |
| GB2471833A GB2471833A (en) | 2011-01-19 |
| GB2471833B true GB2471833B (en) | 2013-05-15 |
Family
ID=41022269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0911767.2A Active GB2471833B (en) | 2009-07-07 | 2009-07-07 | Under land routing |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB2471833B (en) |
| TW (1) | TWI487078B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060022350A1 (en) * | 2004-07-29 | 2006-02-02 | Watkins Charles M | Integrated circuit and methods of redistributing bondpad locations |
| US20060292711A1 (en) * | 2005-06-28 | 2006-12-28 | Peng Su | Mechanical integrity evaluation of low-k devices with bump shear |
| US20070052092A1 (en) * | 2005-09-02 | 2007-03-08 | Ching-Hung Kao | Interconnection structure |
| US20070063352A1 (en) * | 2005-09-21 | 2007-03-22 | Agere Systems Inc. | Routing under bond pad for the replacement of an interconnect layer |
| US20080001296A1 (en) * | 2005-04-18 | 2008-01-03 | Chao-Chun Tu | Bond pad structures and semiconductor devices using the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7122458B2 (en) * | 2004-07-22 | 2006-10-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for fabricating pad redistribution layer |
| US20080083980A1 (en) * | 2006-10-06 | 2008-04-10 | Advanced Chip Engineering Technology Inc. | Cmos image sensor chip scale package with die receiving through-hole and method of the same |
| US20080157303A1 (en) * | 2006-12-28 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Structure of super thin chip scale package and method of the same |
-
2009
- 2009-07-07 GB GB0911767.2A patent/GB2471833B/en active Active
- 2009-07-22 TW TW098124713A patent/TWI487078B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060022350A1 (en) * | 2004-07-29 | 2006-02-02 | Watkins Charles M | Integrated circuit and methods of redistributing bondpad locations |
| US20080001296A1 (en) * | 2005-04-18 | 2008-01-03 | Chao-Chun Tu | Bond pad structures and semiconductor devices using the same |
| US20060292711A1 (en) * | 2005-06-28 | 2006-12-28 | Peng Su | Mechanical integrity evaluation of low-k devices with bump shear |
| US20070052092A1 (en) * | 2005-09-02 | 2007-03-08 | Ching-Hung Kao | Interconnection structure |
| US20070063352A1 (en) * | 2005-09-21 | 2007-03-22 | Agere Systems Inc. | Routing under bond pad for the replacement of an interconnect layer |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201103110A (en) | 2011-01-16 |
| GB0911767D0 (en) | 2009-08-19 |
| GB2471833A (en) | 2011-01-19 |
| TWI487078B (en) | 2015-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103165585B (en) | The stacked package of wafer is reproduced in use | |
| WO2008131395A3 (en) | Solder bump interconnect for improved mechanical and thermo mechanical performance | |
| WO2012061381A3 (en) | Crack arrest vias for ic devices | |
| TW200737482A (en) | Stack package utilizing through vias and re-distribution lines | |
| MY151533A (en) | Substrate and process for semiconductor flip chip package | |
| TW200605242A (en) | Wafer-level chip scale packaging method | |
| SG142340A1 (en) | Package-in-package using through-hole via die on saw streets | |
| SG152979A1 (en) | Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures | |
| SG151167A1 (en) | Semiconductor die with through-hole via on saw streets and through-hole via in active area of die | |
| TWI319223B (en) | Die down ball grid array packages and method for making same | |
| TW200729366A (en) | Bump with multiple vias for semiconductor package, method of fabrication method thereof, and semiconductor package using the same | |
| US20150214170A1 (en) | Semiconductor device with bump stop structure | |
| SG153718A1 (en) | System and apparatus for wafer level integration of components | |
| WO2007127816A3 (en) | Method for forming c4 connections on integrated circuit chips and the resulting devices | |
| TW200729439A (en) | Bond pad structure and method of forming the same | |
| TW200509346A (en) | Flip-chip package, semiconductor chip with bumps, and method for manufacturing semiconductor chip with bumps | |
| TW200733270A (en) | Redistribution layer for wafer-level chip scale package and method therefor | |
| TW200629493A (en) | A routing design to minimize electromigration damage to solder bumps | |
| TWI265582B (en) | Various structure/height bumps for wafer level-chip scale package | |
| GB2471833B (en) | Under land routing | |
| TW200719419A (en) | Wafer structure and method for fabricating the same | |
| SG136004A1 (en) | Semiconductor constructions having interconnect structures, methods of forming interconnect structures, and methods of forming semiconductor constructions | |
| TW200629438A (en) | Chip structure with bumps and testing pads | |
| TW200737465A (en) | A semiconductor connection package for an integrated circuit, a method of connecting a semiconductor connection package to an integrated circuit and an apparatus | |
| SG124339A1 (en) | Under bump metallurgy in integrated circuits |