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GB2465419B - Random number generator circuits - Google Patents

Random number generator circuits

Info

Publication number
GB2465419B
GB2465419B GB0821230.0A GB0821230A GB2465419B GB 2465419 B GB2465419 B GB 2465419B GB 0821230 A GB0821230 A GB 0821230A GB 2465419 B GB2465419 B GB 2465419B
Authority
GB
United Kingdom
Prior art keywords
input
output
block
data processing
random
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0821230.0A
Other versions
GB2465419A (en
GB0821230D0 (en
Inventor
Simon Banks
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SIMBA HPC Ltd
Original Assignee
SIMBA HPC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SIMBA HPC Ltd filed Critical SIMBA HPC Ltd
Priority to GB0821230.0A priority Critical patent/GB2465419B/en
Publication of GB0821230D0 publication Critical patent/GB0821230D0/en
Publication of GB2465419A publication Critical patent/GB2465419A/en
Application granted granted Critical
Publication of GB2465419B publication Critical patent/GB2465419B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/586—Pseudo-random number generators using an integer algorithm, e.g. using linear congruential method
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Security & Cryptography (AREA)
  • Complex Calculations (AREA)

Abstract

The invention relates to hardware architectures for random number generators. We describe a random number generator hardware architecture, comprising: at least one random seed input for providing a plurality of random seeds; a select block having first and second inputs and an output, said first input being coupled to said random seed input; a pipelined data processing block having an input coupled to said select block output and having a feedback path in which a feedback output from said pipelined data processing block is fed back to said second input of said select block, and having a random data output; and a control unit to control said select block to couple said first input of said select block to said select block output to load said plurality of random seeds into successive pipeline stages of said pipelined data processing block, and to then couple said second input of said select block to said select block output to feedback data output from said pipelined data processing block to said input of said pipelined data processing block.
GB0821230.0A 2008-11-20 2008-11-20 Random number generator circuits Active GB2465419B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0821230.0A GB2465419B (en) 2008-11-20 2008-11-20 Random number generator circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0821230.0A GB2465419B (en) 2008-11-20 2008-11-20 Random number generator circuits

Publications (3)

Publication Number Publication Date
GB0821230D0 GB0821230D0 (en) 2008-12-31
GB2465419A GB2465419A (en) 2010-05-26
GB2465419B true GB2465419B (en) 2013-12-11

Family

ID=40230572

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0821230.0A Active GB2465419B (en) 2008-11-20 2008-11-20 Random number generator circuits

Country Status (1)

Country Link
GB (1) GB2465419B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016082142A1 (en) * 2014-11-27 2016-06-02 华为技术有限公司 Rate matching method and apparatus for polar code, and wireless communication device
CN115437603B (en) * 2021-06-04 2023-12-19 中科寒武纪科技股份有限公司 Method for generating random numbers and related products

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5983252A (en) * 1997-01-17 1999-11-09 Picturetel Corporation Pseudo-random number generator capable of efficiently exploiting processors having instruction-level parallelism and the use thereof for encryption
US20040064491A1 (en) * 2002-09-30 2004-04-01 Rarick Leonard D. Continuous random number generation method and apparatus
WO2009074889A1 (en) * 2007-12-12 2009-06-18 Nds Limited Bit generator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5983252A (en) * 1997-01-17 1999-11-09 Picturetel Corporation Pseudo-random number generator capable of efficiently exploiting processors having instruction-level parallelism and the use thereof for encryption
US20040064491A1 (en) * 2002-09-30 2004-04-01 Rarick Leonard D. Continuous random number generation method and apparatus
WO2009074889A1 (en) * 2007-12-12 2009-06-18 Nds Limited Bit generator

Also Published As

Publication number Publication date
GB2465419A (en) 2010-05-26
GB0821230D0 (en) 2008-12-31

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