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GB2462014B - Optimization of organic packaging interconnect for gigabit signalling - Google Patents

Optimization of organic packaging interconnect for gigabit signalling

Info

Publication number
GB2462014B
GB2462014B GB0915781A GB0915781A GB2462014B GB 2462014 B GB2462014 B GB 2462014B GB 0915781 A GB0915781 A GB 0915781A GB 0915781 A GB0915781 A GB 0915781A GB 2462014 B GB2462014 B GB 2462014B
Authority
GB
United Kingdom
Prior art keywords
gigabit
signalling
optimization
organic packaging
packaging interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0915781A
Other versions
GB0915781D0 (en
GB2462014A (en
Inventor
Amarjit Singh Bhandal
Brian Young
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GBGB0709792.6A external-priority patent/GB0709792D0/en
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Publication of GB0915781D0 publication Critical patent/GB0915781D0/en
Publication of GB2462014A publication Critical patent/GB2462014A/en
Application granted granted Critical
Publication of GB2462014B publication Critical patent/GB2462014B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H10W70/685—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H10W44/601—
    • H10W70/635—
    • H10W90/701—
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
GB0915781A 2007-05-22 2009-09-09 Optimization of organic packaging interconnect for gigabit signalling Active GB2462014B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0709792.6A GB0709792D0 (en) 2007-05-22 2007-05-22 Optimization of organic packaging interconnect for gigabit signalling
GB0716790A GB2449508B (en) 2007-05-22 2007-08-31 Optimization of organic packaging interconnect for gigabit signalling

Publications (3)

Publication Number Publication Date
GB0915781D0 GB0915781D0 (en) 2009-10-07
GB2462014A GB2462014A (en) 2010-01-27
GB2462014B true GB2462014B (en) 2010-06-09

Family

ID=41479343

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0915781A Active GB2462014B (en) 2007-05-22 2009-09-09 Optimization of organic packaging interconnect for gigabit signalling

Country Status (1)

Country Link
GB (1) GB2462014B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060207790A1 (en) * 2005-03-15 2006-09-21 Jayoung Choi Bonding pads having slotted metal pad and meshed via pattern

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060207790A1 (en) * 2005-03-15 2006-09-21 Jayoung Choi Bonding pads having slotted metal pad and meshed via pattern

Also Published As

Publication number Publication date
GB0915781D0 (en) 2009-10-07
GB2462014A (en) 2010-01-27

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