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GB2456202B - A digital circuit on a semiconductor chip with a plurality of macro circuits and a clock gating system - Google Patents

A digital circuit on a semiconductor chip with a plurality of macro circuits and a clock gating system

Info

Publication number
GB2456202B
GB2456202B GB0821970.1A GB0821970A GB2456202B GB 2456202 B GB2456202 B GB 2456202B GB 0821970 A GB0821970 A GB 0821970A GB 2456202 B GB2456202 B GB 2456202B
Authority
GB
United Kingdom
Prior art keywords
semiconductor chip
digital circuit
clock gating
gating system
macro circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0821970.1A
Other versions
GB0821970D0 (en
GB2456202A (en
Inventor
Guenter Gerwig
Frank Lehnert
Ulrich Mayer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB0821970D0 publication Critical patent/GB0821970D0/en
Publication of GB2456202A publication Critical patent/GB2456202A/en
Application granted granted Critical
Publication of GB2456202B publication Critical patent/GB2456202B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
GB0821970.1A 2008-01-09 2008-12-02 A digital circuit on a semiconductor chip with a plurality of macro circuits and a clock gating system Active GB2456202B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08100283 2008-01-09

Publications (3)

Publication Number Publication Date
GB0821970D0 GB0821970D0 (en) 2009-01-07
GB2456202A GB2456202A (en) 2009-07-08
GB2456202B true GB2456202B (en) 2012-10-17

Family

ID=40262518

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0821970.1A Active GB2456202B (en) 2008-01-09 2008-12-02 A digital circuit on a semiconductor chip with a plurality of macro circuits and a clock gating system

Country Status (1)

Country Link
GB (1) GB2456202B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8671380B2 (en) 2011-07-18 2014-03-11 Apple Inc. Dynamic frequency control using coarse clock gating
CN120560489B (en) * 2025-07-30 2025-10-14 沐曦集成电路(上海)股份有限公司 Processing method of multi-granularity gating clock, electronic equipment and medium

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5603037A (en) * 1993-04-23 1997-02-11 Intel Corporation Clock disable circuit for translation buffer
US5677849A (en) * 1993-11-08 1997-10-14 Cirrus Logic, Inc. Selective low power clocking apparatus and method
EP0855639A1 (en) * 1996-12-27 1998-07-29 Pacific Communication Sciences, Inc. Gated-clock registers for low-power circuitry
US6536024B1 (en) * 2000-07-14 2003-03-18 International Business Machines Corporation Method for making integrated circuits having gated clock trees
EP1486857A2 (en) * 2003-06-12 2004-12-15 Agilent Technologies, Inc. Method and apparatus for clock gating clock trees to reduce power dissipation
US20040257139A1 (en) * 2003-06-18 2004-12-23 Shelor Charles F. Hierarchical clock gating circuit and method
US20070074054A1 (en) * 2005-09-27 2007-03-29 Chieh Lim S Clock gated pipeline stages

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5603037A (en) * 1993-04-23 1997-02-11 Intel Corporation Clock disable circuit for translation buffer
US5677849A (en) * 1993-11-08 1997-10-14 Cirrus Logic, Inc. Selective low power clocking apparatus and method
EP0855639A1 (en) * 1996-12-27 1998-07-29 Pacific Communication Sciences, Inc. Gated-clock registers for low-power circuitry
US6536024B1 (en) * 2000-07-14 2003-03-18 International Business Machines Corporation Method for making integrated circuits having gated clock trees
EP1486857A2 (en) * 2003-06-12 2004-12-15 Agilent Technologies, Inc. Method and apparatus for clock gating clock trees to reduce power dissipation
US20040257139A1 (en) * 2003-06-18 2004-12-23 Shelor Charles F. Hierarchical clock gating circuit and method
US20070074054A1 (en) * 2005-09-27 2007-03-29 Chieh Lim S Clock gated pipeline stages

Also Published As

Publication number Publication date
GB0821970D0 (en) 2009-01-07
GB2456202A (en) 2009-07-08

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Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20121029