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GB2454597B - A method for checking the reliability of a memory for a receiving data packet in a data array within a data receiving logic circuit - Google Patents

A method for checking the reliability of a memory for a receiving data packet in a data array within a data receiving logic circuit

Info

Publication number
GB2454597B
GB2454597B GB0821855.4A GB0821855A GB2454597B GB 2454597 B GB2454597 B GB 2454597B GB 0821855 A GB0821855 A GB 0821855A GB 2454597 B GB2454597 B GB 2454597B
Authority
GB
United Kingdom
Prior art keywords
data
receiving
checking
reliability
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0821855.4A
Other versions
GB0821855D0 (en
GB2454597A (en
Inventor
Markus Helms
Thomas Schlipf
Daniel Sentler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB0821855D0 publication Critical patent/GB0821855D0/en
Publication of GB2454597A publication Critical patent/GB2454597A/en
Application granted granted Critical
Publication of GB2454597B publication Critical patent/GB2454597B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9021—Plurality of buffers per packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04L12/5694—

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
GB0821855.4A 2008-01-03 2008-12-01 A method for checking the reliability of a memory for a receiving data packet in a data array within a data receiving logic circuit Active GB2454597B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP08100040 2008-01-03

Publications (3)

Publication Number Publication Date
GB0821855D0 GB0821855D0 (en) 2009-01-07
GB2454597A GB2454597A (en) 2009-05-13
GB2454597B true GB2454597B (en) 2012-01-18

Family

ID=40262416

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0821855.4A Active GB2454597B (en) 2008-01-03 2008-12-01 A method for checking the reliability of a memory for a receiving data packet in a data array within a data receiving logic circuit

Country Status (1)

Country Link
GB (1) GB2454597B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995014269A1 (en) * 1993-11-19 1995-05-26 The Trustees Of The University Of Pennsylvania A high-performance host interface for networks carrying connectionless traffic
US6832261B1 (en) * 2001-02-04 2004-12-14 Cisco Technology, Inc. Method and apparatus for distributed resequencing and reassembly of subdivided packets
WO2007115199A2 (en) * 2006-03-31 2007-10-11 Qualcomm Incorporated Memory management for high speed media access control

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995014269A1 (en) * 1993-11-19 1995-05-26 The Trustees Of The University Of Pennsylvania A high-performance host interface for networks carrying connectionless traffic
US6832261B1 (en) * 2001-02-04 2004-12-14 Cisco Technology, Inc. Method and apparatus for distributed resequencing and reassembly of subdivided packets
WO2007115199A2 (en) * 2006-03-31 2007-10-11 Qualcomm Incorporated Memory management for high speed media access control

Also Published As

Publication number Publication date
GB0821855D0 (en) 2009-01-07
GB2454597A (en) 2009-05-13

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Legal Events

Date Code Title Description
746 Register noted 'licences of right' (sect. 46/1977)

Effective date: 20130107