[go: up one dir, main page]

GB2440881A - Technique for forming copper-containing lines embedded in low-K dielectric by providing a stiffening layer - Google Patents

Technique for forming copper-containing lines embedded in low-K dielectric by providing a stiffening layer Download PDF

Info

Publication number
GB2440881A
GB2440881A GB0723101A GB0723101A GB2440881A GB 2440881 A GB2440881 A GB 2440881A GB 0723101 A GB0723101 A GB 0723101A GB 0723101 A GB0723101 A GB 0723101A GB 2440881 A GB2440881 A GB 2440881A
Authority
GB
United Kingdom
Prior art keywords
low
providing
stiffening layer
dielectric
technique
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB0723101A
Other versions
GB0723101D0 (en
Inventor
Peter Huebler
Frank Koschinsky
Frank Feustel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE102005024912A external-priority patent/DE102005024912A1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0723101D0 publication Critical patent/GB0723101D0/en
Publication of GB2440881A publication Critical patent/GB2440881A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H10W20/033—
    • H10W20/043—
    • H10W20/044—
    • H10W20/076—
    • H10W20/081—
    • H10W20/082—
    • H10W20/084—
    • H10W20/095—
    • H10W20/096—
    • H10W20/097—
    • H10W20/425—
    • H10W20/47—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

By providing a stiffening layer (105) at three sidewalls (1055) of a trench (104) to be filled with a copper-containing metal, the reduced thermomechanical confinement of a low-k material (102) may be compensated for, at least to a certain degree, thereby reducing electromigration effects and hence increasing lifetime of sophisticated semiconductor devices having metallization layers including low-k dielectric materials (102) in combination with copper-based metal lines.
GB0723101A 2005-05-31 2006-04-19 Technique for forming copper-containing lines embedded in low-K dielectric by providing a stiffening layer Withdrawn GB2440881A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102005024912A DE102005024912A1 (en) 2005-05-31 2005-05-31 A technique of making copper-containing leads embedded in a low-k dielectric by providing a stiffening layer
US11/295,756 US20060267201A1 (en) 2005-05-31 2005-12-07 Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layer
PCT/US2006/014624 WO2006130250A1 (en) 2005-05-31 2006-04-19 Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layer

Publications (2)

Publication Number Publication Date
GB0723101D0 GB0723101D0 (en) 2008-01-02
GB2440881A true GB2440881A (en) 2008-02-13

Family

ID=36763116

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0723101A Withdrawn GB2440881A (en) 2005-05-31 2006-04-19 Technique for forming copper-containing lines embedded in low-K dielectric by providing a stiffening layer

Country Status (2)

Country Link
GB (1) GB2440881A (en)
WO (1) WO2006130250A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113539945B (en) * 2020-04-16 2023-09-29 长鑫存储技术有限公司 Semiconductor structures and methods of forming them

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010000115A1 (en) * 1999-09-29 2001-04-05 Greco Stephen E. Dual damascene flowable oxide insulation structure and metallic barrier
US20020022280A1 (en) * 2000-03-17 2002-02-21 Advanced Micro Devices Inc Repair of film having an si-o backbone
US20020081834A1 (en) * 2000-12-26 2002-06-27 Honeywell International Inc. Method for eliminating reaction between photoresist and OSG
US6559548B1 (en) * 1999-03-19 2003-05-06 Kabushiki Kaisha Toshiba Wiring structure of semiconductor device
EP1324383A2 (en) * 2001-12-26 2003-07-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20050003656A1 (en) * 2002-08-21 2005-01-06 Jin-Sung Chung Metal interconnections for semiconductor devices including a buffer layer on a trench sidewall

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559548B1 (en) * 1999-03-19 2003-05-06 Kabushiki Kaisha Toshiba Wiring structure of semiconductor device
US20010000115A1 (en) * 1999-09-29 2001-04-05 Greco Stephen E. Dual damascene flowable oxide insulation structure and metallic barrier
US20020022280A1 (en) * 2000-03-17 2002-02-21 Advanced Micro Devices Inc Repair of film having an si-o backbone
US20020081834A1 (en) * 2000-12-26 2002-06-27 Honeywell International Inc. Method for eliminating reaction between photoresist and OSG
EP1324383A2 (en) * 2001-12-26 2003-07-02 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20050003656A1 (en) * 2002-08-21 2005-01-06 Jin-Sung Chung Metal interconnections for semiconductor devices including a buffer layer on a trench sidewall

Also Published As

Publication number Publication date
GB0723101D0 (en) 2008-01-02
WO2006130250A1 (en) 2006-12-07

Similar Documents

Publication Publication Date Title
TW200707641A (en) Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layer
TW200717712A (en) Technique for forming a copper-based metallization layer including a conductive capping layer
TW200616145A (en) 3D interconnect with protruding contacts
TWI256677B (en) Barrier material and process for Cu interconnect
GB2465127A (en) MOS structures that exhibit lower contact resistance and methods for fabricating the same
TW200739811A (en) Interconnect structure of an integrated circuit, damascene structure, semiconductor structure and fabrication methods thereof
WO2007012490A3 (en) Semiconductor component with a drift region and with a drift control region
TW200723521A (en) Metal oxide semiconductor devices and film structures and methods
WO2009019837A1 (en) Silicon carbide semiconductor device and method for producing the same
WO2008112064A3 (en) Light emitting devices having current reducing structures and methods of forming light emitting devices having current reducing structures
TW200705017A (en) Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating the thin film transistor substrate
TW200640325A (en) Wiring board manufacturing method
WO2009001780A1 (en) Semiconductor device and method for manufacturing the same
TW200735348A (en) Semiconductor heterostructure and method for forming a semiconductor heterostructure
TW200943483A (en) Interconnect structure and method for Cu/ultra low k integration
TW200746330A (en) Microelectronic assembly with back side metallization and method for forming the same
TW200731463A (en) A technique for increasing adhesion of metallization layers by providing dummy vias
WO2005071763A3 (en) Thin-film led comprising a current-dispersing structure
TW200731537A (en) Semiconductor device and manufacturing method thereof
TW200741893A (en) Shared contact structures for integrated circuits
TWI257122B (en) Semiconductor device and method for forming conductive path
TW200518228A (en) Semiconductor device and method of manufacturing the same
TW201613110A (en) Semiconductor device and manufacturing method of the same
GB2456479A (en) Semiconductor structure with interconnect comprising sliver and method of forming the same
TW200723448A (en) Interconnect structure and fabrication method thereof and semiconductor device

Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)